Utilizing Virtualized Hardware Logic Computations to Benefit Multi-User Performanceâ€
Round 1
Reviewer 1 Report
The paper is well written and well structured.
The conclusion (section 5.) could do with very short quantitative analysis, which recapitulates and sum up experimental results described in previous sections.
The only (probably) typing error is on page no. 2, line 62 - is "course-grained" instead of (probably) "coarse-grained".
Author Response
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Author Response File: 
Author Response.pdf
Reviewer 2 Report
This manuscript describes performance models on virtualized hardware logic using a queueing model, its discrete-event simulation, and logic simulation of hardware with scheduler. By the addition of a model and sample applications from the authors' previous work, the proposed models seem to become more convincing. The manuscript is basically well organized.
The reviewer has one question regarding the VHDL-based test system: why did the authors investigate scheduling algorithms only with logic simulation? The reviewer agree with the authors' view that logic design helps find out whether the secondary memory, multiplexer data path or control logic becomes the critical path (Issues 1 and 2 in p. 12). As software is generally more flexible than RTL (register transfer level) logic, we would learn more by implementing and evaluating the algorithms on discrete-event simulation. Is there some limitation in the simulation framework? Or will authors simply leave it as future work? Some comments or discussions are recommended.
Author Response
Please see the attachment.
Author Response File: Author Response.pdf
