# A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. The Proposed Solution

_{Pi}and M

_{Ni}, with i = 1, 2, … N and N an odd number greater than 3) are made accessible. An output capacitor, C

_{i}in the red-dashed box, is added at the output of each stage with the aim of setting the nominal oscillation frequency (coarse tuning), and to locally make the single stage insensible to parasitic capacitances, as will be clarified in the next section. The body potentials of both transistors, V

_{BP}and V

_{BN}, are generated from the auxiliary topology depicted in Figure 2, the aim of which is to establish the maximum current flowing in the reference inverter (M

_{PR}-M

_{NR}), i.e., when the input is at the logic threshold, V

_{DD}/2. For this purpose, in quiescent conditions, the input terminal of this reference inverter is set to V

_{DD}/2 and, thanks to the overall negative feedback implemented by error amplifier A

_{2}, such condition is transferred also to the output. Note that also the drain voltage of transistor M

_{PA}is kept to V

_{DD}/2 thanks to A

_{1}. This allows us to set the same nominal operating points for both M

_{PR}and M

_{PA}.

_{BP}for the p-channel transistors, and V

_{BN}for the n-channel ones. These voltages are generated by A

_{1}and A

_{2}, exploiting a technique proposed in [19] and utilized also in [21].

_{BIAS}, transistor M

_{PA}is forced to generate voltage V

_{BP}, which is also applied to M

_{PR}. Therefore, current I

_{BIAS}in M

_{PA}is mirrored by transistor M

_{PR}that, as already stated, together with M

_{NR}, constitutes the reference inverter. Note also that A

_{2}generates the required bulk voltages, V

_{BN}, for M

_{NR}to drive the same current of M

_{PR}under the constraints listed in the following:

- (a)
- assigned aspect ratios (W/L)
_{PA}, (W/L)_{PR}and (W/L)_{NR}; - (b)
- I
_{D,PR/NR}= kI_{BIAS}, where k = (W/L)_{PR}/(W/L)_{PA}; - (c)
- V
_{SG,PR}= V_{GS,NR}= V_{DD}/2; - (d)
- V
_{SD,P}_{R}= V_{DS,NR}= V_{DD}/2, assuming ideal input virtual short in A_{1}and A_{2}.

_{PR}and M

_{NR}must be set so that the required bulk voltages are within V

_{DD}and ground. Moreover, the mirroring error between the biasing branch and the reference one is reduced using a careful layout style.

_{1}and A

_{2}should provide a maximum (rail-to-rail) output voltage range, whereas input common mode range is not a concern as input voltage is kept constant to V

_{DD}/2. Therefore, simple symmetrical OTAs biased in subthreshold, can be effectively used. An example of implementation of this type of amplifier is found in [21,22], and is shown in Figure 3.

_{BN}and V

_{BP}are then applied to the inverters forming the ring oscillator in Figure 1, limiting at the desired value the maximum current flowing when the input voltage is equal to the threshold. Indeed, consider transistor M

_{N1}of the first inverter stage, the exploded view of which is depicted in the red-dashed box in Figure 1. Let us remember that, in quiescent conditions, V

_{IN1}is equal to V

_{DD}/2. Consequently, M

_{NR}and M

_{N1}have respectively the same source, gate, and bulk voltage and hence the drain current of M

_{N1}is related to that of M

_{NR}in a mirror-like condition:

_{N1}is also equal to V

_{DD}/2. Similar considerations hold for all the transistors in the ring oscillator, in practice, all p-channel and n-channel devices have their current linked to I

_{BIAS}via the current-mirror relations

_{Pi}and (W/L)

_{Ni}, with i = 1, 2, … N, are, respectively, the aspect ratios of the generic p-channel and n-channel MOSFET in the ring oscillator.

## 3. Small- and Large-Signal Analysis of the Proposed Ring Oscillator

_{T}= kT/q is the thermal voltage, with k the Boltzmann constant, T is the absolute temperature and C

_{OX}is the oxide capacitance for unit of area. In addition, λ

_{DS}is the channel modulation coefficient, L

_{ov}is the length of the overlap portion, C

_{Jp/n}is the capacitance of the S/D junctions (evaluated at the voltage V

_{DD}/2 in (4e)), m

_{j}is the grading coefficient and V

_{bi}is the built-in voltage.

_{m}(4) and the output resistance r

_{d}(5) yields a constant value, independent of the biasing current I

_{D}and equal to the maximum of the g

_{m}/I

_{D}curves [23]. In such case, only the channel modulation coefficient, λ

_{DS}/nV

_{T}, can be changed by sizing the transistors, in order to (slightly) change the inverter intrinsic gain (i.e., g

_{m}r

_{d}). Note that the drain-induced barrier lowering (DIBL) effect is included in the channel modulation coefficient through the parameter λ

_{DS}. Parasitic capacitance contribution accounts for three capacitances expressed in (6)–(8).

_{OX}and is constituted by a first term that depends on the MOSFET active areas and by the operating condition (assumed with MOSFETs in saturation) and a second term that depends on the overlap capacitance. A similar contribution forms the gate-to-drain equivalent capacitance, C

_{gd}, expressed in (7). The drain-to-bulk capacitance, unlike the previous two, is a non-linear capacitance which depends on S/D diffused areas (included in C

_{Jp/n}) and the applied voltage, i.e., the drain-to-bulk voltage. Referring to Figure 4a, both are evaluated in the quiescent point, i.e., at V

_{DD}/2, and, from Figure 4b, the output node results to be loaded by the sum of the capacitances (8) and the additional one, C.

_{db}on the oscillation frequency can be neglected if an additional capacitance, C, sufficiently large, is connected in parallel. Analysis of the complete ring oscillator leads to closed-loop gain and phase shift which satisfy Barkhausen’s criteria for the common pulsation, ω

_{p}, since the output node electrically coincides with the input one, therefore |H(jω

_{p})| = 1, and the a total phase shift of 180° is constantly achieved for an odd number of stages N. The result of these concurrent conditions ensures oscillation whose frequency is expressed by:

_{tot}gathers all the capacitive contributions (6), (7) doubled for Miller’s effect, (9) and C. It can be noted that, being the output small-signal resistance inversely proportional to the biasing current, I

_{D}, a proportional control of the oscillation frequency can be operated by varying the current itself. Various works presented in literature demonstrated that such kind of analysis is inaccurate when the number of stages exceeds 3, hence (10) is rarely used to design a ring oscillator.

_{PD}, and the frequency of the generated signal follows the expression:

_{PD}, where N is the number of inverters involved. For a digital gate, the propagation delay is defined as the time required to settle the output node to the middle of its dynamic range as referred to the instant of input changing. Henceforth, we call this approach digital or large-signal approach. While the simple relation in (11) and its scalability assuming general gate implementation are the strengths of this approach, evaluating τ

_{PD}could require a great deal of effort. Therefore, designers often adopt a trial-and-error approach.

_{ST0,N}(I

_{ST0,P}), defined as the potential sub-threshold current of the NMOS (PMOS) if the threshold voltage are nullified, and n are technology-dependent parameters, and V

_{TH,N}(V

_{TH,P}) are the threshold voltage of the involved transistors. In (12), the tailing effect of drain-to-source voltages is neglected because we assume that transistors are biased in saturation, i.e., V

_{DD}/2 > V

_{T}. Moreover, V

_{TH,N}(V

_{TH,P}) implicitly depends on V

_{BS,N}(V

_{SB,P}) through the body effect, as well as on V

_{DS,N}(V

_{SD,P}) through the DIBL effect. Their contributions are taken into account by expressing V

_{TH,N}= V

_{TH0,N}− λ

_{BS,N}V

_{BS,N}− λ

_{DS,N}V

_{DS,N}(|V

_{TH,P}| = |V

_{TH0,P}| − λ

_{BS,P}V

_{SB,P}− λ

_{SD,P}V

_{SD,P}) where V

_{TH0,N}(V

_{TH0,P}) and λ

_{BS,N}(λ

_{BS,P}) are two technology parameters, while λ

_{DS,N}(λ

_{SD,P}) coincides with that used in (5) [24]. It should be noted that, if (12) is fulfilled, the two transistors are equally strong, which means that for the same gate to source voltage they conduct the same current. Under the aforementioned considerations, a good approximation (typical error < 10%) for the propagation delay is given by [25]:

_{ST}|

_{VDD}

_{= 0}in order to be enucleated from the circuital parameters like voltages V

_{DD}, V

_{BN}, and V

_{BP}. Moreover, the total large-signal capacitance seen at the output node, C

_{TOT}, can be assumed to be equal to the small-signal one reported in (10). Finally, (13) has be re-written in the last simple form to highlight the biasing current, I

_{D}.

_{DS}/nV

_{T}) that replaces (${e}^{\frac{{V}_{DD}/2}{n{V}_{T}}}$/V

_{DD}). Thus, it can be claimed that small-signal and large-signal analyses yield results that are similar to those obtained for a conventional topology, such as the current-starved RO [26].

_{D}of a N-stage ring oscillator is given by:

_{OSC}, Q is the quality factor and F is an empirical fitting parameter that takes the increased noise in Δf into account. The Q factor is typically used in the design of high-order oscillators like LC-type and is defined as the ratio of the energy stored in the oscillating resonator to the energy dissipated per cycle by damping processes. Finally, P

_{sign}in (18) is the power of generated signal. Unfortunately, as in the conventional ring oscillator, the quality factor is poor since the energy stored in the node capacitances is reset(discharged) every cycle [27], resulting in a higher phase noise.

_{(mW)}is the power consumption expressed in mW, thus normalized to 1 mW.

## 4. Validation Results

_{TH}and SVT (standard threshold) p-channel devices with −460-mV V

_{TH}, were adopted. A single power supply of 0.5 V was set and I

_{BIAS}was 320 nA. Reference operating temperature was in the range from 0 °C to 60 °C, suitable for implanted and wearable circuits. Transistor dimensions, together with other component values, are summarized in Table 1.

_{i}, and the ratios of the transistors’ form factors in (1)–(3) are all reduced to the unity. As a consequence of the transistor’s dimension, the nominal quiescent current in each branch, which coincides with its short-circuit current, of 320 nA, resulting in a total nominal quiescent current of N-times 320 nA. Coarse tuning capacitor C

_{i}was set to 10 fF for all stages. The DC gain of the auxiliary amplifiers, A

_{1}and A

_{2}, with transistors in subthreshold, was around 30 dB and the gain-bandwidth product was 10 kHz, while consuming only 50 nA.

_{BP}and V

_{BN}, generated by the circuit in Figure 2 were 251 mV and 249 mV, respectively. The simulated quiescent current in the main ring oscillator in Figure 1 was 961, 1602 and 2243 nA on average, with a standard deviation of 48.5, 78.3, and 107 nA, respectively, for 3-, 5-, and 7-stage topology after running 1000 Monte Carlo iterations. The difference with respect to the expected values is mainly due to the low DC gains of the auxiliary amplifiers, which cause a closed-loop gain error.

_{BIAS}, in the range 120 nA–820 nA. The voltages fall within the supply rails and, in particular, it is easy to observe that their behaviors are symmetrical, confirming a good sizing of the block and the possibility to exploit the full dynamic range of the control voltages. Currents entering in the body terminals have been also evaluated and reported in Figure 6b to highlight that body junctions are never fully turned on during the control operation. In fact, the values of body currents in the worst case (PMOS), reach around 10 nA, corresponding to less than 2% of the biasing one.

_{DD}(500 mV). As expected, the maximum is achieved for V

_{DD}/2 and accurately follows I

_{BIAS}as a validation of the effectiveness of the exploited biasing strategy and the linearity of the relation between the two quantities as well.

_{i}= 10 fF for three values of biasing current, 120, 320, and 820 nA, representing the minimum, nominal and maximum value, respectively.

_{i}= 10 fF). An oscillation range from 360 MHz to 640 MHz is found with tuning sensitivity, i.e., the ratio between (f

_{MAX}− f

_{MIN})/(I

_{BIAS,MAX}− I

_{BIAS,MIN}), about equal to 0.43 MHz/nA. Compared with the predicted behavior (linear relationships resulting from (14) and (15)), the obtained one shows a logarithmic relationship with I

_{BIAS}. This is confirmed by the inset plot in the same figure, the x-axis of which is logarithmic and slightly extended to cover an entire decade. Such changing in the behavior may be due to the partial operation in moderate inversion region, where subthreshold equations lose accuracy.

_{i}, in the considered current biasing range (Figure 10a) and for a fixed I

_{BIAS}= 320 nA (Figure 10b) at T = 30 °C. It is apparent that frequency varies with the bias current, independently of the number of stages and coarse tuning capacitance. Constant spacing between two adjacent curves shows that the number of stages N acts as a scaling constant factor in the expression of the frequency, as predicted by (14) or, equivalently, (15). Moreover, Figure 10b highlights that the coarse tuning capacitance is comparable, in the range between 10 fF and 100 fF, with the parasitic inverter capacitances, being the oscillation frequency to capacitance relation compressed in this range.

_{BN}and V

_{BP}as a function of I

_{BIAS}, at 30 °C. It is apparent that to ensure correct operation (i.e., to maintain bulk voltages within the supply limits) biasing current range must be limited from 240 nA to 460 nA.

_{BIAS}current must be larger than 240 nA.

_{BIAS}, for the five basic corners (at 30 °C). It can be noted that the tuning frequency range is independent of the process corners. Indeed, the tuning sensitivity is constant regardless the corner and is still approximately equal to 0.43 MHz/nA. The maximum percentage variation between the nominal oscillation frequency and that affected by corners is about 20%.

_{BIAS}equal to 350 nA).

_{BIAS}equal to 350 nA and at 30 °C) for three values of the supply voltage V

_{DD}.

_{tot}can be estimated to be 88.6 fF, including the additional load capacitance of 10 fF. This value agrees with the results shown in Figure 10b.

_{DD}= 0.5 V, I

_{BIAS}= 350 nA and T = 27 °C) are reported in Figure 14, showing the limited impact of mismatches on the oscillation frequency of the proposed CRO.

_{BIAS}vs. temperature plot. Each point of the curves establishes the current I

_{BIAS}needed to set the target frequency between around 450 MHz and 557 MHz in the operating range from 0 °C to 60 °C.

_{DD}) variations. To give an example, Figure 16 shows some isofrequency curves (at 557 MHz, 538 MHz, 516 MHz, 491 MHz, and 462 MHz) in the I

_{BIAS}vs. V

_{DD}plot. Each point of the curves establishes the current I

_{BIAS}needed to set the target frequency between around 450 MHz and 557 MHz in the operating range from 475 mV to 525 mV.

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

- Corres-Matamoros, A.; Martínez-Guerrero, E.; Rayas-Sanchez, J.E. A programmable CMOS voltage controlled ring oscillator for radio-frequency diathermy on-chip circuit. In Proceedings of the 2017 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Cozumel, Mexico, 5–7 June 2017; pp. 65–68. [Google Scholar] [CrossRef] [Green Version]
- Ghafari, B.; Koushaeian, L.; Goodarzy, F.; Evans, R.; Skafidas, E. An ultra-low-power and low-noise voltage-controlled ring oscillator for biomedical applications. In Proceedings of the IEEE 2013 Tencon—Spring, Sydney, NSW, Australia, 17–19 April 2013; pp. 20–24. [Google Scholar] [CrossRef]
- Ranjan, R.; Raman, A.; Kashyap, N. Low Power and High Frequency Voltage Controlled Oscillator for PLL Application. In Proceedings of the 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 7–8 March 2019; pp. 212–214. [Google Scholar] [CrossRef]
- Zambrano, B.; Garzón, E.; Strangio, S.; Crupi, F.; Lanuzza, M. A 0.05 mm2, 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs
**2021**, 1. [Google Scholar] [CrossRef] - Meng, X.; Li, X.; Cheng, L.; Tsui, C.-Y.; Ki, W.-H. A Low-Power Relaxation Oscillator With Switched-Capacitor Frequency-Locked Loop for Wireless Sensor Node Applications. IEEE Solid-State Circuits Lett.
**2019**, 2, 281–284. [Google Scholar] [CrossRef] - Ballo, A.; Bruno, G.; Grasso, A.D.; Vaiana, M.G.G. A Compact Temperature Sensor With a Resolution FoM of 1.82 pJ·K2. IEEE Trans. Instrum. Meas.
**2020**, 69, 8571–8579. [Google Scholar] [CrossRef] - Alioto, M. (Ed.) Enabling the Internet of Things: From Integrated Circuits to Integrated Systems; Springer International Publishing: Berlin/Heidelberg, Germany, 2017. [Google Scholar] [CrossRef]
- Ballo, A.; Bottaro, M.; Grasso, A.D. A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices. Appl. Sci.
**2021**, 11, 2487. [Google Scholar] [CrossRef] - Stornelli, V.; Barile, G.; Pantoli, L.; Scarsella, M.; Ferri, G.; Centurelli, F.; Tommasino, P.; Trifiletti, A. A New VCII Application: Sinusoidal Oscillators. J. Low Power Electron. Appl.
**2021**, 11, 30. [Google Scholar] [CrossRef] - Razavi, B. A study of phase noise in CMOS oscillators. IEEE J. Solid-State Circuits
**1996**, 31, 331–343. [Google Scholar] [CrossRef] [Green Version] - Zaman, K.S.; Reaz, M.I.; Haque, F.; Arsad, N.; Ali, S.H.M. Optimization of WiFi Communication System using Low Power Ring Oscillator Delay Cell. In Proceedings of the 2020 IEEE 8th Conference on Systems, Process and Control (ICSPC), Melaka, Malaysia, 11–12 December 2020; pp. 91–94. [Google Scholar] [CrossRef]
- Nayak, R.; Kianpoor, I.; Bahubalindruni, P.G. Low power ring oscillator for IoT applications. Analog Integr. Circuits Signal Process.
**2017**, 93, 257–263. [Google Scholar] [CrossRef] - Lee, S.-Y.; Hsieh, J.-Y. Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation. IEEE Trans. Circuits Syst. II Express Briefs
**2008**, 55, 624–627. [Google Scholar] [CrossRef] - Reddy, N.; Pattanaik, M.; Rajput, S.S. 0.4V CMOS based low power voltage controlled ring oscillator for medical applications. In Proceedings of the TENCON 2008–2008 IEEE Region 10 Conference, Hyderabad, India, 19–21 November 2008; pp. 1–5. [Google Scholar] [CrossRef]
- Chuang, Y.-H.; Jang, S.-L.; Lee, J.-F.; Lee, S.-H. A low voltage 900 MHz voltage controlled ring oscillator with wide tuning range. In Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004, Tainan, Taiwan, 6–9 December 2004; Volume 1, pp. 301–304. [Google Scholar] [CrossRef]
- Srivastava, A.; Zhang, C. An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits. Int. J. Distrib. Sens. Netw.
**2008**, 4, 213–222. [Google Scholar] [CrossRef] - Deen, M.J.; Kazemeini, M.H.; Naseh, S. Performance characteristics of an ultra-low power VCO. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ’03, Bangkok, Thailand, 25–28 May 2003; Volume 1, p. I. [Google Scholar] [CrossRef]
- Ballo, A.; Grasso, A.D.; Pennisi, S.; Venezia, C. High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS. J. Low Power Electron. Appl.
**2020**, 10, 27. [Google Scholar] [CrossRef] - Monsurró, P.; Pennisi, S.; Scotti, G.; Trifiletti, A. Exploiting the Body of MOS Devices for High Performance Analog Design. IEEE Circuits Syst. Mag.
**2011**, 11, 8–23. [Google Scholar] [CrossRef] - Palumbo, G.; Scotti, G. A Novel Standard-Cell-Based Implementation of the Digital OTA Suitable for Automatic Place and Route. J. Low Power Electron. Appl.
**2021**, 11, 42. [Google Scholar] [CrossRef] - Ballo, A.; Pennisi, S.; Scotti, G. 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control. J. Low Power Electron. Appl.
**2021**, 11, 37. [Google Scholar] [CrossRef] - Pérez-Nicoli, P.; Veirano, F.; Rossi-Aicardi, C.; Aguirre, P. Design method for an ultra low power, low offset, symmetric OTA. In Proceedings of the 2013 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 15–16 August 2013; pp. 38–43. [Google Scholar]
- Silveira, F.; Flandre, D.; Jespers, P.G.A. A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE J. Solid-State Circuits
**1996**, 31, 1314–1319. [Google Scholar] [CrossRef] - Alioto, M. Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis. IEEE Trans. Circuits Syst. Regul. Pap.
**2010**, 57, 1597–1607. [Google Scholar] [CrossRef] - Rabaey, J.M. Digital Integrated Circuits: A Design Perspective; Prentice-Hall, Inc.: Hoboken, NJ, USA, 1996. [Google Scholar]
- Rajahari, G.; Varshney, Y.A.; Bose, S.C. A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator. In VLSI Design and Test; Springer: Berlin/Heidelberg, Germany, 2013; pp. 10–18. [Google Scholar] [CrossRef]
- Lee, T.H.; Hajimiri, A. Oscillator phase noise: A tutorial. IEEE J. Solid-State Circuits
**2000**, 35, 326–336. [Google Scholar] [CrossRef] [Green Version] - Tianwang, L.; Jiang, J.; Bo, Y.; Xingcheng, H. Ultra low voltage, wide tuning range voltage controlled ring oscillator. In Proceedings of the 2011 9th IEEE International Conference on ASIC, Xiamen, China, 25–28 October 2011; pp. 824–827. [Google Scholar] [CrossRef]
- Saheb, Z.; El-Masry, E.; Bousquet, J.-F. Ultra-low voltage and low power ring oscillator for wireless sensor network using CMOS varactor. In Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, BC, Canada, 15–18 May 2016; pp. 1–5. [Google Scholar] [CrossRef]
- Abdollahvand, S.; Oliveira, L.B.; Gomes, L.; Goes, J. A low-voltage voltage-controlled ring-oscillator employing dynamic-threshold-MOS and body-biasing techniques. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015; pp. 1294–1297. [Google Scholar] [CrossRef]

**Figure 2.**Simplified schematic of the biasing section generating V

_{BN}and V

_{BP}for the RO in Figure 1.

**Figure 3.**Simplified schematic of simple mirror OTA [21] used in this work.

**Figure 7.**Static currents flowing in the reference inverter vs. input voltage for different I

_{BIAS}(

**a**), and static currents maxima vs. I

_{BIAS}(T = 30 °C) (

**b**).

**Figure 9.**Oscillation frequency of the 5-stage CRO as a function of the biasing current at T = 30 °C.

**Figure 10.**Oscillation frequencies for different coarse tuning capacitance values in the interested current biasing range (

**a**) and for a fixed I

_{BIAS}= 320 nA (

**b**) at T = 30 °C.

**Figure 11.**Bulk−source voltage of NMOS (

**a**) and PMOS (

**b**) transistors vs. biasing current over the 5 basic process corners.

**Figure 14.**Mismatch Monte Carlo simulations of the oscillation frequency in typical conditions (VDD = 0.5 V, I

_{BIAS}= 350 nA and T = 27 °C).

Parameter | Value |
---|---|

V_{DD} | 0.5 V |

I_{BIAS} | 320 ^{a} nA |

(W/L)_{PA}, (W/L)_{PR}, (W/L)_{Pi} | 8.28/0.18 μm/μm |

(W/L)_{NR}, (W/L)_{Ni} | 5.4/0.18 μm/μm |

A_{1}, A_{2} | 30 dB |

GBW_{A1}, GBW_{A2} | 10 kHz |

C_{i} | 10 fF |

^{a:}This value will be changed to 350 nA after corner analysis.

**Table 2.**Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 °C and at V

_{DD}= 475 mV.

Corner | TT | FF | FS | SF | SS |
---|---|---|---|---|---|

Oscillation frequency (MHz) | 451.2 | 481.6 | 446.2 | 446.7 | 397.3 |

Tuning range (MHz) | 87.09 | 96.38 | 50.69 | 59.24 | 24.12 |

Phase noise @1 MHz (dBc/Hz) | −92.77 | −92.39 | −92.90 | −92.90 | −93.75 |

Average power consumption (μW) | 23.40 | 24.41 | 23.31 | 23.14 | 20.94 |

**Table 3.**Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 °C and at V

_{DD}= 500 mV.

Corner | TT | FF | FS | SF | SS |
---|---|---|---|---|---|

Oscillation frequency (MHz) | 516.2 | 547.3 | 410.7 | 418.5 | 482.5 |

Tuning range (MHz) | 95.44 | 102.50 | 94.11 | 94.94 | 85.08 |

Phase noise @1 MHz (dBc/Hz) | −92.47 | −92.13 | −92.58 | −92.40 | −92.87 |

Average power consumption (μW) | 28.6 | 29.8 | 28.4 | 28.8 | 27.5 |

**Table 4.**Corner analysis of the 5-stage current-controlled ring oscillator performed at 30 °C and at V

_{DD}= 525 mV.

Corner | TT | FF | FS | SF | SS |
---|---|---|---|---|---|

Oscillation frequency (MHz) | 583.3 | 619.7 | 577.6 | 586.5 | 549.6 |

Tuning range (MHz) | 102.47 | 59.27 | 81.37 | 100.50 | 93.52 |

Phase noise @1 MHz (dBc/Hz) | −92.14 | −91.98 | −92.25 | −92.06 | −92.48 |

Average power consumption (μW) | 36.16 | 37.93 | 35.85 | 36.29 | 34.61 |

Reference | [28] | [29] | [30] | This Work ^{b} |
---|---|---|---|---|

Tech. (nm) | 180 | 65 | 65 | 28 |

V_{DD} (mV) | 500 | 600 | 700 | 500 |

N stages | 3 | 3 | 4 | 5 |

Type of control | Voltage | Voltage | Voltage | Current |

Osc. frequency (MHz) | 82–370 | 250–800 | 880–1360 | 360–640 |

Phase Noise (dBc/Hz)@1 MHz | −82 | −86.38 | −90 | −92.47 |

Power consumption (μW) | 60 | 146.2 | 360 | 28.6 |

FoM ^{a} (dBc/Hz) | −145.6 | −153.2 | −153.6 | −164 |

^{a}: see (16);

^{b}: simulations.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |

© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Ballo, A.; Pennisi, S.; Scotti, G.; Venezia, C.
A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices. *J. Low Power Electron. Appl.* **2022**, *12*, 16.
https://doi.org/10.3390/jlpea12010016

**AMA Style**

Ballo A, Pennisi S, Scotti G, Venezia C.
A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices. *Journal of Low Power Electronics and Applications*. 2022; 12(1):16.
https://doi.org/10.3390/jlpea12010016

**Chicago/Turabian Style**

Ballo, Andrea, Salvatore Pennisi, Giuseppe Scotti, and Chiara Venezia.
2022. "A 0.5 V Sub-Threshold CMOS Current-Controlled Ring Oscillator for IoT and Implantable Devices" *Journal of Low Power Electronics and Applications* 12, no. 1: 16.
https://doi.org/10.3390/jlpea12010016