# A Standard-Cell-Based CMFB for Fully Synthesizable OTAs

^{*}

## Abstract

**:**

## 1. Introduction

## 2. The Proposed CMFB

_{i}for a supply voltage V

_{DD}= 0.3 V. Figure 1b clearly shows that an incorrect input dc bias results in a drop of voltage gain, thus making multistage amplifiers very difficult to implement if the dc output voltage of basic inverter stages is not controlled. The plot in Figure 1b also highlights the systematic offset of the inverter from a standard-cell library. In fact, the maximum gain is achieved for an input bias voltage different from V

_{DD}/2 = 150 mV (value marked as a red dashed line). This systematic offset of the inverter (resulting in a logic threshold different from V

_{DD}/2) is due to the fact that standard cells are not optimized for analog applications, and a trade-off between area, propagation time and balancing constraints is considered.

_{ref}to the standard-cell LCMFB through the inverter I

_{7}, as shown in Figure 2.

_{1}and I

_{1}’), the common-mode estimator (I

_{2}, I

_{2}’ and I

_{3}), the reference inverting buffer (I

_{7}, loaded by I

_{5}) and the CMFB auxiliary amplifier (I

_{4}, I

_{5}, I

_{6}and I

_{6}’). Inverters with their input and output terminals connected together are used as load devices to avoid high impedance nodes in the loop, providing better stability and a degree of freedom to design the circuit, as will be shown following this section. They are equivalent to parallel NMOS and PMOS diode-connected devices; thus, the cascade of an inverter and such a diode-connected inverter is equivalent to the parallel connection of an NMOS and a PMOS diode-loaded common-source stage.

_{X}(X = 1, …, 7) with a transconductance gain G

_{X}and an output conductance G

_{oX}, given by

_{m}and g

_{ds}are the small-signal transconductance and output conductance of MOS devices, and n and p subscripts refer to NMOS and PMOS transistors, respectively. We assume that they scale linearly with the size of the devices (hence with the strength of the standard cells, IV_xN meaning an inverter whose devices have N times the minimum width), and their ratio is the voltage gain A

_{X}= G

_{X}/G

_{oX}that we assume is identical for all the inverters (hence A

_{X}= A for x = 1, …, 7).

_{6}and I

_{1}(hence α = G

_{6}/G

_{1}), λ = G

_{2}/G

_{3}, ρ = G

_{4}/G

_{5}and β = G

_{7}/G

_{4}. The differential voltage gain of the first stage in Figure 2 results in

_{ic}and V

_{oc}are the input and output common-mode components. The gains are

_{X}>> G

_{oX,}, since A approaches to infinite, the values of ${\epsilon}_{2}$ and ${\epsilon}_{4}$ tend to 1).

_{R}= 1, which in the limit of large CMRR implies

_{7}must be maximized, and (12) requires β < A.

_{7}(that is βρ times larger than I

_{5}) and I

_{2}(that is λ times larger than I

_{3}):

_{2}saturates.

_{max}> R

_{max}, βρ is set to R

_{max}and maximizing (11) requires keeping the factor ρ as small as possible (ρ = 1). If β

_{max}< R

_{max}, which is the case for low values of the gain A, β = β

_{max}must be chosen; (11) then becomes

_{max}/β

_{max}. A flow graph illustrating this design procedure is reported in Figure 3.

_{offX}that accounts for the offset of the inverter, i.e., the error in the output voltage with respect to V

_{DD}/2 when the input voltage is V

_{DD}/2:

_{oc}due to these offset current sources, which can be obtained by letting V

_{ic}= V

_{ref}= 0 in Figure 4, we obtain

_{oc}= V

_{ref}is due also to the offset currents of the inverters and that the CMFB suppresses this error in the limit of its finite loop gain. This is true both for the systematic offset currents and for their random components, thus demonstrating that the circuit provides a stable dc output voltage under process and mismatch variations. It must be noted that a suitable choice of the inverter strengths can lead to minimizing (17) and could be used as a further design constraint for design optimization.

## 3. Standard-Cell-Based OTA

_{8}–I

_{11}. Inverters I

_{8}and I

_{9}constitute an inverting voltage buffer whose gain is ideally −1, and inverters I

_{10}and I

_{11}act as transconductance amplifiers driving the same output node.

_{8}and I

_{9}cannot be neglected in the analysis. This reduces the gain of the voltage buffer and drastically worsens the CMRR even in typical conditions. Assuming I

_{8}= I

_{9}and I

_{10}= I

_{11}, differential and common-mode gains of the second stage are

_{L}; moreover, its dual path nature results in a pole–zero doublet similar to that provided by the current mirror load of a differential pair. With reference to Figure 2, assuming I

_{8}= I

_{9}and I

_{10}= I

_{11}and considering a differential input to the D2S (i.e., V

_{o}

_{1p}= −V

_{o}

_{1m}), the frequency response of the D2S can be written as

_{X}is the total capacitance seen at the output of I

_{8}. Equation (22) shows that the pole and zero due to the inverting buffer I

_{8}–I

_{9}are spaced by an octave; thus, their effect can be neglected. It must further be noted that Equation (22) poses no constraint on the sizing of inverters I

_{8}and I

_{9}with respect to I

_{10}and I

_{11}; regardless, it could be convenient to use inverters of the same size to provide a symmetric loading to the first stage.

_{8}and I

_{9}, the internal pole of the OTA is given by

_{in}

_{2}and C

_{in}

_{8}are the input capacitances of I

_{2}and I

_{8}, and the output pole is

_{10}= I

_{11}). By imposing that the second pole is γ times the unity-gain frequency (where γ is set by the required phase margin), the minimum load capacitance required to have stability with the dominant pole at the output is

## 4. Simulation Results

_{2}and I

_{8}) and the design factors were set to α = 1, λ = 4, ρ = 1 and β = 4. The resulting static offset is therefore

_{DD}/2, and the error of the output dc common-mode voltage with respect to this reference was evaluated. The LCMFB without I

_{7}and the reference input were also tested for comparison.

_{DD}, 27 °C) due to the finite loop gain of the CMFB. When the reference input is present, the output common-mode voltage presents a limited variation when the temperature ranges from 0° to 80 °C, whereas the voltage drifts with the temperature if the reference input is not used. For what concerns the variation of the supply voltage, the dc common-mode output voltage tracks V

_{DD}/2 with an error, due to the finite loop gain, that presents little variation and is lower than the error achieved by the design without the reference input.

_{VD}) and common-mode (A

_{VC}) gains of the OTA loaded by a 1.5 pF capacitor. The differential dc gain is 28.27 dB with a 15.42 MHz unity-gain frequency and 54.18° phase margin; the common-mode rejection ratio (CMRR) is about 41.07 dB and is constant across all the bandwidth.

_{VD}and the output dc voltage (measured through the parameter V

_{OS}) are extremely stable, confirming the effectiveness of the proposed approach.

_{OS}under mismatch variations, we can place multiple gates in parallel or exploit standard cells with larger driving capability, at the cost, however, of increased area and power consumption. We consider the proposed design as a good tradeoff between area, power consumption and output offset voltage standard deviation. Figure 11 shows the histogram of the CMRR, which is always higher than 10 dB and presents a log-normal distribution. The histogram shows that, even under mismatch conditions, acceptable values of CMRR are obtained, taking also into account the low value of the differential gain.

^{2}that is very limited, notwithstanding the use of large inverters to minimize the mismatches. The layout has been generated automatically starting from a Verilog netlist of the circuit, which is reported in the Appendix A.

_{L}the load capacitance, SR

_{AVG}is the average slew rate and Pd is the power consumption. Subscripts S and L in (27) and (28) denote small signal and large signal, respectively, while the figures of merit (29) and (30) are normalized with respect to the layout area of the OTA. The comparison shows that the proposed circuit exhibits very good small signal performance and adequate large signal performance. Due to the very compact layout, the proposed OTA outperforms all other similar designs in terms of $FO{M}_{L,A}$. The proposed OTA also outperforms almost all other designs in terms of $FO{M}_{S,A}$. Only [30] exhibits a higher $FO{M}_{S,A}$; however, the OTA in [30] is made up of minimum-sized standard cells that result in high sensitivity to process variations and mismatches.

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A

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**Figure 4.**Model for the common-mode half circuit of the proposed CMFB loop considering the offset of the inverters.

**Figure 6.**Relative error (%) of the dc output common-mode voltage vs. process corners; darker colors correspond to higher relative errors.

**Figure 12.**Layout of the proposed OTA generated by using the Cadence Innovus automatic place and route flow.

Corner | FF | SS | FS | SF |
---|---|---|---|---|

A_{VD} [dB] | 25.22 | 31.43 | 28.04 | 27.37 |

GBW [MHz] | 26.4 | 10.24 | 15.28 | 14.57 |

m_{φ} [°] | 63.38 | 49.18 | 60.59 | 60.28 |

Pd [μW] | 7.832 | 1.89 | 3.97 | 3.74 |

V_{OS} [mV] | 0.45 | 0.18 | 0.93 | 0.45 |

SR [V/μs] | 15.15 | 5.85 | 12.47 | 6.33 |

Voltage Variations | Temperature Variations | |||
---|---|---|---|---|

T [°C] | 27 | 27 | 0 | 80 |

V_{DD} [mV] | 270 | 330 | 300 | 300 |

A_{VD} [dB] | 27.28 | 29.03 | 29.25 | 26.32 |

GBW [MHz] | 10.03 | 23.03 | 9.80 | 29.41 |

m_{φ} [°] | 59.94 | 52.04 | 52.10 | 58.50 |

Pd [μW] | 2.65 | 7.15 | 2.38 | 11.21 |

V_{OS} [mV] | −0.29 | −0.29 | −0.29 | 0.17 |

SR [V/μs] | 3.61 | 12.52 | 6.91 | 12.88 |

Mean | Std | |
---|---|---|

A_{VD} [dB] | 28.2 | 0.88 |

GBW [MHz] | 15.78 | 1.91 |

m_{ϕ} [°] | 54.47 | 3.12 |

CMRR [dB] | 24.68 | 8.56 |

Pd [μW] | 4.49 | 0.11 |

V_{OS} [mV] | 0.002 | 9.2 |

SR [V/μs] | 9.12 | 1.02 |

Ref | This Work | [30] | [31] | [17] | [18] | [46] | [10] | [12] | [35] | [36] | [3] |
---|---|---|---|---|---|---|---|---|---|---|---|

Year | 2022 | 2021 | 2021 | 2022 | 2022 | 2020 | 2020 | 2020 | 2019 | 2019 | 2015 |

Tech. [nm] | 130 | 180 | 180 | 130 | 130 | 180 | 65 | 180 | 130 | 130 | 65 |

V_{DD} [V] | 0.3 | 0.55 | 0.3 | 0.3 | 0.3 | 0.3 | 0.25 | 0.5 | 0.3 | 0.25 | 0.35 |

A_{VD} [dB] | 28.3 | 87 | 30 | 38.1 | 52.9 | 39 | 70 | 79.5 | 49.8 | 25 | 43 |

GBW [kHz] | 15,420 | 3150 | 0.25 | 24.14 | 35.16 | 0.9 | 9.5 | 36 | 9100 | 7.23 | 3600 |

m_{φ} [°] | 54 | 65 | 90 | 60 | 52 | 90 | 89 | 65 | 76 | 90 | 56 |

C_{L} [pF] | 1.5 | 250 | 150 | 50 | 50 | 10 | 15 | 15 | 2 | 30 | 3 |

SR_{AVG} [V/ms] | 9075 | 2.7 | 0.085 | 14.23 | 15.06 | -- | 2 | 9.7 | 3800 | -- | 5600 |

Pd [nW] | 4406 | 8200 | 2.4 | 59.9 | 21.9 | 0.6 | 26 | 60 | 1800 | 55 | 17,000 |

Area [μm^{2}] | 164 | 88.3 | 982 | 2700 | 5200 | 472 | 2000 | 3395 | -- | 52,000 | 5000 |

Type | STD | STD | DIG | BD | BD | IB | BD | BD | IB | IB | BD |

FOM_{S}[MHz pF/μW] | 5.25 | 96.04 | 15.62 | 20.15 | 80.31 | 15 | 5.48 | 9 | 10.11 | 3.94 | 0.63 |

FOM_{L}[V pF/μs μW] | 3.09 | 0.08 | 5.31 | 11.88 | 34.40 | -- | 1.15 | 2.42 | 4.22 | -- | 0.99 |

FOM_{S,A}[MHz pF/μW μm ^{2}] | 32.01 | 1088 | 15.9 | 7.46 | 15.44 | 31.78 | 2.74 | 2.65 | -- | 0.07 | 0.13 |

FOM_{L,A}[V pF/ms μW μm ^{2}] | 18.84 | 0.93 | 5.4 | 4.4 | 6.61 | -- | 0.57 | 0.71 | -- | -- | 0.19 |

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## Share and Cite

**MDPI and ACS Style**

Centurelli, F.; Della Sala, R.; Scotti, G.
A Standard-Cell-Based CMFB for Fully Synthesizable OTAs. *J. Low Power Electron. Appl.* **2022**, *12*, 27.
https://doi.org/10.3390/jlpea12020027

**AMA Style**

Centurelli F, Della Sala R, Scotti G.
A Standard-Cell-Based CMFB for Fully Synthesizable OTAs. *Journal of Low Power Electronics and Applications*. 2022; 12(2):27.
https://doi.org/10.3390/jlpea12020027

**Chicago/Turabian Style**

Centurelli, Francesco, Riccardo Della Sala, and Giuseppe Scotti.
2022. "A Standard-Cell-Based CMFB for Fully Synthesizable OTAs" *Journal of Low Power Electronics and Applications* 12, no. 2: 27.
https://doi.org/10.3390/jlpea12020027