Enhancement Mode Ga₂O₃ Field Effect Transistor with Local Thinning Channel Layer

Abstract

β−Ga₂O₃ field−effect transistors (FETs) were fabricated with and without local thinning to change the threshold voltage. A 220 nm Ga₂O₃ layer was mechanically exfoliated from a Cr−doped gallium oxide single crystal. Approximately 45 nm Ga₂O₃ was etched by inductively coupled plasma to form the local thinning. The threshold voltage of the device with etched local thinning increased from −3 V to +7 V compared to the unetched device. The effect of the local thinning was analyzed by device simulation, confirming that the local thinning structure is an effective method to enable enhancement−mode Ga₂O₃ FETs.

1. Introduction

β−Ga₂O₃ has attracted significant attention attributing to its ultra−wide bandgap, high breakdown electric field (~8 MV cm⁻¹), and excellent chemical stability [1,2,3,4,5]. In addition, the Baliga’s figure of merit of Ga₂O₃ is approximately 3200, which is three times higher than that of GaN and eight times higher than that of SiC [1,6]. This shows that Ga₂O₃ has great potential as a future power electronics material. Epitaxial β−Ga₂O₃ layers have been grown by many techniques including metal−organic chemical vapor deposition, molecular beam epitaxy, and pulsed laser deposition [7,8]. Ga₂O₃−based field−effect transistors [9,10,11], metal−semiconductor field−effect transistors [6,12], and Schottky barrier diodes [13,14,15,16] have demonstrated potential as next−generation high−power electronic devices. In particular, Ga₂O₃−based FETs have shown high current densities [17,18], high voltage breakdown [19], low ohmic contact resistance [20], and early prospects for modulation doping [21] and integration [22].

Since β−Ga₂O₃ bulk crystal monoclinic structures have large lattice constant differences between the a, b, and c axes, they can be used to prepare single−crystalline nanolayer flakes by the mechanical exfoliation method [23]. Mechanically exfoliated β−Ga₂O₃ nanolayer flakes are strain−free and have flat surfaces with high crystallinity. Gallium oxide doped with Si [24], Sn [25] and Ge [26] can achieve n−type films. However, an n−type Ga₂O₃ FET is a depletion−mode device with a negative threshold voltage (V_th); with the lack of effective p−type doping, enhancement−mode (e−mode) operation has been limited. Enhancement−mode devices are preferred to mitigate the off−state power dissipation and for safe high−voltage operations in practical power applications [27].

Even so, there have been many reports on e−mode β−Ga₂O₃ FETs in recent years. Chabak et al. [28] fabricated Sn−doped Ga₂O₃ wrap−gate fin−array field−effect transistors (finFETs) with a threshold voltage between 0 and +1 V. Zongyang Hu et al. [29] fabricated an enhancement−mode Ga₂O₃ vertical power metal–insulator field−effect transistors with fin−shaped channels. Yuanjie Lv et al. [27] fabricated Ga₂O₃ metal−oxide−semiconductor field−effect transistors with gate recess depths of 110 nm and 220 nm, respectively. Additionally, upon increasing the recess depth, the threshold voltage increased to +3 V. Kamimura et al. [30] fabricated enhancement−mode devices using N−Si co−doping technology. Zhaoqing Feng et al. [31] achieved an enhancement−mode Ga₂O₃ metal−oxide semiconductor field−effect transistor by incorporating a laminated ferroelectric charge storage gate structure. Janghyuk Kim et al. [6] demonstrated the realization of an E−mode quasi−two−dimensional Ga₂O₃ FET with a novel graphene gate architecture via a van der Waals heterojunction. Xunxun Wang et al. [32] fabricated SnO/Ga₂O₃ p−n heterojunctions in the back channel, achieving enhancement−mode operation.

Herein, bottom−gate (BG) Ga₂O₃ FETs can be easily fabricated with a local thinning channel layer based on high−quality Ga₂O₃ layers with a thickness of 220 nm, exfoliated from Cr−doped Ga₂O₃ single crystals [33]. Before the experiment, the effects of local thinning on the device were thoroughly analyzed based on Technical Computer−Aided Design (TCAD) simulation. The simulation results show that the local thinning can achieve larger output current compared to the overall thinning. Moreover, the threshold voltage shifted in the positive direction by about 4 V for every 50 nm increase in the locally thinned thickness. It can be known from the simulation results that the threshold voltage of the device can be adjusted by changing the thickness of Ga₂O₃. Therefore, by preparing a bottom gate structure transistor, we etch on the top of the gallium oxide, and change the thickness of the Ga₂O₃ layer to achieve the purpose of enhancement mode. The transistor realized by the bottom gate device does not need the preparation process of preparing the trench gate, which greatly simplifies the preparation process. An enhancement−mode Ga₂O₃ FET was made with local thinning depth of 45 nm, exhibiting a high threshold voltage of +7 V and a saturation current of 0.34 μA.

2. Materials and Methods

In this study, unintentionally doped bulk β−Ga₂O₃ crystals were used. The carrier concentration of the crystal is approximately 1 × 10¹⁷ cm⁻³. The arrangement of atoms in the monoclinic system β−Ga₂O₃ allows a facile exfoliate into thin flakes in the (100) direction, which has a larger lattice constant than other directions [9,34]. The device process flow is shown in Figure 1. First, nano−scale thickness Ga₂O₃ flakes were prepared by repeated mechanical exfoliation from the bulk Ga₂O₃ crystals. Then, Ga₂O₃ flakes were transferred to a p−type silicon wafer, with a 100 nm thickness thermally grown SiO₂. For the Ga₂O₃ flakes to have better contact with the Si substrate and reduced amount of contaminants, the substrate was pretreated by oxygen plasma (ProCleanerTM, Harrick Plasma, Ithaca, NY, USA) for 3 min prior to the transfer. The source and drain electrodes were defined by Ti/Au (20 nm/80 nm) using an electron−beam evaporation technique on both ends of the Ga₂O₃ flakes. The source and drain contacts improved by inductively coupled plasma etching before electrode deposition with the power, chamber pressure, gas flow, and etching time of 150 W, 20 mTorr, BCl₃/Ar (15 sccm/5 sccm) and 2 min, respectively. Finally, dry etching was performed using a BCl₃/Ar plasma with a photolithography mask used to form the recess. The power, chamber pressure, gas flow, and etching time was 350 W, 20 mTorr, BCl₃/Ar (15 sccm/5 sccm) and 3.5 min, respectively [35]. After etching, a Ga₂O₃ local thinning structure device was formed as shown in Figure 1f. The channel length and width are 12 μm and 1.1 μm, respectively.

The fabricated devices were characterized by scanning electron microscopy (SEM, FEI Nano 450, Hillsboro, OR, USA), atomic force microscopy (AFM, Benyuan CSPM5500, Guangzhou, China), and their electrical characteristics were measured using a source/measurement unit semiconductor parameter analyzer (Keysight B2902A, Santa Rosa, CA, USA) at room temperature.

3. Results

TCAD provides an efficient way to understand the properties of the device. Up to now, many related works have been reported on the TCAD simulation of Ga₂O₃ transistors [36,37,38]. Due to the non−convergence of the bottom gate model, we used a similar structure for the top gate to analyze the effect of the local thinning on the threshold voltage. Here, the effect of gate recess on the Ga₂O₃ FET with a doping concentration of 10¹⁷ cm⁻³ was investigated by modeling prior to device fabrication. In the model, the channel layer had a 200 nm thick Ga₂O₃ film and a gate dielectric layer of 100 nm SiO₂. Figure 2 shows the simulation schematics with overall thinning of 50 nm (a) and local thinning of 50 nm (b), respectively. As shown in Figure 2c, comparing the output characteristic curves of the overall thinning and the local thinning, the current of the overall thinning is significantly smaller than that of the local thinning, but the transfer curves show that the threshold voltage of the overall thinning and the local thinning hardly changes, as shown in Figure 2d. This result indicates that local thinning can effectively prevent the current reduction caused by thinning Ga₂O₃ film.

Figure 3a,b shows the simulated structure of Ga₂O₃ FET without and with local thinning, respectively. To directly compare the V_th shift by increasing the locally thinned thickness, we set the thinning thickness to increase from 0 to 150 nm. Figure 3c shows the variation of the output current of Ga₂O₃ FETs with different thinning thicknesses. Obviously, with the increase in the local thinning depth, the output current gradually decreases. In addition, the thickness of the local thinning increases by 50 nm, and the threshold voltage is shifted in the positive direction by about 4 V, as shown in Figure 3d.

Based on the simulation results, β−Ga₂O₃ thin−film FET devices were prepared. Figure 4a and b show the SEM images of the β−Ga₂O₃ flake fabricated into a FET structure with a Ti/Au electrode and a FET device with local thinning, respectively. Figure 4c shows the local thinning depth is 45 nm and the bulk β−Ga₂O₃ crystal peeled off into a sheet with a thickness of approximately 220 nm, as revealed by the atomic force microscopy image, as shown in Figure 4d.

The output characteristics of the β−Ga₂O₃ FET with and without the local thinning structure were measured using a semiconductor characterization system at room temperature. In the measurements, the drain−source voltage ranges from 0 V to 10 V. The fabricated Ga₂O₃ FETs exhibited good saturation and pinch−off characteristics. As shown in Figure 5a and b, a linear increase in I_D at low V_D, and saturation at high V_D, represent effective gate modulation in an n−type channel. A maximum drain current (I_Dmax) of 0.4 μA was obtained at the V_G of +5 V in the device before etching, while the I_Dmax was just 0.34 μA at the V_G of +12 V after etching, mainly because the etched oxide channel forms the local thinning. The local thinning structure also results in a low drain current. The transfer characteristics of the Ga₂O₃ FETs before and after etching were also measured. During the measurement, the device drain bias was set to +10 V. As shown in Figure 5c, the device before etching has a threshold voltage of −3 V, and after etching, the threshold voltage reaches +7 V, as shown in Figure 5d. This change is from a depletion mode to an enhanced field−effect transistor, mainly because the formation of a 45 nm local thinning structure after etching decreases the thickness of the channel layer, resulting in an earlier depletion pinch−off of the device during operation. Overall, the result is that V_th shifts from negative values in D−mode to positive values in E−mode by reducing the thickness of Ga₂O₃ [39]. The forward threshold voltage forms a normally on FET device. Comparing the off−state drain current before and after etching, the leakage current after etching is approximately 6 × 10⁻¹¹, which is larger than that of 8 × 10⁻¹² before etching, showing that dry etching damages the n−type Ga₂O₃ layer to some extent. Before the etching, the on/off current ratio of the device reaches 1 × 10⁵, because of the relatively low off−state current. After the etching, the on/off current ratio reduced to 2.2 × 10⁴, because of the rising leakage current.

4. Conclusions

In summary, Ga₂O₃ FETs were fabricated with and without the local thinning based on high−quality quasi−two−dimensional single−crystalline β−Ga₂O₃ flakes exfoliated from a bulk single crystal. The effect of the local thinning structure was investigated by device simulations. The simulation results show that the local thinning can achieve larger output current compared to the overall thinning. In addition, the threshold voltage shifted in the positive direction by about 4 V for every 50 nm increase in the locally thinned thickness. The fabricated Ga₂O₃ FETs have good saturation and pinch−off characteristics. In the device with a doping concentration of 10¹⁷ cm⁻³, the device before etching has a threshold voltage of −3 V, and after etching, the threshold voltage reaches +7 V. By optimizing the device processing, the performance of Ga₂O₃ FET may be further improved.