Circuit Structure and Control Method to Reduce Size and Harmonic Distortion of Interleaved Dual Buck Inverter

Abstract

A new circuit structure and control method for a high power interleaved dual-buck inverter are proposed. The proposed inverter consists of six switches, four diodes and two inductors, uses a dual-buck structure to eliminate zero-cross distortion, and operates in an interleaved mode to reduce the current stress of switch. To reduce the total harmonic distortion at low output power, the inverter is controlled using discontinuous-current-mode control combined with continuous-current-mode control. The experimental inverter had a power-conversion efficiency of 98.5% at output power = 1300 W and 98.3% at output power = 2 kW, when the inverter was operated at an input voltage of 400 V_DC, output voltage of 220 V_AC/60 Hz, and switching frequency of 20 kHz. The total harmonic distortion was < 0.66%, which demonstrates that the inverter is suitable for high-power dc-ac power conversion.

1. Introduction

The full-bridge inverter (FBI, Figure 1a) is widely used for dc-ac power conversion because of its simple structure and easy control [1]. An FBI uses sinusoidal modulation of the switching duty to produce an alternating output voltage. The FBI has a shoot-through problem [2], which occurs when the high side and low side switches (S₁ and S₄, or S₃ and S₂) are turned on at the same time; this problem can cause serious circuit damage. The shoot-through problem can be solved by inserting a dead-time between the gate pulses of the high and low side switches, but inserting a dead-time changes the effective switching duty ratio and increases zero-cross distortion (ZCD) [3]. The FBI has the other disadvantage of requiring high-rated switches and large output filters [4,5].

Various dual-buck inverters [6,7,8,9,10,11,12,13,14,15] have been proposed to remedy the disadvantages of the FBI. The dual-buck inverters use freewheeling diodes to solve the shoot-through problem but have high output current ripple. The interleaved dual-buck inverter (IDBI) in [9], as shown in Figure 1b, is basically a parallel connection of four buck converters. In this inverter, S_U1 and S_U2 operate to generate positive sinusoidal voltage, S_D1 and S_D2 operate to generate negative sinusoidal voltage, and the switching-phase differences between S_U1 and S_U2 and between S_D1 and S_D2 are set to 180°. Thus, the current of S_U1 is interleaved with that of S_U2, and the current of S_D1 is interleaved with that of S_D2. Using an interleaved mode reduces conduction losses, output current ripple, and current stress in switches and diodes. IDBI requires four inductors, so it is expensive and bulky. When IDBI uses typical sinusoidal pulse width control and operates at a low output power P_o, IDBI has much higher total harmonic distortion (THD) of the output current than that of the FBI.

The inverter proposed in this paper (Figure 2) is a modified IDBI. This inverter inherits the IDBI’s advantages but uses two reverse-current-protection diodes D_D3 and D_U3 to reduce the number of inductors and a new control method to reduce the THD of the output current. The proposed inverter operates in discontinuous conduction mode (DCM) [16] when the output current is below the threshold; otherwise, it operates in continuous conduction mode (CCM). The circuit structure and principle of operation are described in Section 2, experimental results and discussions are given in Section 3, and a conclusion is given in Section 4.

2. Proposed Interleaved Dual-buck Inverter

2.1. Circuit Structure and Principle of Operation

The proposed inverter (Figure 2) uses two dual-buck legs (leg 1: S_U1, D_U1; leg 2: S_U2, D_U2) to generate V_grid ≥ 0 V, two dual-buck legs (leg 3: S_D1, D_D1; leg 4: S_D2, D_D2) to generate V_grid < 0 V, two blocking diodes (D_U3, D_D3) to prevent the current flowing through the body diode of switch during freewheeling mode, and two unfolding switches (S_U3, S_D3) to determine the polarity of the output current. Legs 1 and 4 are connected to L₁, and legs 2 and 3 are connected to L₂. Therefore, the proposed inverter requires two inductors, unlike interleaved dual-buck inverters, which have four legs and one inductor per leg. The proposed inverter works with the switching states and leg voltages V_{AN_on} and V_{AN_off} in

Table 1. Switching states and input voltages for inductors in the proposed inverter.

Vgrid	≥0 V	<0 V
SU1	ON/OFF	OFF
SU2	ON/OFF	OFF
SU3	ON	OFF
SD1	OFF	ON/OFF
SD2	OFF	ON/OFF
SD3	OFF	ON
VAN_on	Vin	−Vin
VAN_off	0	0

. Leg switches S_U1, S_U2, S_D1, and S_D2 operate at a fixed switching frequency f_s = 1/T_s, where T_s is the switching period. The switching duty D is varied to produce a sinusoidal output voltage $V_{grid}(t)=V_g\sin (\omega t)$.

The simplified gate signals (Figure 3) for the proposed inverter show that legs 1 and 2 operate for V_grid > 0 V and legs 3 and 4 operate for V_grid < 0 V. S_U3 turns for V_grid ≥ 0 V and S_D3 turns on for V_grid < 0 V. To obtain interleaved dual-buck operation, the switching phase differences between S_U1 and S_U2 and between S_D1 and S_D2 are set to T_s/2. The difference in switching phases reduces ZCD and prevents shoot-through without inserting dead time between switching pulses (Table 1).

When V_grid > 0 V, the current i_L1 and voltage V_L1 waveforms of the inductor L₁ (Figure 4a) consist of three operating modes: Mode 1 during which the input energy is delivered to L₁ and the load; Mode 2 during which the stored energy in L₁ is delivered to the load; and Mode 3 during which the stored energy in L₁ = 0; Mode 3 occurs only when the inverter operates in DCM.

Mode 1 starts at $t_0=(n-1)T_s$ by turning on S_U1 (Figure 4b), where the integer $n$ is a switching sequence number. During this mode, the output voltage $V_{AN}$ of leg 1 is $V_{in}$. The inductor current $i_{L1}(t)$ increases as t increases, because $V_{L1}=V_{AN}-V_{grid}>0$ V and

$$i_{L1}(t)=i_{L1}(t_0)+\frac{1}{L_1}{\displaystyle {\int }_{t_0}^t{V}_{L1}}(t)dt.$$

(1)

Mode 2 starts at $t_1=(n-1+D)T_s$ by turning off S_U1 (Figure 4c). During this mode, $V_{AN}$ is 0 V. $i_{L1}(t)$ decreases as t increases because $V_{L1}=V_{AN}-V_{grid}<0$ V and

$$i_{L1}(t)=i_{L1}(t_1)+\frac{1}{L_1}{\displaystyle {\int }_{t_1}^t{V}_{L1}}(t)dt.$$

(2)

Mode 3 starts at $t_2=(n-1+\Delta )T_s$ where $\Delta T_s$ is duration of $i_{L1}(t)>0$, when D_U1 is turned off (Figure 4d). This mode is skipped when $\Delta =1$, i.e., when the inverter is operating in CCM. During this mode, $V_{AN}=V_{grid}$ because $i_{L1}(t)=0$ and the energy stored in L₁ is 0.

The voltage $V_{AN}$ of node A with respect to node N equals to $V_{grid}+V_{L1}(t)$. The switching states (Table 1) produce $V_{AN}=V_{in}$ in Mode 1, $V_{AN}=0$ V in Mode 2, and $V_{AN}=V_{grid}$ in Mode 3. The average of $V_{AN}$ for one switching period is expressed as

$$V_{AN\_avg}=V_{grid}+V_{L1\_avg}=V_{grid}+L_1\frac{d{i}_{L1\_avg}}{dt}.$$

(3)

S_U1 operates with a switching duty of D = D_SU1. $V_{AN\_avg}$ can also be expressed as

$$V_{AN\_avg}=V_{in}{D}_{SU1}+V_{grid}\left(1-\Delta \right),$$

(4)

because V_AN = V_in in Mode 1, V_AN = 0 V in Mode 2, and V_AN = V_grid in Mode 3. Solving for $\Delta$ using (3) and (4) yields

$$\Delta =\frac{V_{in}{D}_{SU1}}{V_{grid}}-\frac{L_1}{V_{grid}}\frac{d{i}_{L1\_avg}}{dt}.$$

(5)

$i_{L1\_avg}$ is calculated using Equations (1) and (2) as

$$i_{L1\_avg}\approx i_{L1}(t_0)+\left(\frac{V_{in}-V_{grid}(t_0)}{2L_1}\right)D_{SU1}{T}_s\Delta .$$

(6)

To achieve a power factor of 1, the time average of output current $i_{o\_avg}$ should be $I_o\sin (\omega t)$ for $V_{grid}(t)=V_g\sin (\omega t)$. The inverter has $L_1=L_2=L$ and operates in interleaved dual-buck mode, so $i_{o\_avg}=2i_{L1\_avg}$. When the inverter operates in DCM, $D_{SU1}$ at $t=t_0$ to produce sinusoidal $i_{o\_avg}$ is obtained using Equations (5) and (6), $2\pi f_s>>\omega$ and $i_{L1}(t_0)=0$ as

$$D_{SU1}=\sqrt{\frac{L{I}_o{V}_g{\sin }^2(\omega t)}{V_{in}\left(V_{in}-2V_g\sin (\omega t)\right)T_s}+{\left(\frac{\omega L{I}_o\cos (\omega t)}{4V_{in}}\right)}^2}+\frac{\omega L{I}_o\cos (\omega t)}{4V_{in}}.$$

(7)

When the inverter is operating in CCM, $\Delta =1$ and $D_{SU1}$ at $t=t_0$ is obtained using Equation (5) as

$$D_{SU1}=\frac{V_g\sin (\omega t)}{V_{in}}+\frac{\omega L{I}_o\cos (\omega t)}{2V_{in}}.$$

(8)

The DCM interval during which the inverter operates in DCM is calculated using Equations (5), (7), and $\Delta \le 1$ as

$$0<\omega t\le {\sin }^{-1}\left(\frac{V_{in}}{V_g}\left(1-\frac{L{I}_o}{V_g{T}_s}\right)\right)$$

(9)

when V_grid increases, and

$$\pi -{\sin }^{-1}\left(\frac{V_{in}}{V_g}\left(1-\frac{L{I}_o}{V_g{T}_s}\right)\right)\le \omega t<\pi ,$$

(10)

when V_grid decreases.

The condition for operating the inverter only in CCM is obtained by setting the argument of arcsine in Equations (9) and (10) less than 0, and is given as

$$I_o>\frac{V_g{T}_s}{L},$$

(11)

and the condition for operating the inverter only in DCM is obtained by setting the argument of arcsine in Equations (9) and (10) greater than 1, and is given as

$$I_o<\frac{V_g{T}_s}{L}\left(1-\frac{V_g}{V_{in}}\right).$$

(12)

The waveforms i_L2 and V_L2 of the inductor L₂ for V_grid > 0 V are the same as i_L1 and V_L1 except that they are delayed by T_s/2.

The waveforms i_L1, V_L1, i_L2, and V_L2 for V_grid < 0 V are identical to the waveforms i_L2, V_L2, i_L1, and V_L1 for V_grid > 0 V, respectively, except that the polarity is reversed.

2.2. Design Constraint for L₁ and L₂

The inverter must operate at $I_o\le I_{o,\max }$. The highest switching duty $D_{SU1\_\max }$ of S_U1 is calculated using Equation (8) as

$$D_{SU1\_\max }=\frac{\sqrt{4V_g^2+{(\omega L{I}_{o\_\max })}^2}}{2V_{in}}<1$$

(13)

which results in the upper bound of $L_1=L_2=L$ as

$$L<\frac{2\sqrt{V_{in}^2-V_g^2}}{\omega I_{o\_\max }}.$$

(14)

This condition gives $L<103.44$ mH when $P_o=2$ kW and $I_{o\_\max }=12.9$ A.

The current and voltage waveforms for $L_2$ are same as those for $L_1$, except the time delay by $T_s/2$; hence, the output current ripple $i_{o\_ripple}$ of the proposed inverter can be calculated using Equations (1), (2) and (8) as

$$i_{o\_ripple}=\frac{V_{in}{T}_s}{L}D\left(1-2D\right).$$

(15)

for 0 < D < 1/2 and

$$i_{o\_ripple}=\frac{V_{in}{T}_s}{L}\left(1-D\right)\left(2D-1\right).$$

(16)

for 1/2 < D < 1; the highest $i_{o\_ripple}$ occurs at D = 1/4 or 3/4. After allowing the highest $i_{o\_ripple}$ of 1 A at P_o = 2 kW and $f_s=20$ kHz (this condition corresponds to THD < 3%), the lower bound of L is obtained using Equations (15) and (16) as

$$L\ge \frac{V_{in}{T}_s}{8i_{o\_ripple\_\max }}\approx 2.5\mathrm{mH}.$$

(17)

$L_{\min }=2.5$ mH was used in the experimental inverters to minimize the inductor size.

2.3. Controller Design

The controller (Figure 5) was designed using Texas Instrument’s TMS320F28335 digital signal processor (DSP). This controller inputs V_grid, i_{o_avg}, and V_in and uses the D-Q axis control method [17] to produce gating signals S_U1 − S_U3 and S_D1 − S_D3 that can generate a sinusoidal i_{o_avg}. The controller consists of a phase-locked loop (PLL), a D-Q axis controller, and a gate pulse generator. The DSP operates at a clock frequency f_clk = 1/T_clk = 150 MHz and the sampling frequency is the same as the switching frequency f_s = 1/T_s = 20 kHz. Thus, the sampling sequence number n is in the range of 0 ≤ n ≤ 332 when the grid frequency f = ω/2π = 60 Hz, and clock sequence number j is in the range of 0 ≤ j ≤ 7499.

The PLL (Figure 6) sets n = 0 and starts to operate when V_grid = 0 and the enable signal EN = 1. This circuit inputs V_grid and estimates the amplitude V_g and phase $\widehat{\theta }=\widehat{\omega }t$ of V_grid. Using $V_{grid}[n]=V_g\sin (\theta [n])$, the PLL generates a virtual grid-voltage V_{grid_qs} as

$$V_{grid\_qs}[n]=V_g\cos (\theta [n])$$

(18)

$\widehat{\theta }[0]$ has been set to 0 if V_{grid_}qs [0] ≥ 0 and to π otherwise. Thus, the initial estimation error $e_{\theta }[0]=\theta [0]-\widehat{\theta }[0]$ is very small. V_grid and V_{grid_qs} are transformed into the voltages V_{grid_d} and V_{grid_q} in the synchronous reference frame as

$$\left(\begin{array}{c}{V}_{grid\_d}\\ V_{grid\_q}\end{array}\right)=\left(\begin{array}{cc}\sin (\widehat{\theta }[n])& \cos (\widehat{\theta }[n])\\ \cos (\widehat{\theta }[n])& -\sin (\widehat{\theta }[n])\end{array}\right)\left(\begin{array}{c}{V}_{grid\_ds}\\ V_{grid\_qs}\end{array}\right)$$

(19)

Because

$$V_{grid\_d}=V_g\cos \left(\theta [n]-\widehat{\theta }[n]\right)\approx V_g$$

(20)

$$V_{grid\_q}=V_g\sin \left(\theta [n]-\widehat{\theta }[n]\right)\approx V_g\left(\theta [n]-\widehat{\theta }[n]\right)$$

(21)

when $\widehat{\theta }[n]\approx \theta [n]$, V_g and $e_{\theta }[n]=\theta [n]-\widehat{\theta }[n]$ can be calculated using Equations (20) and (21). The PLL loop filter for a proportional-integral (PI) control produces

$$\widehat{\theta }[n]=T_s{\displaystyle \sum _{m=0}^n\left({\omega }_{set}+k_{p\_pll}{e}_{\theta }[m]+k_{i\_pll}{T}_s{\displaystyle \sum _{i=0}^m{e}_{\theta }[i]}\right)}$$

(22)

This equation is equivalent to

$$\widehat{\theta }(s)=\frac{k_{p}s+k_i}{s^2+k_{p}s+k_i}\theta (s)+\frac{{\omega }_{set}}{s^2+k_{p}s+k_i}$$

(23)

in the s-domain, where s is the complex frequency. The final value theory $\underset{s\to 0}{{\displaystyle \lim }}s\widehat{\theta }(s)=\underset{t\to \infty }{{\displaystyle \lim }}\widehat{\theta }(t)$ of the Laplace transform yields $\underset{t\to \infty }{{\displaystyle \lim }}\widehat{\theta }(t)=\underset{t\to \infty }{{\displaystyle \lim }}\theta (t)$, i.e., $\widehat{\theta }\approx \theta =\omega t$ under steady state. (k_p = 2000 and k_i = 0.1 have been chosen for the experimental inverter; these values result in at a zero at s = −0.00005 and two poles at s ≈ −0.00005 and −2000, so the loop filter operates as a first-order system with a cutoff frequency f_c ≈ 2000/2π Hz = f_s/20π ≈ 5 × 60 Hz.)

The D-Q axis controller (Figure 7) consists of a CCM duty-calculator and a duty compensator. The CCM duty-calculator inputs i_{o_avg} and V_in from the inverter, and $\widehat{\theta }$ and V_g from the PLL. In the CCM duty-calculator, i_{o_avg} = i_{o_ds} is delayed by π/2 to obtain the virtual current i_{o_qs} of i_{o_avg}. The D-Q transformation separates i_{o_avg} into a D component I_{o_d} parallel to the grid voltage and a Q component I_{o_q} orthogonal to the grid voltage:

$$\left(\begin{array}{c}{I}_{o\_d}\\ I_{o\_q}\end{array}\right)=\left(\begin{array}{cc}\sin (\widehat{\theta }[n])& \cos (\widehat{\theta }[n])\\ \cos (\widehat{\theta }[n])& -\sin (\widehat{\theta }[n])\end{array}\right)\left(\begin{array}{c}{i}_{o\_ds}\\ i_{o\_qs}\end{array}\right)$$

(24)

For given I_{0_d} and I_{o_q}, the circuit topology results in the D-Q components of V_AN in the synchronous reference frame as

$$\left(\begin{array}{c}{V}_{AN\_d}\\ V_{AN\_q}\end{array}\right)=\left(\begin{array}{c}{V}_g\\ 0\end{array}\right)+\frac{\omega L}{2}\left(\begin{array}{c}-I_{o\_q}\\ I_{o\_d}\end{array}\right)+\frac{L}{2}\frac{d}{dt}\left(\begin{array}{c}{I}_{o\_d}\\ I_{o\_q}\end{array}\right),$$

(25)

and the D-Q components of the switching duty as

$$\left(\begin{array}{c}{D}_d\\ D_q\end{array}\right)=\frac{1}{V_{in}}\left(\begin{array}{c}{V}_g\\ 0\end{array}\right)+\frac{\omega L}{2V_{in}}\left(\begin{array}{c}-I_{o\_q}\\ I_{o\_d}\end{array}\right)+\frac{L}{2V_{in}}\frac{d}{dt}\left(\begin{array}{c}{I}_{o\_d}\\ I_{o\_q}\end{array}\right),$$

(26)

because $V_{AN\_d}=V_{in}{D}_d$ and $V_{AN\_q}=V_{in}{D}_q$. The D-Q axis controller inputs I_{o_d_ref} and I_{o_q_ref} as the reference values of I_{o_d} and I_{o_q}, respectively, and calculates the errors $e_d[n]=I_{o\_d\_ref}-I_{o\_d}$ and $e_q[n]=I_{o\_q\_ref}-I_{o\_q}$. Then, the controller generates the D-Q components of the switching duty for CCM operation:

$$\left(\begin{array}{c}{D}_d[n]\\ D_q[n]\end{array}\right)=\frac{1}{V_{in}}\left(\frac{V_g}{0}\right)+\frac{\omega L}{2V_{in}}\left(\begin{array}{c}-I_{o\_q}[n]\\ I_{o\_d}[n]\end{array}\right)+\frac{k_p}{V_{in}}\left(\begin{array}{c}{e}_d[i]\\ e_q[n]\end{array}\right)+\frac{k_i{T}_s}{V_{in}}{\displaystyle \sum _{i=0}^n\left(\begin{array}{c}{e}_d[i]\\ e_q[i]\end{array}\right)}$$

(27)

Both D and Q components have equivalent closed-loop transfer function in the s-domain as

$$\frac{I_{o\_d}(s)}{I_{o\_d\_ref}(s)}=\frac{I_{o\_q}(s)}{I_{o\_q\_ref}(s)}=\frac{k_{p}s+k_i}{L{s}^2+k_{p}s+k_i}\equiv H(s).$$

(28)

k_p = 5 and k_i = 25 have been chosen for the H(s) of the experimental inverter. These values result in a zero at s = −5 and two poles at s ≈ −5.012, s ≈ −1944.99. The zero at s = −5 is close enough to cancel the pole at s ≈ −5.012; hence, H(s) operates like a first-order system with a cutoff frequency f_c ≈ 2000/2π Hz = f_s/20π ≈ 5 × 60 Hz [18].

To operate the inverter with a power factor of 1, the reference inputs must be I_{o_d_ref} = I_o = 2P_o/V_g and I_{o_q_ref} = 0; therefore, I_{o_d} → I_{o_d_ref} = I_o and I_{o_q} → I_{o_q_ref} = 0 under steady state. Thus, the inverse D-Q transform produces the switching duty D_CCM for CCM operation as

$$D_{CCM}=D_{ds}=D_d\sin (\omega t)+D_q\cos (\omega t)=\frac{V_g\sin (\omega t)}{V_{in}}+\frac{\omega L{I}_o\cos (\omega t)}{2V_{in}}$$

(29)

that is given in Equation (8).

The duty compensator inputs V_in from the inverter, $\widehat{\theta }$ and V_g from the PLL, and I_{o_d_ref} from CCM duty-calculator. Then, the compensator uses in Equations (7) and (8) to calculate the steady-state duty difference ΔD between the switching duties for CCM and DCM operations. ΔD is given by

$$\begin{array}{ll}\Delta D[n]& ={\left(\frac{L{I}_{o\_d\_ref}{V}_g{\sin }^2(\widehat{\theta }[n])}{V_{in}\left(V_{in}-2V_g\sin (\widehat{\theta }[n])\right)T_s}+{\left(\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}}\right)}^2\right)}^{1/2}\\ & -\frac{V_g\sin (\widehat{\theta }[n])}{V_{in}}-\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}}.\end{array}$$

(30)

The time fraction Δ in Equation (5) for which $i_L\ne 0$ is calculated using Equation (7) as

$$\begin{array}{l}\Delta =\frac{V_{in}}{V_g\sin (\widehat{\theta }[n])}({\left(\frac{L{I}_{o\_d\_ref}{V}_g{\sin }^2(\widehat{\theta }[n])}{V_{in}\left(V_{in}-2V_g\sin (\widehat{\theta }[n])\right)T_s}+{\left(\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}}\right)}^2\right)}^{1/2}\\ \hspace{1em}+\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}})-\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{2V_g\sin (\widehat{\theta }[n])}<1\end{array}$$

(31)

which yields

$$\begin{array}{l}\sqrt{\frac{L{I}_{o\_d\_ref}{V}_g{\sin }^2(\widehat{\theta }[n])}{V_{in}\left(V_{in}-2V_g\sin (\widehat{\theta }[n])\right)T_s}+{\left(\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}}\right)}^2}+\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{4V_{in}}\\ <\frac{V_g\sin (\widehat{\theta }[n])}{V_{in}}+\frac{\omega L{I}_{o\_d\_ref}\cos (\widehat{\theta }[n])}{2V_{in}}\end{array}$$

(32)

This equation shows that the switching duty in Equation (7) for DCM operation is always smaller than the one in Equation (8) for CCM operation. Thus, the controller uses $D_{SU1}[n]=D[n]=D_{CCM}[n]+\Delta D[n]$ when ΔD[n] < 0, and the inverter operates in DCM. Otherwise, the controller sets ΔD[n] = 0, and the inverter operates in CCM.

The gate pulse generator (Figure 8) inputs D_SU1 form the D-Q axis controller and generates gate pulses for S_U1 − S_U3 and S_D1 − S_D3. In the gate pulse generator, two saw-tooth-signals S_c[j] and S_cp[j] are generated using two 16-bit up/down (U/D) counters; at each clock (clk) edge, the outputs S_c[j] and S_cp[i] of U/D counters increase by 1 when U/D = UP and decrease by 1 when U/D = DOWN. Initial values of saw-tooth signals are Sc[0] = 0, Scp[0] = Ts/(2Tclk), U/D1[0] = UP, and U/D2[0] = DOWN to yield an interleave operation.

At each clock edge, S_c[j] increases by 1 for nT_s ≤ t < (n+(1/2))T_s during which U/D₁ is UP, and S_c[j] decreases by 1 for (n+(1/2))T_s ≤ t < (n+1)T_s during which U/D₁ is DOWN. When S_c[j] < 0, U/D₁ changes to UP and the next sequence begins. S_cp[j] decreases by 1 for nT_s ≤ t < (n+(1/2))T_s during which U/D₂ is DOWN, and S_cp[j] increases by 1 for (n+(1/2))T_s ≤ t < (n+1)T_s during which U/D₂ is UP. U/D₂ changes to DOWN when S_cp[j] < 0, and the next sequence begins. Thus, S_cp[j] is a time-delayed signal of S_c[j] by T_s/2, the maximum values of S_c[j] and S_cp[j] are T_s/(2T_clk), and the minimum values of S_c[j] and S_cp[j] are 0. To generate PWM signals using the saw-tooth signals, a reference signal R_h[n] is generated using D_SU1 and T_s/(2T_clk) as

$$R_h[n]=\frac{T_s}{2T_{clk}}\left|D_{SU1}[n]\right|.$$

(33)

R_h[n] is stored in the shadow register of the PWM generation module in TMS320F28335 and transferred to the comparator reference-input Ref[n] when S_C[j] = 0. Two comparators check the sign of V_grid[n]: C₃ = 1 and C₄ = 0 for V_grid[n] ≥ 0, otherwise C₃ = 0 and C₄ = 1 (

Table 2. Input and output relationship of comparator array.

Output	i + n	i − n
C1	Ref[n]	Sc[j]
C2	Ref[n]	Scp[j]
C3	Vgrid[n]	0
C4	0	Vgrid[n]

). The other comparators output two PWM signals: C₁ = 1 for Ref[n] > S_c[j] and C₂ = 1 for Ref[n] > S_cp[j]. Finally, the logic gates produce gate control pulses S_U1 = C₁∙C₃, S_U2 = C₂∙C₃, S_U3 = C₃, S_D1 = C₁∙C₄, S_D2 = C₂∙C₄, and S_D3 = C₄.

3. Experimental Results and Discussions

The proposed inverter (Figure 9a,

Table 3. Components for the experimental inverters.

Components		IDBI [9]	FBI	Proposed Inverter
HF Switches	Name	FCH110N65F	FCH110N65F	FCH110N65F
	Price ($)	5.03	5.03	5.03
	Number	4 (SU1, SU3, SD1, SD2)	4 (S1 - S4)	4 (SU1, SU3, SD1, SD2)
LF Switches	Name	IXFK80N60P3	-	IXFK80N60P3
	Price ($)	5.03	-	5.03
	Number	2 (SU3, SD3)	-	2 (SU3, SD3)
Diodes	Name	30ETH06	-	30ETH06
	Price ($)	1.59	-	1.59
	Number	4 (DU1, DU2, DD1, DD2)	-	6 (DU1 − DU3, DD1 − DD3)
Inductor core	Part Name	EER6062	EC90	EER6062
	Price ($)	4.94	16.17	4.94
	Number	4	2	2
Electrolytic capacitor	Part Name	EKMR451VS N681MA50S	EKMR451VS N681MA50S	EKMR451VS N681MA50S
	Price ($)	2.68	2.68	2.68
	Number	8	8	8
Total costs ($)		77.74	73.9	71.04

) was designed to operate at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz and 150 W ≤ P_o ≤ 2 kW, and it was fabricated and tested using the calculated circuit parameters. An IDBI [9] (Figure 9b, Table 3) and an FBI [1] (Figure 9c, Table 3) were also fabricated and tested for comparison; the circuit elements for these inverters were the same as those for the proposed inverter. The control circuits for all experimental inverters were implemented using the TMS320F28335 digital signal processor (DSP) from Texas Instruments.

The proposed inverter uses two inductors, whereas the IDBI uses four inductors, and the proposed inverter uses a small inductor core (EER6062), whereas the FBI uses a large inductor core. The fabricated inverters had a circuit volume of 160mm × 250 mm × 43.9 mm for the proposed inverter, 450 mm × 550 mm × 43.9 mm for the IDBI, and 380mm × 550 mm × 78.0 mm for the FBI; the proposed inverter reduced 83.8% of the circuit volume compared with the IDBI, and 89.3% compared with the FBI. The circuit cost was $71.04 for the proposed inverter, $77.74 for the IDBI, and $73.9 for the FBI; the proposed inverter saved 8.62% of the circuit cost compared with the IDBI, and 3.87% compared with FBI.

To verify operation of the proposed inverter, the waveforms of switch-control pulses (Figure 10a) were measured at Vin = 400 VDC, V_grid = 220 V_AC/60 Hz, P_o = 2 kW, and f_s = 20 kHz. These waveforms show that the switches operated according to the switching states in Table 1; when V_grid > 0 V, S_U1 and S_U2 operated in PWM mode, S_U3 stayed ON and other switches stayed OFF; when V_grid < 0 V, S_D1 and S_D2 operated in PWM mode, S_D3 stayed ON and other switches stayed OFF. The inductor currents i_L1 and i_L2, and the leg voltages V_{GS_SU1} and V_{GS_SU2} (Figure 10b) show that the inverter operated in an interleaved mode; the phase differences between i_L1 and i_L2, and between V_{GS_SU1} and V_{GS_SU2} were T_s/2. These switching states produced the sinusoidal leg voltage V_AN (Figure 10c).

${\eta }_e$ vs. $P_o$ (Figure 11) was measured at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, 150 W ≤ P_o ≤ 2 kW, and f_s = 20 kHz and 40 kHz, using a PW3336 (HIOKI E.E. Co.) power meter. At f_s = 20 kHz, the proposed inverter had ${\eta }_e$> 98% for $P_o\ge 500$ W, but ${\eta }_e$ for $P_o$< 500 W decreased as $P_o$ decreased because the inverter operated in DCM. The highest power conversion efficiency ${\eta }_{e\max }$ of the proposed inverter was 98.5% at P_o = 1300 W when the power loss P_DSP of the gate control/drive circuit was included. (${\eta }_{e\max }$= 99.2% at P_o = 500 W when P_DSP was excluded.) The FBI does not use the interleaved buck inversion; hence, the switching and conduction losses in the current path were higher in the FBI than in the proposed inverter; as a result, the FBI had the lowest ${\eta }_e$ among the inverters tested. The IDBI has a circuit structure similar to the proposed inverter and operates in interleaved mode, so ${\eta }_e$ of the IDBI was very close to that of the proposed inverter. However, the proposed inverter requires two inductors to operate the inverter in interleaved mode, while the IDBI requires four inductors; hence, the proposed inverter can be implemented in a smaller size.

Losses (Figure 12) of the experimental inverters were analyzed at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, f_s = 20 kHz, P_o = 2 kW and 150 W, and reactive output power Q_o = 0 volt-ampere-reactive (VAR). The switching losses P_SW were 13.2 W for proposed, 13.89 W for IDBI, and 29.71 W for FBI at P_o = 2kW, and P_SW were 2.18 W for proposed, 2.48 W for IDBI, and 8.42 W for FBI at P_o = 150 W. The inverters operated at V_SW = V_in and N_SW = 666 for proposed and IDBI, and V_SW = V_in and N_SW = 1333 for FBI, where N_sw is the total switching number for one cycle of V_grid. Thus, the proposed inverter and IDBI had the lowest P_SW. The inductor loss P_IND was 9.25 W for proposed, 10.33 W for IDBI, and 66.32 W for FBI at P_o = 2kW and 0.155 W for proposed, 0.162 W for IDBI, and 0.66 W for FBI at P_o = 150 W. The proposed inverter uses interleaved inputs; hence, the inductor current i_L is half of the i_L of FBI. Moreover, the proposed inverter uses small inductors with fewer turns than that of the FBI. Thus, FBI had the highest P_IND. The diode loss P_D was 7.04 W for proposed, 6.45 W for IDBI, and 0 for FBI at P_o = 2 kW, and P_D was 0.907 W for proposed, 0.885 W for IDBI, and 0 for FBI at P_o = 150 W. The power loss P_DSP of the gate control/drive circuit was 6.02 W for proposed, 6.19 W for IDBI, and 6.48 W for FBI at both P_o = 150 W and P_o = 2 kW. The total power loss P_loss at P_o = 2 kW was 35.53 W for proposed, 36.87 W for IDBI, and 102.51 W for FBI, and the power conversion efficiency ${\eta }_e$ at P_o = 2 kW was 98.2% for proposed, 98.1% for IDBI, and 94.9 % for FBI. P_loss at P_o = 150W was 9.279 W for proposed, 9.717 W for IDBI, and 15.5 W for FBI, and ${\eta }_e$ at P_o = 150 W was 93.8% for proposed, 93.5% for IDBI, and 89.6 % for FBI.

The temperature $T_{SW}$ of switch vs. time of operation (Figure 13) was measured while operating the experimental inverters at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, P_o = 2 kW, and f_s = 20 kHz. $T_{SW}$ was stabilized at ~52 °C (S_U1, S_U2, S_D1, S_D2) and ~55 °C (S_U3, S_D3) in the proposed inverter, ~54 °C (S_U1, S_U2, S_D1, S_D2) and ~58 °C (S_U3, S_D3) in the IDBI, and at ~110 °C in FBI. P_SW at P_o = 2 kW were 13.2 W for proposed, 13.89W for IDBI, and 29.71 W for FBI; therefore, T_sw of the proposed inverter and IDBI was half that of FBI.

THD of $i_o$ vs. P_o (Figure 14) was also measured at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, P_o = 150 W ~ 2 kW, and f_s = 20 kHz. THD at P_o = 2 kW was 0.66% for proposed and IDBI and 3.25% for FBI; FBI had the highest THD because this inverter produced a ZCD during the dead-time period. THD at P_o = 150 W was 16.6% for IDBI and the proposed inverter when the switching duties for the inverters were controlled using the CCM control (given in (8)). At a low P_o, the proposed inverter operated in DCM for some time-interval of sinusoidal V_grid, as discussed in Section 2.2. This operation produced a distortion in I_o when the inverters were operated under CCM control only.

When the switching duties for IDBI and the inverters were controlled using the proposed DCM+CCM control (a combination of the CCM control and the DCM control given in Equation (7)), the THD at P_o = 150 W was reduced to 4.1% because the combined DCM+CCM control reduced the distortion in I_o significantly.

When f_s was increased to 40 kHz, THD of i_o at P_o = 2 kW was 0.63% for proposed and IDBI and 7.24% for FBI. The FBI nearly doubled the THD at f_s = 40 kHz compared to the value at f_s = 20 kHz, because the change increased the effect of dead-time on the switching duty. The THD at P_o = 150 W was 7.41% for the proposed inverter using CCM control, 3.98% for the proposed inverter using DCM+CCM control, and 3.51% for FBI. The DCM operating time was reduced at higher f_s (Equations (9) and (10)); hence, THD of the proposed inverter decreased as f_s increased; a DCM control near the zero crossing point increased i_L. In contrast, the THD for FBI increased as f_s increased because the impact of dead-time on the switching duty increased.

The waveforms of i_o and i_{o_avg} for the experimental inverters (Figure 15) were measured at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, f_s = 20 kHz, P_o = 150 W, Q_o = 0 VAR, and I_o = 0.95 A. The cutoff frequency of the low-pass filter for i_{o_avg} measurement was 2 kHz (=f_s/10). The inverters were controlled using CCM or DCM+CCM control. The waveforms of i_o show that the proposed inverter had the lowest switching ripple of i_o, and the waveforms of i_{o_avg} show that the DCM+CCM control of the proposed inverter achieved the best sinusoidal waveform. The harmonic components of i_o (Figure 16) show that harmonics of i_o of FBI were slightly higher than those of the proposed inverter because the proposed inverter operated as an interleaved dual buck inverter.

The dynamic responses of the proposed inverter (Figure 17) were measured for a step change of P_o from 2 kW to 1 kW and a step change of P_o from 1 kW to 2 kW; the operating conditions for this measurement were V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, f_s = 20 kHz, and Q_o = 0 VAR. For both P_o changes, the output current i_o did not overshoot, and the transient time of i_o was < 2 ms, which is ~1/8 of the sinusoidal period at 60 Hz. PF, THD, and i_o of the proposed inverter were measured for P_o = 666.6 W, 1.333 kW, and 2 kW at V_in = 400 V_DC, V_grid = 220 V_AC/60 Hz, f_s = 20 kHz, and line impedance Z = 0.4 + j0.25 Ω. The measured PF was 0.9973 at P_o = 666.6 W (33% of the rated power), 0.9985 at P_o = 1.333 kW (66% of the rated power), and 0.9992 at P_o = 2 kW (100% of the rated power). The measured THD of i_o was 4.20% at P_o = 666.6 W, 3.68% at P_o = 1.333 kW, and 3.43% at P_o = 2 kW. These results fulfill most grid-connected inverter standards for renewable energy [19,20,21,22].

Comparisons (

Table 4. Circuit parameters and experimental results for experimental inverters. Parenthesis contain peak switch voltages and currents measured at V_in = 404 V.

Circuit Parameters		Proposed Inverter	IDBI [9]	FBI
# of switches		6	6	4
# of diodes		6	4	0
# of inductors		2	4	2
Vsw,max	Unfolding	Vin (404 V)	Vin (404 V)	-
	Switching	Vin (413 V)	Vin (415 V)	Vin (423 V)
Isw,max	Unfolding	Io (13.1 A)	Io (13.5 A)	-
	Switching	Io/2 (5.8 A)	Io/2 (6.0 A)	Io (13.5 A)
Inductance		2.5 mH	2.5 mH	2.5 mH
THD at Po = 2 kW		0.66%	0.66%	3.25%
Maximum efficiency		98.5%	98.4%	95.2%
Efficiency at Po = 2 kW		98.3%	98.2%	95.0%

) of the circuit parameters and experimental results demonstrate the superiority of the proposed inverter. The proposed inverter has the following advantages: (1) proposed inverter requires two inductors, whereas IDBI requires four inductors; hence, the proposed inverter can be implemented with lower cost and smaller volume than IDBI; (2) it uses interleaved operation, which reduces the current stress of the switch by 1/2 of that in FBI; (3) the number of switching for one period of V_grid in the proposed inverter is 1/2 of that in FBI; hence, the switching loss is reduced; and (4) ${\eta }_e$ at $P_o$ = 2 kW is as high as 98.3%, compared to 95.0% for FBI. These advantages indicate that the proposed inverter is useful for high-power dc-ac power conversion.

4. Conclusions

This paper proposes an inverter that can achieve high power conversion efficiency η_e at high output power P_o. The inverter uses a dual-buck structure to eliminate zero-cross distortion, operates in an interleaved mode to reduce the current stress of switch, and uses DCM + CCM combined control to reduce the output current distortion at low output power. The size and weight of the circuit are reduced by decreasing the number of inductors and by using blocking diodes; the proposed inverter could reduce 83.8% of the circuit volume compared with IDBI and 89.3% compared with FBI, and it could save 8.62% of the circuit cost compared with IDBI and 3.87% compared with FBI. When the experimental inverter was operated at an input voltage of 400 V_DC, an output voltage of 220 V_AC/60 Hz, and switching frequency of 20 kHz, η_e was > 94% at 150 W ≤ P_o ≤ 2 kW, 98.5% at P_o = 1300 W, and 98.3% at P_o = 2 kW. The total harmonic distortion was 0.66% at P_o = 2kW. The proposed inverter is well-suited for high power dc-ac power conversion.