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Application of FPGA-Based Sensor Systems
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Application of FPGA-Based Sensor Systems

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Communications".

Deadline for manuscript submissions: 20 September 2024 | Viewed by 3344

Special Issue Editor

Dr. Nicola Lusardi

E-Mail Website
Guest Editor
Department of Electronics, Information and Bioengineering, Politecnico di Milano, Milano, Italy
Interests: digital electronic; time-to-digital converter; digital-to-time converter; field programmable gate array; system-on-chip

Special Issue Information

Dear Colleagues,

The development of intelligent sensor technology with the capacity for integrated processing intelligence is crucial for a variety of reasons. It enables immediate digitization of sensor-detected information, avoiding losses or alterations during transmission, and facilitates rapid data analysis and real-time response. This proximity between the sensor and intelligence optimizes systems, reducing latency and communication overhead. The use of programmable parallel processing units such as field-programmable gate arrays (FPGAs) provides the capability of executing operations in parallel, allowing for increased speed and channel capacity. Furthermore, the reprogrammability offered by FPGA solutions makes these sensors more flexible and quicker to design than fully integrated solutions. Moreover, through processing time-mode techniques, it is sometimes possible to completely eliminate the fragile, sensitive, and often poorly integrable read-out electronics that separates the sensor from the FPGA, resulting in a more compact and cost-effective system.

The purpose of Sensor is to promote the scientific dissemination of intelligent and cutting-edge sensing technology. Therefore, a sensor that integrates processing units, especially if they are programmable and parallel such as field-programmable gate arrays (FPGAs), precisely pushes in this direction.

Dr. Nicola Lusardi
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • integrated processing intelligence
  • digitization of sensor data
  • real-time processing
  • latency reduction
  • communication overhead
  • programmable parallel processing
  • field-programmable gate arrays (FPGAs)
  • time-mode

Published Papers (3 papers)

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Research

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10 pages, 2235 KiB  
Communication
FFT-Based Simultaneous Calculations of Very Long Signal Multi-Resolution Spectra for Ultra-Wideband Digital Radio Frequency Receiver and Other Digital Sensor Applications
by Chen Wu and Michael Low
Sensors 2024, 24(4), 1207; https://doi.org/10.3390/s24041207 - 13 Feb 2024
Cited by 1 | Viewed by 540
Abstract
The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) [...] Read more.
The discrete Fourier transform (DFT) is the most commonly used signal processing method in modern digital sensor design for signal study and analysis. It is often implemented in hardware, such as a field programmable gate array (FPGA), using the fast Fourier transform (FFT) algorithm. The frequency resolution (i.e., frequency bin size) is determined by the number of time samples used in the DFT, when the digital sensor’s bandwidth is fixed. One can vary the sensitivity of a radio frequency receiver by changing the number of time samples used in the DFT. As the number of samples increases, the frequency bin width decreases, and the digital receiver sensitivity increases. In some applications, it is useful to compute an ensemble of FFT lengths; e.g., 2P−j for j=0, 1, 2, …, J, where j is defined as the spectrum level with frequency resolution  2j·Δf. Here Δf is the frequency resolution at j=0. However, calculating all of these spectra one by one using the conventional FFT method would be prohibitively time-consuming, even on a modern FPGA. This is especially true for large values of P; e.g., P≥20. The goal of this communication is to introduce a new method that can produce multi-resolution spectrum lines corresponding to sample lengths  2P−j for all J+1 levels, concurrently, while one long 2P-length FFT is being calculated. That is, the lower resolution spectra are generated naturally as by-products during the computation of the 2P-length FFT, so there is no need to perform additional calculations in order to obtain them. Full article
(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)
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15 pages, 4217 KiB  
Article
Design of A High-Precision Component-Type Vertical Pendulum Tiltmeter Based on FPGA
by Xin Xu, Zheng Chen, Hong Li, Shigui Ma, Liheng Wu, Wenbo Wang, Yunkai Dong and Weiwei Zhan
Sensors 2023, 23(18), 7998; https://doi.org/10.3390/s23187998 - 20 Sep 2023
Viewed by 812
Abstract
This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It [...] Read more.
This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It comprises a pendulum body, a triangular platform, a locking motor and sealing cover, a ratiometric measurement bridge, a high-speed ADC, and an FPGA embedded system. The pendulum body is a plumb-bob-type single-suspension wire vertical pendulum capable of measuring ground tilt in two orthogonal directions simultaneously. It is installed on a triangular platform, sealed as a whole, and equipped with a locking motor to withstand a free-fall impact of 2 m. The system utilizes a differential capacitance ratio bridge in the measurement circuit, replacing analog circuits with high-speed AD sampling and FPGA digital signal processing technology. This approach reduces hardware expenses and interferences from active devices. The system also features online compilation functionality for flexible measurement parameter settings, high reliability, ease of use, and rapid deployment without the need for professional technical personnel. The proposed tiltmeter holds significant importance for further research in geophysics. Full article
(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)
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Review

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32 pages, 6429 KiB  
Review
Binary Neural Networks in FPGAs: Architectures, Tool Flows and Hardware Comparisons
by Yuanxin Su, Kah Phooi Seng, Li Minn Ang and Jeremy Smith
Sensors 2023, 23(22), 9254; https://doi.org/10.3390/s23229254 - 17 Nov 2023
Viewed by 1603
Abstract
Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers {−1,1}. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and [...] Read more.
Binary neural networks (BNNs) are variations of artificial/deep neural network (ANN/DNN) architectures that constrain the real values of weights to the binary set of numbers {−1,1}. By using binary values, BNNs can convert matrix multiplications into bitwise operations, which accelerates both training and inference and reduces hardware complexity and model sizes for implementation. Compared to traditional deep learning architectures, BNNs are a good choice for implementation in resource-constrained devices like FPGAs and ASICs. However, BNNs have the disadvantage of reduced performance and accuracy because of the tradeoff due to binarization. Over the years, this has attracted the attention of the research community to overcome the performance gap of BNNs, and several architectures have been proposed. In this paper, we provide a comprehensive review of BNNs for implementation in FPGA hardware. The survey covers different aspects, such as BNN architectures and variants, design and tool flows for FPGAs, and various applications for BNNs. The final part of the paper gives some benchmark works and design tools for implementing BNNs in FPGAs based on established datasets used by the research community. Full article
(This article belongs to the Special Issue Application of FPGA-Based Sensor Systems)
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