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Nanomaterials
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Semiconductor Nanomaterials for Memory Devices
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Semiconductor Nanomaterials for Memory Devices

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: 31 August 2024 | Viewed by 6436

Special Issue Editors

Prof. Dr. Xianbin Li

E-Mail Website
Guest Editor
State Key Laboratory of Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012, China
Interests: materials physics of phase-change memory; ultrafast optical storage; mechanism of memristor/atomristor; high-through calculation screening of memory materials; defect physics of semiconductors
Prof. Dr. Wei Zhang

E-Mail Website
Guest Editor
Center for Alloy Innovation and Design (CAID), State Key Laboratory for Mechanical Behavior of Materials, Xi'an Jiaotong University, Xi'an 710049, China
Interests: phase-change materials for memory and brain-like computing devices; TEM analysis; glass/amorphous structures; machine-learning potential simulations; optical properties of chalcogenide glass
Prof. Dr. Ming Xu

E-Mail Website
Guest Editor
1. School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China
2. Hubei Yangtze Memory Laboratories, Wuhan 430205, China
Interests: phase-change memory materials and devices; RRAM materials and devices; OTS materials and devices; machine-learning for amorphous structures; mechanisms of ionic transport; metallic glass

Special Issue Information

Dear Colleagues,

Memory Technology is a key component of the modern information society. Its value will be further enhanced in the future big-data era. As a kind of matter carrier for recording data or information, semiconductor nanomaterials increasingly play important roles in memory devices due to their potential advantage of device miniature and high-density integration. The electrical/optical/spin/magnetic/chemical/ferroelectric properties, band structure, atomic structure, defect, and various phases of semiconductor nanomaterials together decide the ways of efficient data encoding, which includes volatile and nonvolatile memories. Their microscopic working mechanism, response to external stimuli, characterization/analysis, growth, optimization/design, and device fabrication of the semiconductor nanomaterials are closely related to memory performances including data retention, power consumption, signal contrast, encoding speed, write/erase cycling and so on. Moreover, some fast-developing memory-related technologies, for example, brain-like or neuromorphic computing devices, also depend on semiconductor nanomaterials.  

Original research articles and reviews are both welcome. Research areas may include (but not limited to) the following:  

  • Nanomaterials, Devices, and Technologies for Phase-Change Memory 
  • Nanomaterials, Devices, and Technologies for Resistive Random-Access Memory 
  • Nanomaterials, Devices, and Technologies for Magnetic/Spin Memory 
  • Nanomaterials, Devices, and Technologies for Ferroelectric Memory 
  • Nanomaterials, Devices, and Technologies for Flash Memory 
  • Nanomaterials, Devices, and Technologies for DRAM/SRAM  
  • Nanomaterials for Neuromorphic Computing/In-Memory Computing Devices 
  • Nanomaterials for Optical Storage/Optical Computation 
  • Nanomaterials for Selector Devices 
  • Two-Dimensional Materials for Memory Devices 
  • Nanotube Materials for Memory Devices 
  • Other Semiconductor Nanomaterials for Memory and Related Devices 
  • Simulation and Theoretical Analysis

The Special Issue “Semiconductor Nanomaterials for Memory Devices” aims at providing an overview of the most recent progress and new developments in the design and utilization of semiconductor nanomaterials for advanced memory devices as well as their related technologies. Here, we are pleased to invite you to contribute works related to this Special Issue. Thank You. 

Prof. Dr. Xianbin Li
Prof. Dr. Wei Zhang
Prof. Dr. Ming Xu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • memory
  • data storage
  • volatile/nonvolatile
  • 2D materials
  • nanomaterials
  • semiconductor
  • PCM
  • RRAM
  • FeRAM
  • MRAM
  • DRAM
  • SRAM
  • flash memory
  • neuromorphic computing
  • selector

Published Papers (6 papers)

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Research

12 pages, 4341 KiB  
Article
Transfer-Free Analog and Digital Flexible Memristors Based on Boron Nitride Films
by Sibo Wang, Xiuhuan Liu, Han Yu, Xiaohang Liu, Jihong Zhao, Lixin Hou, Yanjun Gao and Zhanguo Chen
Nanomaterials 2024, 14(4), 327; https://doi.org/10.3390/nano14040327 - 07 Feb 2024
Viewed by 723
Abstract
The traditional von Neumann architecture of computers, constrained by the inherent separation of processing and memory units, faces challenges, for instance, memory wall issue. Neuromorphic computing and in-memory computing offer promising paradigms to overcome the limitations of additional data movement and to enhance [...] Read more.
The traditional von Neumann architecture of computers, constrained by the inherent separation of processing and memory units, faces challenges, for instance, memory wall issue. Neuromorphic computing and in-memory computing offer promising paradigms to overcome the limitations of additional data movement and to enhance computational efficiency. In this work, transfer-free flexible memristors based on hexagonal boron nitride films were proposed for analog neuromorphic and digital memcomputing. Analog memristors were prepared; they exhibited synaptic behaviors, including paired-pulse facilitation and long-term potentiation/depression. The resistive switching mechanism of the analog memristors were investigated through transmission electron microscopy. Digital memristors were prepared by altering the electrode materials, and they exhibited reliable device performance, including a large on/off ratio (up to 106), reproducible switching endurance (>100 cycles), non-volatile characteristic (>60 min), and effective operating under bending conditions (>100 times). Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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7 pages, 2055 KiB  
Communication
Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States
by Juhee Jeon, Kyoungah Cho and Sangsig Kim
Nanomaterials 2024, 14(2), 210; https://doi.org/10.3390/nano14020210 - 18 Jan 2024
Viewed by 629
Abstract
In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, [...] Read more.
In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state “State 1 (State 0)”. Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width. Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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0 pages, 5391 KiB  
Article
Internal Resistor Effect of Multilayer-Structured Synaptic Device for Low-Power Operation
by Hyejin Kim, Geonhui Han, Seojin Cho, Jiyong Woo and Daeseok Lee
Nanomaterials 2024, 14(2), 201; https://doi.org/10.3390/nano14020201 - 16 Jan 2024
Cited by 1 | Viewed by 825
Abstract
A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal–insulator–metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal–oxide–semiconductor (CMOS) fabrication process. The [...] Read more.
A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal–insulator–metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal–oxide–semiconductor (CMOS) fabrication process. The three types of MIM-structured synaptic devices are compared to assess their effects on reducing the operating power. The obtained results exhibited low-power operation owing to the inserted layers acting as an internal resistor. The modulated operational conductance level and simple MIM structure demonstrate the feasibility of implementing both low-power operation and high-density integration in multilayer synaptic devices. Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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12 pages, 3265 KiB  
Article
Capacitorless One-Transistor Dynamic Random-Access Memory with Novel Mechanism: Self-Refreshing
by Sang Ho Lee, Jin Park, Young Jun Yoon and In Man Kang
Nanomaterials 2024, 14(2), 179; https://doi.org/10.3390/nano14020179 - 12 Jan 2024
Viewed by 964
Abstract
In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the [...] Read more.
In this paper, we propose for the first time a self-refreshing mechanism in a junctionless field-effect transistor (JLFET) based on one-transistor dynamic random-access memory (1T-DRAM) with a silicon-on-insulator (SOI) structure. The self-refreshing mechanism continuously creates holes by appropriately generating impact ionization during the holding process through the application of an appropriate operation bias voltage. This leads to self-refreshing, which prevents the recombination of holes. When using the self-refreshing mechanism for the proposed device, the sensing margins were 15.4 and 12.7 μA/μm at 300 and 358 K, respectively. Moreover, the device achieved an excellent performance retention time of >500 ms, regardless of the temperature of the 1T-DRAM with a single gate. Furthermore, cell disturbance analysis and voltage optimization were performed to evaluate the in-cell reliability of the proposed device. It also showed excellent performance in terms of energy consumption and writing speed. Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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15 pages, 2256 KiB  
Article
Semiempirical Two-Dimensional Model of the Bipolar Resistive Switching Process in Si-NCs/SiO2 Multilayers
by Juan Ramirez-Rios, Karla Esther González-Flores, José Juan Avilés-Bravo, Sergio Alfonso Pérez-García, Javier Flores-Méndez, Mario Moreno-Moreno and Alfredo Morales-Sánchez
Nanomaterials 2023, 13(14), 2124; https://doi.org/10.3390/nano13142124 - 21 Jul 2023
Viewed by 677
Abstract
In this work, the SET and RESET processes of bipolar resistive switching memories with silicon nanocrystals (Si-NCs) embedded in an oxide matrix is simulated by a stochastic model. This model is based on the estimation of two-dimensional oxygen vacancy configurations and their relationship [...] Read more.
In this work, the SET and RESET processes of bipolar resistive switching memories with silicon nanocrystals (Si-NCs) embedded in an oxide matrix is simulated by a stochastic model. This model is based on the estimation of two-dimensional oxygen vacancy configurations and their relationship with the resistive state. The simulation data are compared with the experimental current-voltage data of Si-NCs/SiO2 multilayer-based memristor devices. Devices with 1 and 3 Si-NCs/SiO2 bilayers were analyzed. The Si-NCs are assumed as agglomerates of fixed oxygen vacancies, which promote the formation of conductive filaments (CFs) through the multilayer according to the simulations. In fact, an intermediate resistive state was observed in the forming process (experimental and simulated) of the 3-BL device, which is explained by the preferential generation of oxygen vacancies in the sites that form the complete CFs, through Si-NCs. Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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13 pages, 20953 KiB  
Article
Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps
by Chanyang Park, Jun-Sik Yoon, Kihoon Nam, Hyundong Jang, Minsang Park and Rock-Hyun Baek
Nanomaterials 2023, 13(9), 1451; https://doi.org/10.3390/nano13091451 - 24 Apr 2023
Viewed by 1705
Abstract
The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by [...] Read more.
The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over−programming in measurements. Using a 3D Monte−Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over−programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over−programming and help mitigate the most problematic programming obstacles for multiple−bit techniques. Full article
(This article belongs to the Special Issue Semiconductor Nanomaterials for Memory Devices)
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