Special Issue "Low-Power FPGA Designs for Next-Generation Artificial Intelligence Applications"
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (30 June 2020) | Viewed by 5551
Interests: reconfigurable computing; system on chip; embedded systems
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The deployment of Machine Learning (ML) algorithms in once unexpected fields of application seems to be nowadays unrestrainable. Deep Neural Networks (DNN) are, presently, the most popular application models. Such multilayered networks, characterized by a large number of hidden layers and vast amounts of data to be trained, demand specialized, high-performance, low-power hardware architectures. DNN training and inference are both computation-intensive processes: Training demands a high throughput, whereas inference needs a low latency.
In the last few years, FPGAs and GPUs vendors engaged in a race to offer the best hardware platform that runs computationally-intensive ML algorithms quickly and efficiently. While GPUs are well-suited options for several fields of application, in all power-constrained scenarios, FPGAs are the natural choice. FPGA DNN implementations with reduced arithmetic precision, pruned networks, and custom high-performance hardware implementation lead to both latency and performance per watt advantages over GPUs.
Traditional FPGAs have recently become multi-processor high-performance system-on-chip (SoC). Prominent FPGA vendors rely on fin-FET 3D process technology to integrate unprecedented computational and memorization power in a single flexible chip. Such devices can deliver flexible architectures, as a mix of hardware programmable resources, DPS, RAM blocks and purposely-designed software.
Within the above scenario, this Special Issue focuses on the latest developments in the field of designing low-power high-performance architectures for next-generation ML applications by relying on the latest SoC FPGAs.
Topics include, but are not limited to:
- FPGA implementations of DNN training/inference accelerators
- Applications of reconfigurability in deep learning context
- Domain-specific SoC FPGA architectures for ML
- ML-based systems in IoT under highly constrained energy/power requirements
- Application of approximate computing to FPGA implementations of DNN
- Microarchitectures and Implementations of DNN applications on Heterogeneous FPGAs
- New design methodologies for DNN on FPGAs
Prof. Pasquale Corsonello
Prof. Michael Hübner
Manuscript Submission Information
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