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Hardware Security and Trust
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Hardware Security and Trust

A special issue of Information (ISSN 2078-2489). This special issue belongs to the section "Information and Communications Technology".

Deadline for manuscript submissions: 31 May 2024 | Viewed by 4162

Special Issue Editor

Dr. Paolo Maistri

E-Mail Website
Guest Editor
TIMA Laboratory, CNRS, 38031 Grenoble, France
Interests: hardware security; physical attacks; RTL countermeasures; secure test

Special Issue Information

Dear Colleagues,

The presence of security functions at any level is becoming more and more pervasive in every aspect of society due the increasing number of connected devices and heavy data processing. Moreover, the advances in processing power and computing paradigms also push for research into novel schemes and protocols, which pose new challenges in terms of implementations. The search for new cryptographic schemes, in order to find strong successors to the existing standards, and for novel computing approaches requires continuous effort from the engineering community in order to achieve the best results.

In many domains, the need for adequate performance will require recurring hardware acceleration, at least partially: the presence of cryptographic functions in embedded processors as software or hardware implementations is now established, and the trend shows that all sorts of devices will soon be equipped with security features to guarantee confidentiality and authenticity. On the other hand, the possibilities available to attackers aiming to bypass the security of a system have also increased. Microarchitectural vulnerabilities found in modern CPUs (e.g., Spectre, Meltdown, Spoiler, RowHammer) are very recent, proving that possible breaches may be discovered at any time. “Traditional” implementation attacks (side channel analysis, fault attacks) are still a major concern, which needs continuous efforts from the research community in both directions: attacks and countermeasures, from the lowest to the highest level of abstraction.

This Special Issue seeks novel contributions to improve the current state-of-the-art literature on methodologies, tools, and results on architectures, experimental attacks, and countermeasures for embedded systems in the field of hardware security and trust. Topics of interest include but are not limited to the following:

  • Embedded implementation of cryptographic algorithms;
  • Physical attacks against embedded implementations and related countermeasures;
  • Security of test infrastructures;
  • Hardware Trojans and detection techniques;
  • Hardware security primitives;
  • Secure processors and architectures;
  • Microarchitectural attacks: characterization, exploitation, protections;
  • Post-quantum cryptographic implementations;
  • Lightweight cryptographic implementations;
  • Secure implementation in constrained environments.

Dr. Paolo Maistri
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Information is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • secure hardware
  • physical attacks
  • IC trust

Published Papers (3 papers)

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Research

46 pages, 5660 KiB  
Article
A Quantum-Safe Software-Defined Deterministic Internet of Things (IoT) with Hardware-Enforced Cyber-Security for Critical Infrastructures
by Ted H. Szymanski
Information 2024, 15(4), 173; https://doi.org/10.3390/info15040173 - 22 Mar 2024
Viewed by 795
Abstract
The next-generation “Industrial Internet of Things” (IIoT) will support “Machine-to-Machine” (M2M) communications for smart Cyber-Physical-Systems and Industry 4.0, and require guaranteed cyber-security. This paper explores hardware-enforced cyber-security for critical infrastructures. It examines a quantum-safe “Software-Defined-Deterministic IIoT” (SDD-IIoT), with a new forwarding-plane (sub-layer-3a) for [...] Read more.
The next-generation “Industrial Internet of Things” (IIoT) will support “Machine-to-Machine” (M2M) communications for smart Cyber-Physical-Systems and Industry 4.0, and require guaranteed cyber-security. This paper explores hardware-enforced cyber-security for critical infrastructures. It examines a quantum-safe “Software-Defined-Deterministic IIoT” (SDD-IIoT), with a new forwarding-plane (sub-layer-3a) for deterministic M2M traffic flows. A “Software-Defined Networking” (SDN) control plane controls many “Software-Defined-Deterministic Wide-Area Networks” (SDD-WANs), realized with FPGAs. The SDN control plane provides an “Admission-Control/Access-Control” system for network-bandwidth, using collaborating Artificial Intelligence (AI)-based “Zero Trust Architectures” (ZTAs). Hardware-enforced access-control eliminates all congestion, BufferBloat, and DoS/DDoS attacks, significantly reduces buffer-sizes, and supports ultra-reliable-low-latency communications in the forwarding-plane. The forwarding-plane can: (i) Encrypt/Authenticate M2M flows using quantum-safe ciphers, to withstand attacks by Quantum Computers; (ii) Implement “guaranteed intrusion detection systems” in FPGAs, to detect cyber-attacks embedded within billions of IIoT packets; (iii) Provide guaranteed immunity to external cyber-attacks, and exceptionally strong immunity to internal cyber-attacks; (iv) Save USD 100s of billions annually by exploiting FPGAs; and (v) Enable hybrid Classical-Quantum networks, by integrating a “quantum key distribution” (QKD) network with a classical forwarding plane with exceptionally strong cyber-security, determined by the computational hardness of cracking Symmetric Key Cryptography. Extensive experimental results for an SDD-WAN over the European Union are reported. Full article
(This article belongs to the Special Issue Hardware Security and Trust)
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15 pages, 4624 KiB  
Article
CAPTIVE: Constrained Adversarial Perturbations to Thwart IC Reverse Engineering
by Amir Hosein Afandizadeh Zargari, Marzieh AshrafiAmiri, Minjun Seo, Sai Manoj Pudukotai Dinakarrao, Mohammed E. Fouda and Fadi Kurdahi
Information 2023, 14(12), 656; https://doi.org/10.3390/info14120656 - 11 Dec 2023
Viewed by 1168
Abstract
Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate-level information of an IC. In general, the RE process can be done for [...] Read more.
Reverse engineering (RE) in Integrated Circuits (IC) is a process in which one will attempt to extract the internals of an IC, extract the circuit structure, and determine the gate-level information of an IC. In general, the RE process can be done for validation as well as Intellectual Property (IP) stealing intentions. In addition, RE also facilitates different illicit activities such as the insertion of hardware Trojan, pirating, or counterfeiting a design, or developing an attack. In this work, we propose an approach to introduce cognitive perturbations, with the aid of adversarial machine learning, to the IC layout that could prevent the RE process from succeeding. We first construct a layer-by-layer image dataset of 45 nm predictive technology. With this dataset, we propose a conventional neural network model called RecoG-Net to recognize the logic gates, which is the first step in RE. RecoG-Net is successful in recognizing the gates with more than 99.7% accuracy. Our thwarting approach utilizes the concept of adversarial attack generation algorithms to generate perturbation. Unlike traditional adversarial attacks in machine learning, the perturbation generation needs to be highly constrained to meet the fab rules such as Design Rule Checking (DRC) Layout vs. Schematic (LVS) checks. Hence, we propose CAPTIVE as a constrained perturbation generation satisfying the DRC. The experiments show that the accuracy of reverse engineering using machine learning techniques can decrease from 100% to approximately 30% based on the adversary generator. Full article
(This article belongs to the Special Issue Hardware Security and Trust)
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17 pages, 3708 KiB  
Article
Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation
by Mehdi Sadi, Bashir Mohammad Sabquat Bahar Talukder, Kaniz Mishty and Md Tauhidur Rahman
Information 2023, 14(9), 516; https://doi.org/10.3390/info14090516 - 19 Sep 2023
Viewed by 1398
Abstract
Universal adversarial perturbations are image-agnostic and model-independent noise that, when added to any image, can mislead the trained deep convolutional neural networks into the wrong prediction. Since these universal adversarial perturbations can seriously jeopardize the security and integrity of practical deep learning applications, [...] Read more.
Universal adversarial perturbations are image-agnostic and model-independent noise that, when added to any image, can mislead the trained deep convolutional neural networks into the wrong prediction. Since these universal adversarial perturbations can seriously jeopardize the security and integrity of practical deep learning applications, the existing techniques use additional neural networks to detect the existence of these noises at the input image source. In this paper, we demonstrate an attack strategy that, when activated by rogue means (e.g., malware, trojan), can bypass these existing countermeasures by augmenting the adversarial noise at the AI hardware accelerator stage. We demonstrate the accelerator-level universal adversarial noise attack on several deep learning models using co-simulation of the software kernel of the Conv2D function and the Verilog RTL model of the hardware under the FuseSoC environment. Full article
(This article belongs to the Special Issue Hardware Security and Trust)
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Planned Papers

The below list represents only planned manuscripts. Some of these manuscripts have not been received by the Editorial Office yet. Papers submitted to MDPI journals are subject to peer-review.

Title: A Lightweight Crypto Design for Protecting Constraint Devices in Smart Grid
Authors: Radek Fujdiak; Ina Fujdiak; Jiri Misurec
Affiliation: Brno University of Technology
Abstract: The smart grid network consists of various devices, such as smart meters, that communicate sensitive information. These devices are often resource-constrained and overlooked from a cybersecurity perspective. This paper proposes a hybrid lightweight cryptography solution for securing constraint devices in smart grid networks. The solution focuses on ensuring confidentiality, integrity, authenticity, data freshness, and non-repudiation. The proposed solution combines AES-128 CBC, ECDH, CRC-16, and AES-ECB to create a novel lightweight crypto design. Experimental measurements and optimization processes are included to demonstrate the effectiveness of the proposed solution.

Title: Recent Advances in RowHammer Attacks and Defenses
Authors: Hyung-Min Lee
Affiliation: School of Electrical Engineering, Korea University, Seoul, Korea
Abstract: With the advancement of DRAM technology processes, the susceptibility to RowHammer attacks has heightened. Leading technology companies like Intel and AMD employ various countermeasures, including ECC, TRR, and PARA, to combat these threats. However, defense mechanisms are not infallible, and there exist methods to circumvent them. In this paper, we commence by elucidating the fundamental theory and methodologies behind RowHammer. We delve into the architectural intricacies of DRAM DIMMs, the ramifications of RowHammer attacks on computer systems, and the underlying attack mechanisms. Drawing from this foundational understanding, we explore various documented RowHammer attacks, categorizing them based on attack patterns and advancements in RowHammer's attack capabilities. Specifically, in the section on patterns, we concentrate on single-sided, double-sided, half-double, TRR-Bypassing, and one-location attacks. To shed light on the enhancement of its intrinsic attack potential, we discuss RowHammer techniques that leverage cache allocation technology. Further, the paper delves into the influence of RowHammer on web browsers, discussing the rowhammer.js (a side channel approach) and "smash" for JavaScript-centric RowHammer assaults. Shifting the architectural focus, we also examine RowHammer attacks on the ARM architecture, specifically DRAMMER, diverging from the traditionally targeted x86 architecture. Additionally, we touch upon RAMbleed, a RowHammer variant that jeopardizes data confidentiality. We conclude by underscoring the significance of understanding and countering RowHammer, reflecting on the myriad of defense mechanisms dissected.

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