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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 October 2022) | Viewed by 14966

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Prof. Dr. Paris Kitsos

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Electrical & Computer Engineering Department, University of the Peloponnese, 26334 Patras, Greece
Interests: integrated circuit design for security systems; encryption algorithms and signal processing systems; methods of searching for hardware trojans in integrated circuits; hardware design for embedded systems
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Special Issue Information

Dear Colleagues,

Hardware security is a major area of investigation because it can deliver significant benefits at the device level, such as robust, tamper-resistant storage of keys, integrated cryptographic primitives, secure communication between devices, protection against both virtual and physical attacks, authorization and authentication between the devices, and many others.
So, this Special Issue provides an opportunity to present new results from both the research and industry communities. We invite you to submit high quality papers to this Special Issue on “Circuits and Systems of Security Applications”, with subjects covering all aspects of embedded, HW/SW design and VLSI implementations. The topics include, but are not limited to:

•   Hardware security primitives;
•   Applications of secure hardware;
•   Attacks against hardware implementations and countermeasures;
•   Hardware Trojans – backdoors and detection techniques;
•   IC Trust and anti-Counterfeiting;
•   Reverse engineering and hardware obfuscation;
•   Hardware security primitives: PUFs and TRNGs;
•   Security architectures in Embedded Systems;
•   Protection of Industrial Internet of Things (IIoT);
•   Protection of Internet of Things (IoT);
•   Security architectures for pervasive computing and wireless applications/protocols;
•   Secure System-on-Chip (SoC) designs;
•   Lightweight cryptography and implementations;
•   FPGA and reconfigurable fabric security;
•   Cyber-physical system security.

Prof. Dr. Paris Kitsos
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (7 papers)

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Research

18 pages, 1907 KiB

Open AccessArticle

Distributed Deep Neural-Network-Based Middleware for Cyber-Attacks Detection in Smart IoT Ecosystem: A Novel Framework and Performance Evaluation Approach

by Guru Bhandari, Andreas Lyth, Andrii Shalaginov and Tor-Morten Grønli

Electronics 2023, 12(2), 298; https://doi.org/10.3390/electronics12020298 - 06 Jan 2023

Cited by 10 | Viewed by 3331

Abstract

Cyberattacks always remain the major threats and challenging issues in the modern digital world. With the increase in the number of internet of things (IoT) devices, security challenges in these devices, such as lack of encryption, malware, ransomware, and IoT botnets, leave the devices vulnerable to attackers that can access and manipulate the important data, threaten the system, and demand ransom. The lessons from the earlier experiences of cyberattacks demand the development of the best-practices benchmark of cybersecurity, especially in modern Smart Environments. In this study, we propose an approach with a framework to discover malware attacks by using artificial intelligence (AI) methods to cover diverse and distributed scenarios. The new method facilitates proactively tracking network traffic data to detect malware and attacks in the IoT ecosystem. Moreover, the novel approach makes Smart Environments more secure and aware of possible future threats. The performance and concurrency testing of the deep neural network (DNN) model deployed in IoT devices are computed to validate the possibility of in-production implementation. By deploying the DNN model on two selected IoT gateways, we observed very promising results, with less than 30 kb/s increase in network bandwidth on average, and just a 2% increase in CPU consumption. Similarly, we noticed minimal physical memory and power consumption, with 0.42 GB and 0.2 GB memory usage for NVIDIA Jetson and Raspberry Pi devices, respectively, and an average 13.5% increase in power consumption per device with the deployed model. The ML models were able to demonstrate nearly 93% of detection accuracy and 92% f1-score on both utilized datasets. The result of the models shows that our framework detects malware and attacks in Smart Environments accurately and efficiently. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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24 pages, 888 KiB

Open AccessArticle

True Random Number Generation Capability of a Ring Oscillator PUF for Reconfigurable Devices

by Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez and Piedad Brox

Electronics 2022, 11(23), 4028; https://doi.org/10.3390/electronics11234028 - 05 Dec 2022

Cited by 3 | Viewed by 1879

Abstract

This paper presents the validation of a novel approach for a true-random number generator (TRNG) based on a ring oscillator–physical unclonable function (RO-PUF) for FPGA devices. The proposal takes advantage of the different noise sources that affect the electronic implementation of the RO-PUF to extract the entropy required to guarantee its function as a TRNG, without anything more than minimal changes to the original design. The new RO-PUF/TRNG architecture has been incorporated within a hybrid HW/SW embedded system designed for devices from the Xilinx Zynq-7000 family. The degree of randomness of the generated bit streams was assessed using the NIST 800-22 statistical test suite, while the validation of the RO-PUF proposal as an entropy source was carried out by fulfilling the NIST 800-90b recommendation. The features of the hybrid system were exploited to carry out the evaluation and validation processes proposed by the NIST publications, online and on the same platform. To establish the optimal configuration to generate bit streams with the appropriate entropy level, a statistical study of the degree of randomness was performed for multiple TRNG approaches derived from the different implementation modes and configuration options available on the original RO-PUF design. The results show that the RO-PUF/TRNG design is suitable for secure cryptographic applications, doubling its functionality without compromising the resource–efficiency trade-off already achieved in the design. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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24 pages, 822 KiB

Open AccessArticle

SKG-Lock+: A Provably Secure Logic Locking SchemeCreating Significant Output Corruption

by Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes and Bruno Rouzeyre

Electronics 2022, 11(23), 3906; https://doi.org/10.3390/electronics11233906 - 25 Nov 2022

Cited by 2 | Viewed by 1995

Abstract

The current trend to globalize the supply chain in the Integrated Circuits (ICs) industry has raised several security concerns including, among others, IC overproduction. Over the past years, logic locking has grown into a prominent countermeasure to tackle this threat in particular. Logic locking consists of “locking” an IC with an added primary input, the so-called key, which, unless fed with the correct secret value, renders the ICs unusable. One of the first criteria ensuring the quality of a logic locking technique was the output corruption, i.e., the corruption at the outputs of a locked circuit, for any wrong key value. However, since the introduction of SAT-based attacks, resulting countermeasures have compromised this criterion in favor of a better resilience against such attacks. In this work, we propose SKG-Lock+, a Provably Secure Logic Locking scheme that can thwart SAT-based attacks while maintaining significant output corruption. We perform a comprehensive security analysis of SKG-Lock+ and show its resilience against SAT-based attacks, as well as various other state-of-the-art attacks. Compared with related works, SKG-Lock+ provides higher output corruption and incurs acceptable overhead. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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21 pages, 452 KiB

Open AccessArticle

Equivalent Keys: Side-Channel Countermeasure for Post-Quantum Multivariate Quadratic Signatures

by David Pokorný, Petr Socha and Martin Novotný

Electronics 2022, 11(21), 3607; https://doi.org/10.3390/electronics11213607 - 04 Nov 2022

Viewed by 1043

Abstract

Algorithms based on the hardness of solving multivariate quadratic equations present promising candidates for post-quantum digital signatures. Contemporary threats to implementations of cryptographic algorithms, especially in embedded systems, include side-channel analysis, where attacks such as differential power analysis allow for the extraction of secret keys from the device’s power consumption or its electromagnetic emission. To prevent these attacks, various countermeasures must be implemented. In this paper, we propose a novel side-channel countermeasure for multivariate quadratic digital signatures through the concept of equivalent private keys. We propose a random equivalent key to be generated prior to every signing, thus randomizing the computation and mitigating side-channel attacks. We demonstrate our approach on the Rainbow digital signature, but since an unbalanced oil and vinegar is its special case, our work is applicable to other multivariate quadratic signature schemes as well. We analyze the proposed countermeasure regarding its properties such as the number of different equivalent keys or the amount of required fresh randomness, and we propose an efficient way to implement the countermeasure. We evaluate its performance regarding side-channel leakage and time/memory requirements. Using test vector leakage assessment, we were not able to detect any statistically significant leakage from our protected implementation. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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10 pages, 3424 KiB

Open AccessArticle

Method for Improving the Reliability of SRAM-Based PUF Using Convolution Operation

by Ruihu Cao, Niansong Mei and Qian Lian

Electronics 2022, 11(21), 3493; https://doi.org/10.3390/electronics11213493 - 28 Oct 2022

Cited by 1 | Viewed by 1441

Abstract

This paper introduces a novel and efficient physical unclonable function (PUF) extraction method for SRAM. The proposed one-layer convolution scheme is based on a convolution operation, which significantly enhances the reliability of the PUF. To further reduce the hardware resources, a lightweight solution is presented based on a one-layer convolution scheme at the cost of a higher redundancy coefficient and a larger range for the inter-chip Hamming distance (HD). Both the above schemes only use certain hardware resources in the initial stage and the hardware resources are automatically released after PUF verification. The two schemes were verified using SRAM cells in three stm32f407 chips to output a 256-bit PUF response. The experimental results show that the one-layer convolution scheme required 8 KB SRAM, while the lightweight scheme used only 0.5 KB SRAM. The reliability of the one-layer convolution was found to be 100% when the redundancy coefficient was 0.08 and the inter-chip HD was 50.8073%. The reliability of the lightweight scheme was 100% and of the inter-chip HD was 50.195%. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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29 pages, 10962 KiB

Open AccessArticle

Design and Implementation of Real-Time Image Acquisition Chip Based on Triple-Hybrid Encryption System

by Jiakun Li, Yixuan Luo, Fei Wang and Wei Gao

Electronics 2022, 11(18), 2925; https://doi.org/10.3390/electronics11182925 - 15 Sep 2022

Cited by 3 | Viewed by 1241

Abstract

With the improved hardware storage capabilities and the rapid development of artificial intelligence image recognition technology, information is becoming image-oriented. Increasingly sensitive image data needs to be processed. When facing a large amount of real-time sensitive image data encryption and decryption, ensuring both the speed and the security is an urgent demand. This paper proposes an original triple-hybrid encryption system for a real-time sensitive image acquisition chip. This encryption system optimizes the symmetric encryption algorithm AES, asymmetric encryption algorithm ECC, and chip authentication algorithm PUF in pursuit of security, calculation speed, and to ensure that it is lightweight. The three optimized algorithms are further mixed and reused on the circuit level, to ensure mutual protection while making full use of their advantages. Apart from sensitive image protection at the algorithm level, the image chip itself is also protected by an innovative PUF chip authentication method that prevents it from being tampered with and copied. Triple-hybrid encryption system hardware implementation achieves a frequency of 132.5 MHz under the Virtex-5 FPGA with an area of 2834 Slices; with Virtex-7 FPGA, it reaches a frequency of 137.6 MHz with an area of 2716 Slices. The system is also implemented on SMIC 40 nm ASIC, and the clock frequency reaches 480 MHz and the area is 94,812.4

μ

^{2}

. In terms of computing speed, the peak image encryption speed is 6.15 Gb/s, which meets the real-time image encryption requirement. In terms of hardware resource usage, AES reduced the hardware area by 60.1% compared with the results in other literature, ECC reduced the hardware area by 43.4%, and the PUF hardware area decreased exponentially with the increase in information entropy. The implementation of the three algorithms is reasonable and cost-effective, and the mixture of algorithms does not increase the required capacity of the hardware resource. The triple-hybrid encryption system cooperates with the image acquisition subsystem, storage subsystem, and asynchronous clock subsystem through software control to realize a complete triple-hybrid encryption SoC chip solution, and was successfully taped-out under the SMIC 40 nm process with all constraints passed and a total area of 10.59 mm

^{2}

. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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23 pages, 8091 KiB

Open AccessFeature PaperArticle

GAINESIS: Generative Artificial Intelligence NEtlists SynthesIS

by Konstantinos G. Liakos, Georgios K. Georgakilas, Fotis C. Plessas and Paris Kitsos

Electronics 2022, 11(2), 245; https://doi.org/10.3390/electronics11020245 - 13 Jan 2022

Cited by 7 | Viewed by 2690

Abstract

A significant problem in the field of hardware security consists of hardware trojan (HT) viruses. The insertion of HTs into a circuit can be applied for each phase of the circuit chain of production. HTs degrade the infected circuit, destroy it or leak encrypted data. Nowadays, efforts are being made to address HTs through machine learning (ML) techniques, mainly for the gate-level netlist (GLN) phase, but there are some restrictions. Specifically, the number and variety of normal and infected circuits that exist through the free public libraries, such as Trust-HUB, are based on the few samples of benchmarks that have been created from circuits large in size. Thus, it is difficult, based on these data, to develop robust ML-based models against HTs. In this paper, we propose a new deep learning (DL) tool named Generative Artificial Intelligence Netlists SynthesIS (GAINESIS). GAINESIS is based on the Wasserstein Conditional Generative Adversarial Network (WCGAN) algorithm and area–power analysis features from the GLN phase and synthesizes new normal and infected circuit samples for this phase. Based on our GAINESIS tool, we synthesized new data sets, different in size, and developed and compared seven ML classifiers. The results demonstrate that our new generated data sets significantly enhance the performance of ML classifiers compared with the initial data set of Trust-HUB. Full article

(This article belongs to the Special Issue Circuits and Systems of Security Applications)

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