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Electronics
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Error-Control Coding Algorithms and Architectures for Modern Applications
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Error-Control Coding Algorithms and Architectures for Modern Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 January 2022) | Viewed by 10220

Special Issue Editors

Dr. Francisco Garcia-Herrero

E-Mail Website
Guest Editor
ARIES Research Center, Universidad Nebrija, 28040 Madrid, Spain
Interests: design and implementation of algorithms and hardware architectures for Error Correction Codes (ECC) codes required in modern communication networks, storage systems and quantum processors
Dr. Shahid Mumtaz

grade E-Mail Website
Guest Editor
Quantum Communication Instituto de Telecomunicaces, University Campus of Santiago, P-3810-193 Aveiro, Portugal
Interests: 5G-NR; quantum communication; machine learning; satellite communication
Special Issues, Collections and Topics in MDPI journals
Dr. Carmen G. Almudever

E-Mail Website1 Website2
Guest Editor
Computer Engineering Department, Technical University of Valencia, Camino de Vera s/n, 46022 Valencia, Spain
Interests: quantum computing; quantum computer architecture; compilation and mapping of quantum algorithms; quantum error correction; fault tolerant quantum computing
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

The development of algorithms and architectures for error-control coding (ECC) has been a rapidly growing field for several decades now, allowing the design of reliable data storage systems, data centers, and communication networks. Although great improvements have been achieved by the community with capacity-approaching codes and efficient implementations of gigabit decoders, more challenging requirements and constraints come with the release of new standards, the scaling of manufacturing processes, the appearance of new memory technologies, and the quantum-computing revolution. As an example of the applications that will require more advanced ECC solutions in a near future, we find the evolution of wireless networks toward a sixth generation (6G) that will need both higher data rates and lower power consumption devices, ensuring at the same time high-quality links with error-free transmissions. To achieve that, the design of new codes and decoding algorithms will be necessary, which will require the use of frameworks that combine artificial intelligence solutions with more classic coding paradigms. Additionally, innovative storage systems such as phase change memories cannot use the same solutions employed for previous technologies in the last decade due to the increase in demand for better performance and better capacity and because these new paradigms involve some new and particular reliability concerns. Finally, other well-known faulty systems are quantum computers, which are inherently prone to more errors than classical systems. Even though tremendous work has been done proposing correction techniques and codes over the years, due to its complexity, no real-time implementations have been presented for practical lengths. These are just some examples to show that, although the performance demand in terms of error correction is still very real, the present efforts are not only toward designing algorithms that provide the largest coding gain, but rather toward compatibility to specific applications and also with a focus on hardware constraints such as energy consumption, throughput, and silicon area. 

This Special Issue on “Error-Control Coding Algorithms and Architectures for Modern Applications” aims to include different implementation solutions and design of algorithms and error-correction codes, provided that such solutions suppose a significant scientific contribution in the field.

Dr. Francisco Garcia-Herrero
Dr. Shahid Mumtaz
Dr. Carmen G. Almudever
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Error-correction codes
  • FPGA/ASIC implementations
  • Decoding algorithms
  • Code design
  • Quantum error correction

Published Papers (4 papers)

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Research

23 pages, 11888 KiB  
Article
Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks
by Cheng-Hung Lin, Hsin-Hao Su, Tang-Syun Chen and Cheng-Kai Lu
Electronics 2022, 11(5), 733; https://doi.org/10.3390/electronics11050733 - 26 Feb 2022
Cited by 2 | Viewed by 2525
Abstract
In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different [...] Read more.
In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively. Full article
(This article belongs to the Special Issue Error-Control Coding Algorithms and Architectures for Modern Applications)
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15 pages, 2494 KiB  
Article
A Novel Flip-List-Enabled Belief Propagation Decoder for Polar Codes
by Qasim Jan, Shahid Hussain, Muhammad Furqan, Zhiwen Pan, Nan Liu and Xiaohu You
Electronics 2021, 10(18), 2302; https://doi.org/10.3390/electronics10182302 - 18 Sep 2021
Cited by 4 | Viewed by 2307
Abstract
Due to the design principle of parallel processing, belief propagation (BP) decoding is attractive, and it provides good error-correction performance compared with successive cancellation (SC) decoding. However, its error-correction performance is still inferior to that of successive cancellation list (SCL) decoding. Consequently, this [...] Read more.
Due to the design principle of parallel processing, belief propagation (BP) decoding is attractive, and it provides good error-correction performance compared with successive cancellation (SC) decoding. However, its error-correction performance is still inferior to that of successive cancellation list (SCL) decoding. Consequently, this paper proposes a novel flip-list- (FL)-enabled belief propagation (BP) method to improve the error-correction performance of BP decoding for polar codes with low computational complexity. The proposed technique identifies the vulnerable channel log-likelihood ratio (LLR) that deteriorates the BP decoding result. The FL is utilized to efficiently identify the erroneous channel LLRs and correct them for the next BP decoding attempt. The preprocessed channel LLR through FL improves the error-correction performance with minimal flipping attempts and reduces the computational complexity. The proposed technique was compared with the state-of-the-art BP, i.e., BP bit-flip (BP-BF), generalized BP-flip (GBPF), cyclic redundancy check (CRC)-aided (CA-SCL) decoding, and ordered statistic decoding (OSD), algorithms. Simulation results showed that the FL-BP had an excellent block error rate (BLER) performance gain up to 0.7 dB compared with BP, BP-BF, and GBPF decoder. Besides, the computational complexity was reduced considerably in the high signal-to-noise ratio (SNR) regime compared with the BP-BF and GBPF decoding methods. Full article
(This article belongs to the Special Issue Error-Control Coding Algorithms and Architectures for Modern Applications)
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16 pages, 4253 KiB  
Article
LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems
by Cheng-Hung Lin, Chen-Xuan Wang and Cheng-Kai Lu
Electronics 2021, 10(16), 2010; https://doi.org/10.3390/electronics10162010 - 19 Aug 2021
Cited by 6 | Viewed by 2333
Abstract
This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement [...] Read more.
This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW. Full article
(This article belongs to the Special Issue Error-Control Coding Algorithms and Architectures for Modern Applications)
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10 pages, 590 KiB  
Article
Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial
by Zhe Zhang, Liang Zhou and Zhi Heng Zhou
Electronics 2021, 10(4), 425; https://doi.org/10.3390/electronics10040425 - 09 Feb 2021
Cited by 5 | Viewed by 1785
Abstract
An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. [...] Read more.
An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5. Full article
(This article belongs to the Special Issue Error-Control Coding Algorithms and Architectures for Modern Applications)
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