Memristor Devices: Models, Developments and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Electronic Materials".

Deadline for manuscript submissions: closed (31 July 2023) | Viewed by 1886

Special Issue Editors


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Guest Editor
CNRS, Institut Matériaux Microélectronique Nanosciences de Provence, Aix-Marseille University, 13451 Marseille, France
Interests: non-volatile memories; TCAD simulation; electrical characterization for reliability and security
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
CNRS, Institut Matériaux Microélectronique Nanosciences de Provence, Aix-Marseille University, F-13453 Marseille, France
Interests: non-volatile memories; EEPROM; flash; MRAM; electrical characterization; modelization; reliability; security
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Memristor devices are promising candidates for the next generations of non-volatile (NV) memories compared to traditional embedded NV-Flash and volatile SRAM technologies. Indeed, they generally offer high density, high scalability and high reliability also in addition to low cost and low power consumption. Moreover, memristor devices offer a wide range of possible applications, such as very dense memory arrays, neural networks and in-memory computing. This Special Issue is dedicated to these memristor devices and especially to their modelling, development and applications. The list of possible topics includes, but is not limited to:

  • Emerging memristors, including ReRAM, MRAM, PCRAM, FeRAM and associated selectors, from the demonstration of novel device concepts to fully integrated memory arrays;
  • Memristor architectures and process development from product prototyping to manufacturing-related challenges and solutions (integration schemes, novel circuit design schemes and novel memory architectures that enhance memory performance);
  • Use and reliability of memristive devices for artificial intelligence and design architectures for in-memory and neuromorphic computing (neural networks);
  • Memristor devices physics and theoretical approaches including analytical, numerical and statistical approaches applied to structures with dimensions ranging from atomistic over device dimensions to full-chip dimensions, including physics-based compact modeling;
  • Security and radiation effects on memristor devices (measurements, simulation, modelling, etc.).

Dr. Jérémy Postel-Pellerin
Prof. Dr. Pierre Canet
Guest Editors

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Keywords

  • artificial intelligence
  • in-memory and neuromorphic computing
  • new architectures
  • process development
  • modelling
  • security
  • radiation effects

Published Papers (1 paper)

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Research

13 pages, 4729 KiB  
Article
Experimental Analysis of Oxide-Based RAM Analog Synaptic Behavior
by Hassan Aziza, Jeremy Postel-Pellerin and Mathieu Moreau
Electronics 2023, 12(1), 49; https://doi.org/10.3390/electronics12010049 - 23 Dec 2022
Cited by 1 | Viewed by 1482
Abstract
One of the important features of Resistive RAM (RRAM) is its conductance modulation, which makes it suitable for neuromorphic computing systems. In this paper, the conductance modulation of Oxide-based RAM (OxRAM) devices is evaluated based on experimental data to reveal its inherent analog [...] Read more.
One of the important features of Resistive RAM (RRAM) is its conductance modulation, which makes it suitable for neuromorphic computing systems. In this paper, the conductance modulation of Oxide-based RAM (OxRAM) devices is evaluated based on experimental data to reveal its inherent analog synaptic behavior. A test chip made of a classical 1T-1R elementary memory array is used to demonstrate the conductance modulation. Using an array of cells, as opposed to an isolated cell, allows to catch temporal as well as spatial variabilities. Thus, the multiple resistance levels capability of OxRAMs is assessed in a more realistic context. Two different programming techniques are used to program the OxRAM cells. The first approach leverages on RESET (RST) voltage control. The second approach relies on compliance current control during the SET operation. In both approaches, although multiple resistance levels can be easily obtained, it is demonstrated that a successful implementation of a reliable conductance modulation scheme mainly depends on the ability to precisely control the impact of variability on the different conductance levels obtained after the programming operation. Full article
(This article belongs to the Special Issue Memristor Devices: Models, Developments and Applications)
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