FPGA-Based Deep Neural Network Accelerators Using Emerging Technologies

Dear Colleagues,

Electronics invites manuscript submissions in the area of deep neural network (DNN) acceleration, such as fast convolution algorithms, sparsification, low-bit quantization, approximate computing and other emerging technologies or models, which are applied to implement FPGA-based deep learning accelerators. In recent years, DNNs have been widely used in many rising fields, such as computer-vision, object segmentation and autonomous driving, achieving excellent performance. Due to its excellent power consumption and configurability, FPGA is most commonly used to implement DNN accelerators. However, the huge parameters and computation workloads, as well as the rapid evolution of DNN models, make it difficult to deploy them in scenarios with tight limits on FPGA resources and requirements for high performance. Some emerging technologies have the potential to achieve computation reduction and runtime latency degradation. Many open issues still remain unresolved when those emerging and promising technologies are applied for hardware acceleration, such as how to extend the fast convolution algorithm to different convolution types with reduced hardware resources, how to efficiently eliminate the invalid zero elements in sparse DNNs and how to support different computation parallelism for various low-bit schemes with stable processing element utilization.

To tackle the above issues and challenges, this Special Issue of Electronics will advance innovative solutions and novel advancements in the field of DNN acceleration, sparsification, low-bit quantization, approximate computing, etc. Additionally, this field also looks forward to brand new ideas (e.g., other fast convolution algorithms and novel pruning strategies) and subversive FPGA-based accelerators on other emerging networks (e.g., graph neural networks, spike neural networks) to help solve the aforementioned problems and challenges.

In this Special Issue, original research articles and reviews are welcome. Research areas may include (but not limited to) the following:

• Novel architecture for FPGA-based DNN accelerators;
• Hardware/software co-design for FPGA-based DNN accelerators;
• Resource/bandwidth optimizations for FPGA-based DNN accelerators;
• FPGA-based DNN accelerators using fast convolution algorithms;
• FPGA-based accelerators for sparse DNNs;
• FPGA-based DNN accelerators performing low-bit/mixed-bit quantization;
• FPGA-based DNN accelerators using approximate computing;
• Dynamically reconfigurable DNN accelerators;
• FPGA-based graph convolution neural network acceleration;
• FPGA-based spike neural network acceleration;
• FPGA-based transformer network acceleration;
• FPGA-based acceleration of other atypical convolutions/networks;
• Emerging applications of FPGA-based DNN accelerators.

Dr. Chen Yang
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

• deep learning
• convolution neural network
• fast convolution algorithm
• sparsification
• low-bit quantization
• approximate computing
• reconfigurable computing
• FPGA