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Proceeding Paper

A Highly Efficient Cross-Connected H-Bridge-Style Multilevel Inverter with Lower Power Components †

by
Vijayaraja Loganathan
1,*,
Dhanasekar Ravikumar
1,
Kesav Sanadhan Saikumar
1 and
Rupa Kesavan
2
1
Department of Electrical and Electronics Engineering, Sri Sairam Institute of Technology, Chennai 600044, India
2
Department of Computer Science and Engineering, Sri Venkateswara College of Engineering, Sriperumbudur, Chennai 602117, India
*
Author to whom correspondence should be addressed.
Presented at the 4th International Electronic Conference on Applied Sciences, 27 October–10 November 2023; Available online: https://asec2023.sciforum.net/.
Eng. Proc. 2023, 56(1), 38; https://doi.org/10.3390/ASEC2023-15296
Published: 26 October 2023
(This article belongs to the Proceedings of The 4th International Electronic Conference on Applied Sciences)

Abstract

:
Compared to the classical inverters, the multilevel inverter finds remarkable advantages that can be suitably implemented in green energy power generation. Here, an asymmetric multilevel inverter with fewer components is proposed for renewable energy applications. The proposed inverter is a cross between two H-bridge-style devices. To maximize the output voltage, three different algorithms to fix the amplitude of the DC sources are proposed, and the best among them is chosen for implementation. The recommended inverter can generate 19 levels of output voltage using three DC sources with reduced power components. The nearest-level modulation is used as the control course for the inverter. Here, MATLAB software is used to simulate the proposed inverter, and the performance of the inverter is observed. The proposed inverter is constructed in real time, and the performance of the inverter is studied by testing with fixed and variable reactive loads. A comparative study is made between the simulation model and real-time work results interms of efficiency and harmonics in the load waveforms.

1. Introduction

An electrical inverter transforms DC power into AC power from sources like batteries, fuel cells, or solar cells. Current source inverters (CSI) and voltage source inverters (VSI) are two different types of inverters. A multilevel inverter is a device that uses power electronic devices as switches and produces higher voltage levels compared to traditional inverters, depending on the voltage sources used. These multilevel inverters are used in renewable energy systems with high efficiency, electric vehicles, industrial motor drives to improve the motor’s performance, power factor corrections to reduce reactive power consumption, etc. These inverters have high voltage stress, which causes reliability and durability issues, complex control algorithms, harmonic distortions at low switching frequencies, and a high challenge in balancing capacitor voltage. There are different types of MLI, such as diode clamped MLI, Flying Capacitor MLI, Cascaded MLI, Diode-Clamped MLI, and Capacitor-Clamped MLI. These conventional MLIs use capacitors, diodes, and voltage sources, providing a simple topology. A multilevel inverter is proposed on the basis of a series connection [1,2]. The invented MLI gives output voltages of 11 levels, 15 levels, and 19 levels. These inverters are coupled with renewable energy systems as well as fuel cell applications [3]. The designed MLI produces an output voltage of 17 levels with two asymmetrical DC sources. The module had a simple inherent charging for capacitors without any additional circuit. The negative voltage capability is involved [4]. The proposed D-type MLI produces output voltage at 7 levels. The Nearest Level Modulation (NLM) technique is used to control the inverter. The input voltage can be boosted by synthesizing capacitor voltage [5]. Integrating the solar PV system with the inverter is the main goal of the power quality improvement, and the performance of an asymmetric multilevel inverter with different PWM approaches for harmonic suppression is also examined [6]. Three induction motors are driven by a cascaded multilevel inverter using a hybrid control approach. Lower-voltage DC sources are used to improve the voltage rating and solar photovoltaic system power quality. Switching Frequency Optimum (SFO) and Nearest Level Control (NLC) control approaches are used [7]. The control strategy of the neutral point clamped inverter is limited since only one basic vector may be selected as the optimal output during a control period. An extended control set that accelerates the search for the appropriate vector and enhances control performance. The proposed inverter generates three output voltage levels [8]. This proposed topology collects maximum power from the sources and transmits it to the grid in pure AC form with minimal switching and power loss. In this proposed solution, only two switches are switched on for a single state, greatly reducing switching losses and thus increasing efficiency [9]. The proposed inverter produces 19 levels of output voltage without the H-bridge circuit, which is used for power quality improvement in the grid [10]. The proposed inverter produces 7 levels of output voltage in the symmetric case and 15 levels of output voltage in the asymmetric case with 9 switches; however, the total harmonic distortion is high, so the efficiency is reduced [11]. Considering the above papers, a multilevel inverter is proposed that produces 19 levels of output voltage with 3 DC sources and 12 switches. The inverter is simulated using the MATLAB software and tested for real-time applications. This paper comprises Section 2, which discusses the proposed inverter structure; Section 3 presents the comparative analysis of various trends in multilevel inverters; Section 4 consists of the simulation finding; and Section 5 is the conclusion.

2. Proposed 19-Level Inverter

The proposed asymmetric multilevel inverter structure is shown in Figure 1. The inverter consists of 3asymmetric sources and 12 power electronic switches. The proposed inverter produces 19 levels of output voltage, and the inverter is controlled usingt he Nearest Level Modulation (NLM) technique. With the unequal DC magnitude, i.e., V1 = VDC,V2 = 3VDC, and V3 = 5VDC, the configured inverter produces 9 +ve voltage levels, 9 −ve voltage levels, and zero voltage levels. The switching combinations of the proposed inverter are shown in Figure 2, Figure 3, and the switching pattern is provided in Table 1.

3. Comparative Analysis

In this section, several kinds of multilevel inverters are compared on the basis of output voltage produced, the number of switches used, voltage sources used, IGBT devices used, total standing voltage (TSV), and the THD of various configurations, as given in Table 2. The MLI circuit proposed in [3,6] produces eleven levels of output voltage with different switch counts. In [11], the proposed topologies produce thirteen levels of output voltage, whereas the THD is reduced. For the 17 levels of output voltage, 13 switches and 10 switches are used in [5]. The configured inverter produces a total harmonic distortion of 12.17% with seven levels of output voltage [7]. Only one DC voltage source is needed in order to operate at levels 3 and 5 in [7,11].

4. Simulation and Experimentation

The MATLAB/SIMULINK software is used to model the designed multilevel inverter. The asymmetrical DC voltage magnitudes are V1 = 20 VDC, V2 = 60 VDC, and V3 = 100 VDC. The required voltage is attained with the operation of selected switches. The load parameters are R = 90 Ω and L = 30 mH. The nineteen-level inverter is controlled using the Nearest Level Modulation (NLM) technique, which reduces THD. The nearest edge control is selected at the nearest voltage level and fed to logic gates to produce the appropriate output, which is fed to IGBT switches. The load waveforms and harmonic presences are depicted in Figure 4, Figure 5 and Figure 6.
The prototype of the proposed inverter is shown in Figure 7. The inverter receives pulses from the edge control mechanism. The program is flashed to the controller using the FPGA controller. The IGBT devices are used as switches. The four step-down transformers are used to step down the grid voltage and are fed to the driver circuits. The driver circuits are used to drive the 12 IGBT switches. The prototype is validated with variable and fixed resistive impedance loads and parameters, which are provided in Table 3, and the load waveform is shown in Figure 8.

5. Conclusions

This paper presents the asymmetric multilevel inverter with a reduced number of DC sources and switch counts. The proposed inverter produces 19 levels of output voltage and is controlled using the Nearest Level Modulation technique. The inverter voltage sources are set as V1 = VDC, V2 = 3VDC, and V3 = 5 VDC. The inverter is simulated using MATLAB software that produces a lower THD = 4.26% which is minimum compared to standard IEEE formats. This is also tested in real time for fixed R and RL loads. Because of the variable DC supply, the configured inverter is more suitable for renewable energy systems.

Author Contributions

Conceptualization, V.L. and D.R.; methodology, K.S.S.; software, K.S.S.; validation, V.L., K.S.S. and R.K.; investigation, R.K.; writing—original draft preparation, V.L. and K.S.S.; writing—review and editing and supervision, V.L. and K.S.S. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are available in this manuscript.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Vijayaraja, L.; Dhanasekar, R.; Ganesh Kumar, S. An Inspection on Multilevel Inverters Based on Sustainable Applications. In Power Converters, Drives and Controls for Sustainable Operations; Ganesh Kumar, S., Abarca, M.R., Patnaik, S.K., Eds.; Wiley: Hoboken, NJ, USA, 2023. [Google Scholar]
  2. Raman, G.; Imthiyas, A.; Raja, M.D.; Vijayaraja, L.; Kumar, S.G. Design of 31-level Asymmetric Inverter with Optimal Number of Switches. In Proceedings of the 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS), Tamilnadu, India, 11–13 April 2019; pp. 1–3. [Google Scholar]
  3. Thakre, K.; Mohanty, K.B.; Kommukuri, V.S.; Chatterjee, A.; Nigam, P.; Gupta, S.K. Modified cascaded multilevel inverter for renewable energy systems with less number of unidirectional switches. Energy Rep. 2022, 8, 5296–5304. [Google Scholar] [CrossRef]
  4. Samadaei, E.; Kaviani, M.; Iranian, M.; Pouresmaeil, E. The P-Type Module with Virtual DC Links to Increase Levels in Multilevel Inverters. Electronics 2019, 8, 1460. [Google Scholar] [CrossRef]
  5. Azimi, E.; Tavasoli, A.; Hafezi, H.; Nateghi, A. A Dumbbell Type (D-Type) multilevel inverter based on switched capacitor concept. Int. J. Electron. 2022, 109, 152–168. [Google Scholar] [CrossRef]
  6. Vivek, P.; Muthuselvan, N.B. Investigation on Photovoltaic System based Asymmetrical Multilevel Inverter for Harmonic Mitigation. In Proceedings of the International Conference on Electrical Energy Systems (ICEES), Chennai, India, 11–13 February 2021; pp. 334–339. [Google Scholar]
  7. Mahesh, P.; Venkatesh, C.; Rajagopal, V. NLC and SFO Control Technique Based Multilevel Inverter fed 3-φ Induction Motor Drive. In Proceedings of the International Conference on Sustainable Energy and Future Electric Transportation (SEFET), Hyderabad, India, 21–23 January 2021; pp. 1–7. [Google Scholar]
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  10. Devalraju, P.; Dhanamjayulu, C. A Novel 19-level Asymmetrical Multilevel Inverter for Dynamic Voltage Restorer Applications. In Proceedings of the Power and Advanced Computing Technologies (i-PACT), Kuala Lumpur, Malaysia, 27–29 November 2021; pp. 1–7. [Google Scholar]
  11. Thiyagarajan, V.A. New Symmetric and Asymmetric Multilevel Inverter Circuit with Reduced Number of Components. Mater. Proc. 2022, 10, 5. [Google Scholar]
Figure 1. Circuit diagram of the proposed MLI.
Figure 1. Circuit diagram of the proposed MLI.
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Figure 2. −1 V.
Figure 2. −1 V.
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Figure 3. +1 V.
Figure 3. +1 V.
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Figure 4. R load waveform.
Figure 4. R load waveform.
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Figure 5. RL load waveform.
Figure 5. RL load waveform.
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Figure 6. THD analysis.
Figure 6. THD analysis.
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Figure 7. Hardware model of 19-level MLI.
Figure 7. Hardware model of 19-level MLI.
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Figure 8. Voltage waveform.
Figure 8. Voltage waveform.
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Table 1. Switching pattern of proposed MLI.
Table 1. Switching pattern of proposed MLI.
VDCS1S2S3S4S5S6S7S8S9S10S11S12
0 V001100111100
1 V100100111100
9 V100111001100
0 V001100111100
−1 V100100110011
−9 V100111000011
Table 2. Comparison between various configured MLIs.
Table 2. Comparison between various configured MLIs.
Ref No.NLNSWNDSXTHDN(D+C)
311854.562D
5171323.1218D + 2C
6111253.3512D
779112.172C
11131114.93D + 3C
Proposed191234.36-
Table 3. Performance parameters—MLI.
Table 3. Performance parameters—MLI.
LoadVoIoPo%effTHD
R180236095.164.30
RL180236094.344.26
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MDPI and ACS Style

Loganathan, V.; Ravikumar, D.; Saikumar, K.S.; Kesavan, R. A Highly Efficient Cross-Connected H-Bridge-Style Multilevel Inverter with Lower Power Components. Eng. Proc. 2023, 56, 38. https://doi.org/10.3390/ASEC2023-15296

AMA Style

Loganathan V, Ravikumar D, Saikumar KS, Kesavan R. A Highly Efficient Cross-Connected H-Bridge-Style Multilevel Inverter with Lower Power Components. Engineering Proceedings. 2023; 56(1):38. https://doi.org/10.3390/ASEC2023-15296

Chicago/Turabian Style

Loganathan, Vijayaraja, Dhanasekar Ravikumar, Kesav Sanadhan Saikumar, and Rupa Kesavan. 2023. "A Highly Efficient Cross-Connected H-Bridge-Style Multilevel Inverter with Lower Power Components" Engineering Proceedings 56, no. 1: 38. https://doi.org/10.3390/ASEC2023-15296

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