VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector
Round 1
Reviewer 1 Report
Questions to the author:
1. Introduction: This part is too short, and I am unable understand the contribution of this manuscript while reading this part.
2. Section 3: I felt that this part is too long to explain the device physics, please explain the need of such in depth device physics illustration.
3. Figure 8: It is not clear whether current is increasing/decreasing with respect to temperature. Please explain it with the help of device physics.
4. The reason of CMP is not clear. Is this for making rough poly-Si layer to smooth? if so, how it imparts on device performance? Please explain with results.
5. Minor issues:
a. Abstract: Define VESTIC when you introduce for the first time. Also, this part did not contain any outcome.
b. Figure 2: update the figure, it has missing contents.
c. Page 4/19: line number 8, and also other equations (particularly eq. 2) did you develop these equations? if not, add citations.
d. Figure 7 and other figures: please add/indicate arrows to the arises more clearly.
e. TCAD: Mention which simulator package and which models were used? did you consider any density of states defect model here?
Author Response
Introduction: This part is too short, and I am unable understand the contribution of this manuscript while reading this part.
The introduction has been extended. The main contribution of the paper has been pointed out.
2. Section 3: I felt that this part is too long to explain the device physics, please explain the need of such in depth device physics illustration.
The purpose of Section 3 is to stress and explain all details of the device operation that differ from operation of traditional bipolar transistors.
3. Figure 8: It is not clear whether current is increasing/decreasing with respect to temperature. Please explain it with the help of device physics.
Figure 8 (Figure 10 in the revised version) does not illustrate any temperature dependences. All curves represent currents of individual transistors measured on the third prototype wafer. Charakteristics of 8 p-n-p (Figure 8 a, now 10 a) and 8 n-p-n (Figure 8 b, now 10 b) transistors were measured at standard room temperature 300 K. This information has been added in the caption to this figure.
4. The reason of CMP is not clear. Is this for making rough poly-Si layer to smooth? if so, how it imparts on device performance? Please explain with results.
Additional explanations and a new Figure 6 have been added. Figure 6 shows the cross section of the VES-BJT after deposition of polysilicon.
Minor issues:
a. Abstract: Define VESTIC when you introduce for the first time. Also, this part did not contain any outcome.
The abstract has been extended, VESTIC acronym has been expanded and the outcome pointed out.
b. Figure 2: update the figure, it has missing contents.
Figure 2 is complete and the caption explains its content.
c. Page 4/19: line number 8, and also other equations (particularly eq. 2) did you develop these equations? if not, add citations.
The equations are developed by authors themselves, Citations ( [18], [20] and [22]) were provided.
d. Figure 7 and other figures: please add/indicate arrows to the arises more clearly.
Almost all figures have been redrawn to improve their quality and readability.
e. TCAD: Mention which simulator package and which models were used? did you consider any density of states defect model here?
The simulations were held using Sentaurus TCAD software package in version 2016.1. Model of the device was constructed by Author with the use of software of the Sentaurus package.This information has been added in Section 3. No special density of states defect model was used.
Reviewer 2 Report
This manuscript by Mierzwinski et al. described the fabrication of bipolar junction transistor using VESTIC technology. They also demonstration it is possible to make simple inverter from the BJT. This manuscript is generally well-written and the results sound. Recommend to publish after addressing the following issues.
1. Please provide the full name of VESTIC technology.
2. Please clean up figure 1b and figure 3, some of the notation are overlapped.
3. Please label the junction between the gate and channel in Figure 1a.
4. What does line 88 mean? "Error! Reference source not found"
Author Response
1. Please provide the full name of VESTIC technology.
Added in the Abstract and the Introduction.
2. Please clean up figure 1b and figure 3, some of the notation are overlapped.
Corrected by pasting images instead of vector graphics.
3. Please label the junction between the gate and channel in Figure 1a.
Figure 1 (a) contains the field effect (a.k.a VESFET) transistor. The arrow shows the thin oxide layer between the gates and the channel (slit) area.
4. What does line 88 mean? "Error! Reference source not found"
No reference is needed here, corrected.
Reviewer 3 Report
In this authors summarizes the results of investigations of bipolar transistors made in VESTIC technology. But some major changes are recommended for further improvement.
1) Authors claim the fabrication of a prototype of BJT without supporting SEM or other characterization, which is not acceptable. Either remove this claim or add SEM or other characterization.
2) It is very difficult to develop a clear picture of the BJT device with dimensions.
3) It is better in diagram 2, some dimensions should be introduced.
4) all simulation depends on the set of equations 1, but no reference is provided.
5) If authors add the distribution of electrons and holes through an emitter, base, or collector. It will help to under the fundamentals of BJT working.
Author Response
1. Authors claim the fabrication of a prototype of BJT without supporting SEM or other characterization, which is not acceptable. Either remove this claim or add SEM or other characterization.
SEM photos added as Figure 7.
2. It is very difficult to develop a clear picture of the BJT device with dimensions.
It is mentioned in the text that the radius r of the fabricated devices has a value of about 450 nm, and the wb0 is about 250 nm.
3. It is better in diagram 2, some dimensions should be introduced.
Figure 2 is provided to show the cross-section in VES-BJT, typical dimensions of fabricated devices are mentioned in the text.
4. all simulation depends on the set of equations 1, but no reference is provided.
The set of equations 1 is the analytical description of the geometry of the base region. It follows from the Figure 3. Similar description was presented in a cited paper [18] – eq. no. 4.
5. If authors add the distribution of electrons and holes through an emitter, base, or collector. It will help to under the fundamentals of BJT working.
Figure 4 presents two-dimensional distribution of excess carriers in the base region.
Reviewer 4 Report
The manuscript presents an analysis both from experiments and simulations concerning a technology for lateral bipolar transistors. The topic can be of interest, but some major points need to be addressed.
1) What is the scope of fabricating an inverter using bipolar? The current consumption would be way higher than in CMOS. Fig.10b should report the current consumption of the inverter.
2) Why emitter and collector should be equal? Bipolars are designed with doping levels in the collector way lower than in the emitter.
3) Very limited information is given about the structure, for example what are the doping levels in the silicon and poly?
4) What parameters have been adjusted to reproduce the experimental currents by TCAD? Mobility? Lifetimes? How is tunneling across the 0.25nm SiO2 layer modeled? Some numbers are reported in lines 389-391, but it is not clear where are they from and how they compare with other works.
Other (not so) minor points:
Line 9: extend the acronym VESTIC
Introduction: prior art on lateral BJT should include papers from University of Zagreb, for example “M. Koričić, J. Žilak and T. Suligoj, "Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost," in IEEE Electron Device Letters, vol. 36, no. 2, pp. 90-92, Feb. 2015, doi: 10.1109/LED.2014.2385107 “
Fig.1: I suspect the arrow pointing to the circle “G1” should instead point to the orange line between the poly (green) and silicon (pink) regions, that should be SiO2. Am I correct? Also, please adjust the fonts in the top right panel: all labels are overlapping and impossible to read.
Fig.3: the lable “Base Contact” is cut after “Cont”
Line 88: there is an undefined reference
Lines 111-120 repeat concepts already stated in lines 94-100: please rearrange and keep just one of the two paragraphs.
Eq3: please report the expression of the weighting function. Also, why integrating only up to “r”? Should one integrate up to sqrt(2)r?
Line 129: what do it mean that wbef is close to unity? It is a length, so unity would mean 1meter, 1cm?
Eqs.6, 7: n_n0 should be the concentration at the beginning of the base, i.e. in y=-Wb/2, not in y=0. At least this is the theory in any book about BJTs. Also, the equation is valid iv Vce>>kT/q
Line 159: Fig.6 is referenced before Fig.5, so their order should be reversed.
Caption of Fig.5: please explicitly state the methodology (eq. Eq,xx+Eq.yy) used to determine the two curves
All figures lack a legend. It is quite hard to check the caption to see what solid, dashed, dotted lines represent.
Fig.6: what are the base current levels associated to the different curves? The legend should display the maximum, minimum values and the step.
Figs.7, 8, 11 and 14: what is the value of Vce?
Fig.9 requires some additional explanation: what is the difference between IN and IN2? Is UZ the output? A schematic with the same labels as the layout is needed.
Fig.10a: what is Vbe? Is the Vce the one of the npn or pnp ? In the latter case should be a Vec. How can the two devices be measured separately?
Lines 279, 281: not “transient” but “transfer”
Figs. 12, 13: a legend is needed to identify the different curves
Line 437: I cannot get the meaning. Why should one sum the components of a vector? Also, it says “vectors of the gradient” so, more than one? The gradient is a vector, not more than one. Should one sum different vectors rather than components? What vectors? Why? Please rewrite the sentence.
Line 447: “Device Model IN SPICE”
Author Response
1. What is the scope of fabricating an inverter using bipolar? The current consumption would be way higher than in CMOS. Fig.10b should report the current consumption of the inverter.
It was shown in a recent paper [Ref. 27] how quasi-CMOS bipolar inverters and bipolar gates can become thermally stable. It is shown that their current consumption can be of the same order as CMOS gates or even lower. The current flow in quasi-CMOS bipolar inverters is different than in CMOS inverters. At “0” at the input the current flows from the source of the supply voltage to the ground, at “1” at the input the current flows from the input (i.e. input signal source) to the ground. Since this is discussed in detail in [27], it is not repeated in this paper. Figure 12 (former Fig. 10) shows the currents measured in the inverter.
To make useful bipolar quasi-CMOS inverters and gates one needs to have complementary pairs of NPN and PNP bipolar devices, i.e. devices with the same structures and similar electrical characteristics. It is demonstrated in the paper that in the VESTIC technology such complementary pairs can be made, and bipolar inverter has been designed and measured in order to confirm this claim. Additional comment was added in Section 6.
2. Why emitter and collector should be equal? Bipolars are designed with doping levels in the collector way lower than in the emitter.
In the VES-BJT manufacturing process emitters and collectors are made in the same polysilicon deposition and doping process (see [Ref. 12]), and also their geometry is the same. This is why they are electrically identical. This is an advantage, not a shortcoming. A symmetrical bipolar transistor (i.e with identical emitter and collector) has very low saturation voltage. Moreover, highly doped collector has very low series resistance. A note on these features has been added in Section 6.
3. Very limited information is given about the structure, for example what are the doping levels in the silicon and poly?
Data added in Section 4.
4. What parameters have been adjusted to reproduce the experimental currents by TCAD? Mobility? Lifetimes? How is tunneling across the 0.25nm SiO2 layer modeled? Some numbers are reported in lines 389-391, but it is not clear where are they from and how they compare with other works.
Although the TCAD simulations covered current tunneling, such as conduction band to conduction band (electron tunneling), the tunneling to the valence band from the valence band ( ‘hole tunneling’) and the band-to-band tunneling, there was no tunnel current observed. The discontinuity in oxide layer, mentioned in the paper, was the main reason limiting the current of the modeled structure. The mobility, lifetime etc. had default values in the Sentaurus simulator for the doping levels in the device areas.
The numbers in lines 389-391 are given only to estimate the length of the diffusion path in order to check if the condition of “short base” is met. They are fairly typical at standard conditions (T=300K). The exact values are not very important because the condition of “short base” is met with a large margin.
Line 9: extend the acronym VESTIC
Added.
Introduction: prior art on lateral BJT should include papers from University of Zagreb, for example “M. Koričić, J. Žilak and T. Suligoj, "Double-Emitter Reduced-Surface-Field Horizontal Current Bipolar Transistor With 36 V Breakdown Integrated in BiCMOS at Zero Cost," in IEEE Electron Device Letters, vol. 36, no. 2, pp. 90-92, Feb. 2015, doi: 10.1109/LED.2014.2385107 “
Although this paper describes a bipolar structure that is completely different than VES-BJT, reference has been added for completeness of the overview of other works.
Fig.1: I suspect the arrow pointing to the circle “G1” should instead point to the orange line between the poly (green) and silicon (pink) regions, that should be SiO2. Am I correct? Also, please adjust the fonts in the top right panel: all labels are overlapping and impossible to read.
Figure corrected.
Fig.3: the lable “Base Contact” is cut after “Cont”
Corrected.
Line 88: there is an undefined reference
Corrected – no reference needed here.
Lines 111-120 repeat concepts already stated in lines 94-100: please rearrange and keep just one of the two paragraphs.
Corrected – repetition was deleted, and text was slightly rearranged.
Eq3: please report the expression of the weighting function. Also, why integrating only up to “r”? Should one integrate up to sqrt(2)r?
The limit was corrected, and comment on the weighting function added.
Line 129: what do it mean that wbef is close to unity? It is a length, so unity would mean 1meter, 1cm?
Corrected, the sentence was erroneously shortened too much.
Eqs.6, 7: n_n0 should be the concentration at the beginning of the base, i.e. in y=-Wb/2, not in y=0. At least this is the theory in any book about BJTs. Also, the equation is valid iv Vce>>kT/q
The equations 6 and 7 are correct. When y is equal to 0, the value of n is n= n_n0/2, not n_n0. The difference comes from different point of reference. As depicted in Fig. 3 the y=0 is for the middle of the base region, typically it is the beginning of the base region. Of course this is rough approximation, and with the change of depletion region width the equation 6 will not be as simple as the presented one.
Line 159: Fig.6 is referenced before Fig.5, so their order should be reversed.
Previous Figure 6 was merged with Figure 5, but the wrong reference remained, the reference was corrected.
Caption of Fig.5: please explicitly state the methodology (eq. Eq,xx+Eq.yy) used to determine the two curves
This is described in the Appendix A. The Eq. A7 was normalized by the factor max() that is by the value of for x=0 , accordingly the results of simulation – the diffusion current density, was normalized to its maximum value.
All figures lack a legend. It is quite hard to check the caption to see what solid, dashed, dotted lines represent.
Legends added.
Fig.9 requires some additional explanation: what is the difference between IN and IN2? Is UZ the output? A schematic with the same labels as the layout is needed.
Schematic and explanation of labels added.
Fig.10a: what is Vbe? Is the Vce the one of the npn or pnp ? In the latter case should be a Vec. How can the two devices be measured separately?
The Fig. 10 has been replaced by a new Fig. 12. Instead of characteristics of individual transistors (Fig. 10a) now Fig. 12 shows the transfer characteristics and current of the inverter. Discussion in the text has been added. This helps to answer your first question (about current consumption).
Lines 279, 281: not “transient” but “transfer”
Corrected.
Line 437: I cannot get the meaning. Why should one sum the components of a vector? Also, it says “vectors of the gradient” so, more than one? The gradient is a vector, not more than one. Should one sum different vectors rather than components? What vectors? Why? Please rewrite the sentence.
The text was extended and rewritten.
Line 447: “Device Model IN SPICE”
Changed to “SPICE Device Model”.
Round 2
Reviewer 1 Report
No further comment.
Author Response
Thank you very much for reviewing the paper. I understand that you do not expect any further changes or corrections.
Reviewer 3 Report
Since the authors have adopted all of my recommendations, I am confident in recommending that the manuscript be considered for publication.
Author Response
Thank you very much for reviewing the paper.
Reviewer 4 Report
Most of my previous comments have been addressed. Some minor suggestion:
1) Models and model parameters used in TCAD are not reported. Are them related to the diffusivities and lifetimes reported in line 421
2) Vce is duplicated below the x-axis of Fig.8
3) values of Vce in Figs.9, 10, 13 etc?
4) Fig.12: please report the supply voltage
5) Fig.13: label of the x-axis “Vbe [V}” should be “Vbe [V]”
6) Line 115: which form of the weighting function has been used in the paper? Please report it
7) Line 296: “from the input to the source of the input signal”? I don’t get it. Same for the text beginning at line 304. Probably “source” should read “supply”? “input signal” should read “input port”?
Author Response
- In our TCAD simulations the doping concentrations were the ones reported in Section 4 of the paper, the other parameters (mobilities, lifetimes etc.) had default values in the Sentaurus package for the doping concentrations in the respective regions. This information has been added in the text.
- Corrected.
- Added.
- Added.
- Corrected.
- Explanation added.
- A drawing has been added showing the current paths in the inverter.
Thank you very much for your reviews, they helped a lot to improve the paper.
