VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector

Abstract

This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology.

1. Introduction

A VESTIC-based bipolar transistor (VES-BJT) is a lateral device where current between the emitter and the collector flows in a plane parallel to the surface of the substrate. In a CMOS process, lateral bipolar devices are usually regarded as parasitic devices. Lateral bipolar transistors can also be fabricated in some bipolar or BiCMOS integrated circuits, e.g., a p-n-p bipolar transistor in a BiCMOS process is usually fabricated as a lateral transistor. Lateral transistors were investigated in the late 1960s [1,2,3,4,5,6]. Lateral bipolar transistors on SOI substrate [7,8,9] have also been reported. One more idea of a lateral bipolar transistor has been presented in [10]. However, structures of VES-BJT are very different from other lateral bipolar transistors. The idea of VES-BJT was proposed by W. Maly in his patent application and subsequent publications [11,12,13,14].

VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology has been proposed as an alternative to traditional bulk CMOS technology. The field effect devices using this technology have already been investigated in theory and experiment [13,14,15,16]. These include a field effect VES-FET device and its junction counterpart, the VES-JFET [17].

The VES-BJT transistor was presented previously in [18,19,20,21]. It is demonstrated, here, that VES_BJT can be fully compatible with the production process of the VES-FET transistor [13], and it may be incorporated in the same integrated circuit; however, there are trade-offs related to the doping levels used. This demonstration, together with the theoretical and experimental results reported, is the main contribution of this paper. The ability to fabricate many different kinds of active devices with minimal changes in the cell structure and manufacturing process is the unique feature of the VESTIC technology. Section 2 of the paper shows the structure of VES-BJT and indicates the most important differences between VES-BJT and other lateral bipolar transistors. Theoretical analysis of the operation of VES-BJT is presented in Section 3. This section is focused on differences between VES-BJT and traditional bipolar transistors—in paticular, on specific non-planar shape of the emitter and collector junctions. Section 4 describes the fabrication process of VES-BJT prototypes. Results of measurements of the prototype devices are shown in Section 5, and Section 6 shows simple two-transistor circuits. In Section 7, measurement results are discussed in the context of numerical TCAD-based device simulations. Section 8 concludes the paper.

2. VESTIC Bipolar Transistor Structure

The VESTIC-based integrated circuits have the form of a regular array of identical elementary cells [11,13]. In such a cell, several different semiconductor devices can be manufactured. An insulated gate field effect transistor named VESFET has insulating layers of the gate oxide, while in a field-effect junction transistor or bipolar transistor, the gate oxide is absent. Figure 1 shows a single cell, a comparison, and the labelling of the different areas in the two types of devices in a plan view and 3D view.

The device is fabricated on a SOI substrate in the top layer of silicon. Due to the absence of the gate insulating layer, the structure of the VES-BJT is simpler than that of the VESFET (Figure 1 and Figure 2). Without the gate oxide, the VESFET gate regions become the emitter and collector regions of VES-BJT, and the slit between them serves as the base region. Each region is uniformly doped, and the emitter and collector regions have the same doping level. The junctions are not plane-parallel, but they are quarter-cylindrical with characteristic radius r. The base region has a minimum width of w_b0 in the center, increasing towards the two base contacts. Doped polysilicon is used for the emitter and collector regions. (Figure 2).

3. Theoretical Analysis

The specific structure of the VES-BJT device, which is very different from typical bipolar transistors, raised a question of how to describe the operation of such a device. A theoretical analysis was followed by numerical (TCAD) simulations. These simulations were carried out using the Sentaurus TCAD software package in version 2016.12. A model of the device was constructed by the authors with the use of the software of the Sentaurus package. The doping concentrations reported in Section 4 were used in all the the TCAD simulations. Other parameters (such as mobilities, lifetimes, etc.) had default values assumed, in the Sentaurus package, for the doping concentrations in the respective regions.

Taking into account the geometry of the device, a formula for the base width, as a function of x, can be expressed as follows (Figure 3, see also [18]):

$$W_b\left(x\right)=\{\begin{array}{cc}{w}_{b0}+2r-2r\sqrt{2}-2x,& x\in \left(-L;-\frac{r\sqrt{2}}{2}\right)\\ w_{b0}+2r-2\sqrt{r^2-x^2},& x\in \langle -\frac{r\sqrt{2}}{2}; \frac{r\sqrt{2}}{2}\rangle \\ w_{b0}+2r-2r\sqrt{2}+2x,& x\in \left(\frac{r\sqrt{2}}{2};L\right)\end{array},$$

(1)

where r is the characteristic radius, $w_{b0}$ is the minimum base width (minimum distance between metallurgical junctions), and L is half the length of the junction (dimension of the junction in the X-axis direction). The width of the base $W_b\left(x\right)$ reaches its minimum, equal to $w_{b0}$, for x = 0, wherein the function is symmetric with respect to the line x = 0.

Bipolar transistors with plane-parallel junctions may suffer for the emitter current crowding [22] phenomenon. The emitter-based bias voltage is the highest in the vicinity of the base contacts, and it decreases with the distance from these contacts, due to voltage drop resulting from base current flow across the base spreading resistance. In the case of VES-BJT, our estimations (using the same approach as in [22]) have shown that the voltage drop between the base contacts and the central part of the base is negligible. As a result, current crowding is not a problem in VES-BJT, and it is not accounted for in our theoretical considerations and device modeling.

To be able to use as much as possible, the existing, well-known models of bipolar transistors, such as the Gummel–Poon model and the concept of effective base width, have been introduced. The effective base width is the base width of an electrically equivalent bipolar transistor with a plane-parellel emitter and collector junctions. The effective base width is calculated as

$$w_{bef}=k^{-1},$$

(2)

where the integral k is the product of the weighted average function of the reciprocal of base width $1/\mathrm{W}\left(x\right)$, where $\mathsf{\phi }\left(x\right)$ is the weighting function and can be written as

$$k=\frac{1}{S}\underset{0}{\overset{L}{{\displaystyle \int }}}\frac{\phi \left(x\right)}{W_b\left(x\right)}dx,$$

(3)

where $S={{\displaystyle \int }}_0^L\mathsf{\phi }\left(x\right)dx$ [18,20]. The weighting function φ(x) may represent, for example, uneven distribution of the emitter current density (emitter current crowding). In this work, it was assumed that the weighting function φ(x) = 1. Furthermore, the effective base width may include the distances of depletion layers entering the base region.

$$w_{bef}=\frac{w_{bt}-d_{EB}-d_{CB}}{k^{\prime }},$$

(4)

where $d_{EB}$ and $d_{CB}$ are penetration depths of the depletion layer of the emitter–base junction and the base–collector junction, respectively, $w_{bt}=w_{b0}$ is the metallurgical minimum base width, and $k^{\prime }=k{w}_{b0}$ is the normalized k integral with respect to $w_{b0}$. This approach was also adapted for small signal analysis of VES-BJT [18].

Using the effective base width, the collector current can be determined, from the known relationship, for the current of minority carriers injected into a uniformly doped base region of a planar transistor:

$$I_C=q{D}_{n}2hr\frac{n_{ieB}^2}{N_B{w}_{bef}}\left[\exp \left(\frac{q{U}_{BE}}{kT}\right)-1\right]$$

(5)

where N_B is doping concentration, $w_{bef}$ is the effective base width, and the emitter junction area is 2 hr [20]. $D_n$ is the diffusivity of the minority carriers, and $n_{ieB}$ is the effective intrinsic concentration in the base.

In the case of prototype transistors, in which the dimensions of the characteristic radius r and the metallurgical base width $w_{b0}$ are comparable, the integral k’ in the relation for the effective base width $w_{bef}$ has a value close to unity and does not significantly affect the calculations performed. In the general case, the effective base width $w_{bef}$ may be treated as a fitting parameter.

Analysis supported by TCAD numeric simulations of the structure of the VES-BJT transistor leads to some interesting observations. The shape of the junctions causes the excess charge carriers in the base to be distributed in such a way that most of the diffusion current occurs in the central region of the base. It may be called “current crowding induced by geometry of the device”. This is in contrast to the planar vertical bipolar transistor structures where, as mentioned above, most of the emitter diffusion current may flow closer to the base contacts.

Similarly to the one-dimensional transistor model where, for a short base, the excess carrier distribution in the base is approximated by a linear function of the distance between edges of the emitter and collector depletion layers, the carrier distribution in the base of the VES-BJT transistor can be defined as

$$n\left(x,y\right)=\frac{n_{n0}}{2}\left(1-\frac{2y}{W_b\left(x\right)}\right),$$

(6)

where $W_b\left(x\right)$ is the function describing the base width (1), and $n_{n0}$ may be defined as

$$n_{n0}=\frac{n_{iB}^2}{N_B}\left(e^{q{V}_{BE}/kT}-1\right)$$

(7)

where $N_B$ is the base doping concentration, and $n_{iB}^2$ is the intrinsic carrier concentration of the base material. $V_{BE}$ is the forward bias of base–emitter junction. Figure 4a shows a plot of the distribution defined between the edge of the base–emitter junction and the edge of the base–collector junction, the carrier concentration varies linearly in a function of a distance between edges for a fixed x. The diffusion current is proportional to the gradient of the excess carrier distribution, so the currents in the base region do not follow a straight path from the edge of the base–emitter junction to the edge of the base–collector junction (Figure 4b). For further details see Appendix A.

Numerical simulations have shown (Figure 5) that, in agreement with intuition, the highest collector current density occurs in the narrowest region of the base. Determining the excess carrier distribution in the base $n\left(x,y\right)$ allows the current density distribution to be estimated. The proposed excess carrier distribution model allows the current density distribution along the X-axis of Figure 3 to be easily determined because, on this line, the gradient of the excess carrier distribution has only one component in the y-direction (see Figure 4b as well). With the current density distribution determined, it can be shown that the region of highest activity, which covers 90% of the current density, lies between −1.5·r and 1.5·r. Thus, the geometry of the device is an important factor for determining the flow of diffusion current in the base.

This is confirmed by the similarities of the curves in Figure 5. The current density distribution obtained from numerical simulations takes into account more factors than the proposed distribution model described by Equations (2)–(4). Among the main differences between the curves in Figure 5, one is the abrupt change in the current density distribution obtained from the numerical simulations for the value x/r = ±1. The simulations included a highly doped region in the vicinity of the base contacts. The comparison of the curves in Figure 5 is, therefore, qualitative. The determination of the gradient itself also makes it possible to analytically determine the diffusion current paths (Figure 4b) and calculate their length.

4. Fabrication Process

Transistor prototypes were fabricated at the Institute of Electron Technology (ITE, currently Łukasiewicz Research Network Institute of Microelectronics and Photonics) in Warsaw. The device design used differed slightly from the originally proposed VESTIC concept, where all structures are formed from a combination of 100–200 nm diameter circular masks. The process developed at ITE allowed for the fabrication of devices with a slit width of 50–200 nm between the semi-cylindrical polysilicon regions. All other dimensions of the devices were much larger. The original concept of making spatial contacts (metal pillars) within the volume of each region was also abandoned in favor of surface contacts. SOI substrate wafers, with a diameter of 4 inches and a Si layer over SiO₂ thickness of 170–190 nm, were used to fabricate the prototype series. For p-n-p bipolar devices, the concentration of phosphorus dopant atoms in monocrystalline was 2 × 10¹⁸ cm⁻³ for the latter two prototype wafers, while the polycrystalline silicon region was doped with boron atoms by the implantation of dopant atoms at a dose of 5 × 10¹⁵ cm⁻². For the n-p-n bipolar devices, the concentration of boron dopant atoms in the monocrystalline silicon was 1.2 × 10¹⁸ cm⁻³, while the dose of phosphorus doping in the polycrystalline silicon region was 5 × 10¹⁵ cm⁻². Technical details of the fabrication process can be found in [21,23].

The polysilicon is deposited in a single step, after deep etching of the emitter and collector regions, down to the buried oxide layer of the SOI substrate. Figure 6 shows the cross-section along the diagonal of the elementary cell after deposition of polysilicon (compare with Figure 2). All regions of the transistor are shorted. Therefore a necessary step after deposition of polysilicon is chemical–mechanical polishing (CMP) to remove the connections between the polysilicon regions above the slit, i.e., to separate emitter and collector regions.

Unfortunately, it was observed that the speed of polysilicon removal during the CMP process was different for p-type polysilicon and n-type silicon. As a result, on the wafer that contained both p-n-p and n-p-n devices, some transistors became damaged. As experiments have shown, attempts to separate these regions by other means, e.g., by polysilicon etching, did not yield the expected results.

There were three prototype wafers with junction structures produced. Among them, two prototype wafers contained fully functional bipolar transistors, including one with complementary devices. Each wafer contained 47 modules with bipolar transistors. Figure 7 shows SEM photos of the slit regions with various shapes and minimum base widths w_b0. To verify that unipolar and bipolar devices could be fabricated on the same process wafer, the layout of the bipolar devices was almost identical to that used in previous experiments with unipolar devices. All measurements were carried out on wafers.

5. Measurements

The first prototype wafer did not contain bipolar transistors, and it was used for experiments with unipolar junction field effect transistor VES-JFET [24], as well as for measurements of basic parameters such as resistances, capacitances, etc. The second wafer contained p-n-p bipolar transistors. The third prototype wafer contained both types of devices—p-n-p and n-p-n. Results of measurements of the devices from the third wafer are reported here, together with some data from the second wafer reported previously [21], in order to preserve context.

From all fabricated bipolar transistors, two groups called E-type and F-type were selected for measurements. The E-type devices have smaller base (slit) width than F-type structures. In all correctly working devices, the output (I_C vs. V_CE) characteristics, the I_C and I_B vs. V_BE characteristics (Gummel plots), and the current gain h_FE were measured. Figure 8 shows an example of the characteristics of an E-type p-n-p transistor. The Early voltage was 16.65 V for this structure, which was significantly lower than for F-type structures. The average value of the Early voltage for F-type devices was 29.6 [V], and the interval containing 90% of all values (from 18.17 V to 41.04 V) was calculated.

Figure 9 shows the I_C and I_B vs. V_BE characteristics, as well as the current gain h_FE of the same E-type device, whose output characteristics are shown in Figure 8. The calculated average slope factor m of the base current had a value of m between 1.17 and 2.21, while the collector current had values between 1 and 2. This is rather far from the ideal slope factor m = 1. The maximum current gain for this device equals 7.38.

In general, the average values of the current gain in tested devices were low, and the typical maximum current gain was between 8 and 25 for E-type structures. For F-type structures, it was 3 to 5 on average, while the maximum current gain was 16.

The temperature dependences of the collector and base current vs, V_BE were also measured. Based on the measurements, the calculated temperature coefficient of V_BE is 1.9 mV/ºC, except for the base current of the F-type structure, where it is 1.8 mV/°C [21].

The third prototype wafer contained complementary structures of bipolar transistors of p-n-p and n-p-n type. Moreover, the third wafer also contained a very simple circuit of the complementary bipolar inverter.

In addition to the measurements of the F-type transistors, measurements were made of the inverters and the individual transistors. The voltage–transfer curves of the inverters and the currents in each inverter were measured (see the next Section).

The vast majority of modules did not contain any working transistor, either p-n-p or n-p-n. This is a much worse result than in the second prototype wafer. It indicates that a key process step in the proposed VESTIC manufacturing process flow is the separation of the emitter and collector regions by means of the CMP process.

The transistors measured—752 structures in total—were the first working complementary bipolar transistors in VESTIC technology. As it can be seen in the accompanying diagrams (Figure 10), they were not complementary in terms of electrical properties. This was due to the mismatched doping levels of the opposite type regions and, probably, due to the physical properties of the dopants used, which were related to the segregation of the n-type dopant into either the grain boundary areas of polycrystalline or the edge area between polycrystalline and monocrystalline silicon [25].

6. The Inverters with Complementary Bipolar Transistors

As part of the third prototype wafer, simple inverter circuits were fabricated with two variants. Their layouts are shown in Figure 11.

The inverters were added to the topography of the prototype module in replacement of some earlier experimental structures. That is why they were limited in number only to six devices per module. Fortunately, out of the 282 devices, several presented correct input and transient characteristics of the transistors, as well as useful transfer characteristics of the inverter (Figure 12). Below are presented characteristics of the best inverter. The supply voltage and the logical level “1” equals 1 V.

The measured transfer characteristics indicate that it is possible to build working inverter circuits with complementary bipolar transistors. Such bipolar inverters were patented long ago [26] but never used. A recent paper [27] shows that thermally stabilized CBip (Complementary Bipolar) inverters and gates can be used for fully functional digital circuits.

The current flow in the bipolar inverter is different than in a CMOS inverter. At “0” at the input (i.e., V_in = 0 V), the current flows from the source of the supply voltage to the input (negative current in Figure 12b) and from the input to the source of the input signal. At “1” at the input (i.e., V_in = supply voltage), the input current flows from the external source (e.g., another gate) to the ground (positive current in Figure 12b). This is discussed in detail in [27] and illustrated in Figure 13. A unique feature of CBip-based digital circuits is that the same circuit can be used either as an ultra-low power circuit or as a high-performance circuit, and power vs. performance tradeoff can be easily controlled in a working circuit [27].

It is worth noting that the VES-BJT devices are symmetrical: emitters and collectors are made in the same polysilicon deposition and doping process, and their geometry is also the same. This is why they are electrically identical. A symmetrical bipolar transistor has very low saturation voltage. Moreover, a highly doped collector has very low series resistance. Both features are advantageous from the viewpoint of circuit applications.

7. Discussion

Using the measurement results of the VES-BJT transistors obtained from the second prototype wafer, which had the highest number of working structures, a comparison was made between the characteristics obtained from the measurements and the results of the numerical simulations.

A model of the semiconductor structure of the bipolar transistor was adjusted to match the parameters used in the prototype wafers. The present model contains components that were not initially included [18,19,20]. The most important modification to the model of the transistor structure was the addition of a 0.25 nm thin layer of silicon dioxide at the boundary between the polycrystalline and monocrystalline silicon regions, together with discontinuities—random points where the silicon dioxide was perforated. The model, modified in this way, proved to be surprisingly consistent with the observed current values (Figure 14). At the same time, it was observed that defects occurring at the base-collector metallurgical junction have greater effects on the characteristics of both base and collector currents than corresponding defects at the base-emitter metallurgical junction. The other important parameters which were adjusted in the model are the dimensions of the structure, where w_b0 = 250 nm and r = 450 nm.

In order to facilitate the comparison of many different characteristics with the simulation results, the measurements from the modules with the most operating structures were averaged, with a total of 112 averaged characteristics. The mean value and standard deviation for each characteristic point were determined. The resulting values were compared with the simulation results, and they are shown in Figure 15 and Figure 16. While the collector’s current characteristics largely agree with the simulation results (the area marked on the graphs covers more than 68% of the observations), the base current characteristics clearly differ in the area of voltages greater than 0.9 V. This is a high injection region for the prototype of VES-BJT transistors.

Determining the parameters of the Gummel–Poon model from the averaged values also yielded plots from the SPICE-type simulator (for model parameters, see Appendix B), which also agree reasonably well with the results of the numerical simulations in TCAD. A comparison is shown in Figure 17.

In light of the results of the simulations, it seems reasonable to conclude that, besides the influence of the mechanical–chemical polishing on the transistor properties, a very important aspect is the control of the silicon dioxide removal process prior to the polycrystalline silicon deposition step.

8. Conclusions

It has been shown that it is possible to fabricate complementary bipolar compatible transistors using VESTIC technology. By using complementary structures, it was possible to make a simple inverter. The experiments carried out confirm that digital circuits with this type of transistor can be made.

In the process flow that was used, the main difficulty in obtaining working transistors is the separation of polycrystalline silicon regions fabricated in a single step. A second problem is the presence of native silicon dioxide between the polycrystalline and monocrystalline regions. Any imperfections in this layer can affect the characteristics obtained and their symmetry.

Theoretically, the emitter and collector areas should be identical and can, therefore, be treated interchangeably. Imperfections in the prototype structures resulted in the lack of ideal symmetry. The imperfections in the prototypes were not limited to the thickness of the silicon dioxide; they also included the shape of the structures themselves, the width of the base (slit), and other physical characteristics, the repeatability of which was very limited.

Another problem that can arise in the fabrication of practical structures is the appropriate level of doping of various regions. Doping levels that are suitable for field effect structures are not suitable for bipolar transistors. Different doping levels in VESFETs and VES-BIPs require additional steps in the fabrication process. The measurements carried out showed that transistors fabricated with similar doping levels to those used in field effect devices resulted in structures with very low current gain.

The overall result of the research carried out should be considered a moderate success. It has been confirmed that structures with emitter and collector regions made of polysilicon can be an alternative to both the known vertical structures and the previously known lateral structures. It has also been shown that VES-BJT transistors can be fabricated as complementary structures, and they can also be used to create completely new logic circuits not previously used in bipolar technology. VESFET and VES-BIP devices could also be used in analog circuits. This is a large but unexplored research field.