A High-Power Density DC Converter for Medium-Voltage DC Distribution Networks

Abstract

A DC converter is the core equipment of voltage conversion and power distribution in a DC distribution network. Its operating characteristics have a profound impact on the flexible regulation of distributed resources in an active distribution network. It is challenging for the existing single-stage conversion topology to meet the requirements of distributed renewable energy connected to a multi-voltage level, medium-voltage grid. It is necessary to study the multistage transform power unit topology further, which can satisfy high reliability, high efficiency, and wide input range. This paper proposes a high-power density DC converter for medium-voltage DC networks with wide voltage levels. It adopts Buck-LLC integrated modular composition. The input ends of the high isolation resonant power unit are connected in series to provide high voltage endurance, and the output ends are connected in parallel to meet the high-power demand and achieve high-power transmission efficiency. The proposed series dual Buck-LLC resonant power unit topology can adjust the duty cycle of series dual buck circuits to meet the needs of different levels of medium-voltage DC power grids. The soft switching problem within the wide input range of all switching tubes is solved by introducing auxiliary inductors, thereby improving energy transmission efficiency. The auxiliary circuit and control parameters are optimized based on the research of each switching tube’s soft switching boundary conditions. Finally, an experimental prototype of a 6.25~7 kW power unit is designed and developed to prove the proposed topology’s feasibility and effectiveness. Great breakthroughs have been made both in theoretical research and engineering prototype development.

1. Introduction

With the large-scale penetration of renewable energies, storage, and various types of power electronic devices in recent years, the construction of a new power system with renewable energy as the main body has attracted wide attention. Flexible DC distribution network technology, with high-power quality, high stability, and flexible control advantages, has become a research hotspot [1,2,3,4,5]. Among them, the DC transformer is indispensable as the hub of energy convergence and distribution in the DC power grid.

Unlike the AC transformer, through the electromagnetic induction voltage conversion principle, the DC transformer can only use power electronic devices to achieve DC voltage manipulation. Some DC converter topologies have been mature applications, but not all topologies meet the connection needs of different medium voltage levels. A clamp multilevel circuit was first introduced by A. Nabae et al. [6], in which a midpoint clamp topology is proposed. The voltage stress of each device is only half of the DC side voltage. It has been widely used in high-voltage and high-power situations. However, with the voltage levels increasing, the number of power devices also increases, and the number of diodes increases by the square of the voltage levels. Therefore, the current practical application is mainly a three-level structure, which limits the voltage level of its application to generally less than 3 kV [7,8].

The concept of a modular multilevel structure was first proposed in 2001 by Rainer Marquardt, a scholar at the Bundeswehr University in Munich, Germany. The modular multilevel converter (MMC) adopts the cascade of sub-modules of half-bridge and full-bridge converter structures, which does not have the problems of dynamic voltage equalization and consistent triggering. It has been widely studied and applied in flexible DC transmission [9,10,11,12,13,14,15]. In [16], a compact MMC-DC/DC is proposed, which improves the integration of MMC-DC/DC, but the short-circuit fault on the DC side is not considered. When the DC side is short-circuited, a large number of submodule capacitors are short-circuited and discharged, resulting in a large short-circuit impulse current that endangers the safe operation of the transmission line. Thus, Professor Hui Li of Florida State University proposed the improved current source type MMC-DC/DC topology [17,18]. The bridge arm inductor is added based on the full-bridge submodule type MMC structure, and the high-frequency conversion port between the bridge arm inductor is led out. When there is a short-circuit fault on the DC side, the bridge arm inductor can limit the fault current well, and the whole bridge submodule can realize the DC side fault crossing.

The resonant converter and MMC topology combination have also received more and more attention in medium-voltage DC research [19]. A transformer-free resonant modular multilevel converter is proposed in [20], with inherent voltage-balance capability between modules. Moreover, it adopts phase-shift control between modules to obtain higher equivalent switching frequency and step-down ratios. However, the switching tube’s high voltage and current stress limit its application in high-voltage and high-power situations. In addition, the lack of electrical isolation limits its potential for further expansion. Therefore, [21] added isolation transformers to the topology, which can achieve electrical isolation and bidirectional energy flow. The voltage gain can also be manipulated by adjusting the number of submodules involved in modulation.

In the modular combined DC converter, [22] describes the connection mode of a modular combined converter in detail. It puts forward the general control method of four series-parallel combined systems. In [23], the modular combined DC converter’s operation characteristics and control methods are deeply studied, which is used to interconnect high and low-voltage DC power grids. In [24], the research of modular combined DC converters in flexible DC distribution is carried out. In [25], the modular combined DC converter is improved, and a topology based on four active full-bridge power modules is proposed. Due to its modular structure, high-frequency isolation, and other characteristics, modular combined DC converters have also been widely studied in AC-DC power electronic transformers [26,27,28].

In summary, the ISOP structure suits high-voltage and low-voltage output in medium-voltage conversion. The modular power unit can realize topology integration with a simple structure. It also has an immense capacity-expansion ability and can fully reflect the advantages of the power unit topology. Moreover, it can improve reliability, which is more suitable for the scenario of renewable energy access studied in this paper. However, with access requirements for broad voltage levels in medium-voltage power grids, single-stage conversion power units can hardly meet the criteria mentioned. The multistage conversion power unit topology with high reliability, high efficiency, and wide input range is required.

This paper proposes a Buck-LLC integrated modular combined DC converter for renewable energy access. A detailed analysis of the converter operating principles is performed to illustrate the features. A comparison with the current existing references and the proposed converter is presented in

Table 1. Comparisons among different DC converters in references.

Refs.	Voltage Stress	ZVS Ability	Tracking Performance
[9]	Medium	Poor	Poor
[13]	Low	Medium	Good
[20]	High	Medium	Medium
[25]	Low	Medium	Good
Proposed	Low	Good	Good

.

Based on the analysis of the working principle of the proposed topology, its DC gain characteristics, power characteristics, and soft switch characteristics were derived. The boundary conditions of soft switching for each switch tube were studied. The auxiliary circuit and control parameters were optimized and designed. The experimental results of the prototype verify the analysis, as mentioned above.

2. Modular Combined DC Converter Topology Based on Buck-LLC Integration

The modular combined DC converter based on Buck-LLC integration in this paper is shown in Figure 1. A series dual-buck integrated LLC converter (SDBuck-LLC) is used as a power unit. The input terminals of each power unit bear high voltage in series and output terminals in parallel to provide stable DC output. Considering the redundancy requirements of power units, redundant switches are connected to the input front of each power unit, which has the advantages of quick cutting of power units, fault current limiting, etc.

The above SDBuck-LLC comprises an auxiliary network, series buck circuit, integrated LLC resonant circuit, isolation transformer, and rectifier circuit. The converter uses high-frequency SiC MOSFET S₁~S₆ as the main power switch tubes to meet the stable operation at the high-input voltage operating point. Moreover, all switch tubes can realize soft switching in a wide working range. The buck circuit uses S₁~S₄ as the power switches, withstanding the high input voltage stress in series, and realizes the voltage reduction through the previous stage circuit. The S₅ and S₆ are switching tubes in the rear LLC resonant circuit, providing convenience for each switching tube’s ZVS through the resonator. Input capacitors C₁~C₄ and auxiliary inductors L_a1 and L_a2 form an auxiliary network to provide a bias current for S₁~S₄ to meet the conditions of realizing ZVS. As the output inductor of the series buck circuit, L_b is connected with1 S₂ and S₁ at point A and S₅ and S₆ at point C.

The clamping capacitor C_c, S₅, and S₆ together form an integrated half-bridge circuit, which can not only work with the front-end buck inductor L_b to adjust the clamping capacitor voltage V_Cc, but also form a half-bridge resonant circuit with the back-end cavity. The resonator cavity comprises the resonant inductor L_r, the resonant capacitor C_r, the excitation inductor L_m, and the high-frequency isolation transformer. The isolation transformer is used to realize the electrical isolation of the input and output terminals, and then the required low-voltage DC is obtained by the rectifier diode D₁~D₄ rectification. The transformer ratio is n_T:1. I_Lf, I_Lr, I_Lb, I_La1, I_La2 are the current flowing through the inductor L_f, L_r, L_b, L_a1, and L_a2, respectively. The forward reference direction of the currents is given in the form of an arrow in Figure 1.

3. SDBuck-LLC’s Operating Principle and Steady-State Analysis

3.1. Analysis of Working Mode and Working Principle

The power unit SDBuck-LLC adopts a fixed-frequency and fixed-phase-shift pulse-width modulation strategy and adjusts the output voltage by controlling the duty cycle of S₁~S₄ in the series buck circuit. The phase-shift angle between S₁ and S₅ and the auxiliary network provides appropriate current bias to ensure all switching tubes can realize ZVS within a wide input voltage range. LLC resonators operate at a fixed frequency. Specifically, the driving signals G₁ and G₄ of switching tubes S₁ and S₄ are the same, and the duty cycle is D₁; the driving signals G₂ and G₃ of the switching tube S₂ and S₃ are the same. S1 and S2 are complementary switching on. The duty cycle D₂ of the switching tube S5 is fixed at 0.5. S₅ and S6 are complementary switching on. Define G₁ rising edge leading G₅ rising edge φT_s.

By analyzing the relationship between D₁ and φ, the working state of the converter can be divided into eight working modes, as shown in

Table 2. Submodule SDBuck-LLC operational mode division.

Mode	1	2	3	4
X (0 < D1 ≤ 0.5)	0 < φ ≤ D1	D1 < φ ≤ 0.5	0.5 < φ ≤ D1 + 0.5	D1 + 0.5 < φ ≤ 1
Y (0.5 < D1 ≤ 1)	0 < φ ≤ D1–0.5	D1–0.5 < φ ≤ 0.5	0.5 < φ ≤ D1	D1 < φ ≤ 1

, and the brief waveform of each working mode is shown in Figure 2.

To ensure that the switching tube S₁~S₆ could meet the ZVS condition under various load conditions within a wide input voltage range, the buck inductor current I_Lb should be negative at the turn-on time of S₁, S₄, and S₆. The modes X4 and Y1 could not meet the current requirements above. Thus, modes X4 and Y1 are not included in the working range of the power unit. The proposed power unit adopts the fixed frequency and fixed phase-shift control scheme. To adapt to the power transmission in a wide range, the phase shift φT_s should not be too significant.

Thus, mode X3, mode Y3, and mode Y4 are excluded. In mode X2, D₁ < φ, the inductor L_b has two continuous current states in one cycle. Compared with mode X1, the RMS value of the buck inductor current ILb in mode X2 is slightly higher under the same voltage gain, transmission power, and ZVS conditions. Thus, Mode X2 will lead to higher loss. In summary, mode X1 and mode Y2 are the most suitable operating modes for the proposed SDBuck-LLC within the design requirements. Therefore, the two working modes are analyzed in detail in this paper. The critical waveforms of each mode are shown in Figure 3, and the corresponding equivalent circuits are shown in Figure 4, Figure 5, Figure 6 and Figure 7. For simple analysis, two assumptions are followed: (1) all devices, including switching tubes and capacitors, are ideal devices; and (2) the DC voltage ripple at both ends of the output capacitor is ignored.

(1) Mode X1:

Stage 1 (t₀~t_0′): Before time t₀, S₆ has been turned on. The driving signals G₁, G₄ of S₁, and S₄ rise at time t₀. Since the reverse diodes of S₁ and S₄ have been switched on, S₁ and S₄ realize ZVS, and V_AB rises from 0 to V_i. At this stage, the voltage of the auxiliary inductors L_a1 and L _a2 is -V_c1 and V_c4, which are both in the discharge and charging states, respectively. The input voltage V_CB of the resonator is 0, and the voltage applied at both ends of the buck inductor L_b is the difference between V_AB and V_CB, which is equal to Vi. L_b is in a state of high excitation, and I_Lb rises rapidly from the initial I_p value. The resonant current I_Lr increases by a sine wave at the resonant frequency f_r. The diodes D₂ and D₃ are on. The excitation inductor voltage V_Lm is clamped by the reverse output voltage V_o, and the excitation inductor current I_Lm gradually decreases.

Stage 2 (t_0′~t₁): At t_0′, I_Lr equals I_Lm. Diodes D₁~D₄ are turned off at this stage, and no current passes through the transformer winding. No energy is transmitted to the secondary side through the transformer. The resonant inductor L_r, the excitation inductor L_m, and the resonant capacitor C, participate in the resonance, and the resonant frequency is f_m. Because the excitation inductor is higher than the resonant inductor in the LLC resonant design, the change of resonant current at this stage is minimal.

Stage 3 (t₁~t_1′): At t₁, S₆ is turned off, and S₁ and S₄ remain on. This phase is the dead time between S₆ and S₅. The junction capacitors of S₅ and S₆ begin to discharge and charge, respectively, laying the foundation for the ZVS of S₅. At the same time, D₁ and D₄ switch on, and the excitation inductor Lm exits the resonance link.

Stage 4 (t_1′~t₂): At t_1′, the driving signal G₅ of S₅ begins to rise, then S₅ realizes ZVS, and the current value passing through S₅ at the opening moment is the difference between I_Lr and I_Lb. The input voltage V_CB of the resonator rises and equals the clamp capacitor voltage V_Cc. The voltage applied at both ends of L_b equals V_i–V_Cc, L_b is in a low excitation state, and the growth rate of I_Lb slows down. The auxiliary inductor currents I _La1 and I _La2 fall and rise simultaneously, but the direction reverses at this stage. In the resonator cavity, only the resonator inductor and the resonator capacitor participate in the resonance. I_Lr increases with the resonant frequency f_r as a sine wave, V_Lm is affected by V_o clamp, and I_Lm gradually increases.

Stage 5 (t₂~t_2′): at t₂, S₁ is turned off and S₅ remains open. I_La1 and I_La2, respectively, reach the lowest and highest values. This phase is the dead time between S₂ and S₁, and the junction capacitors of S₁ and S₂ begin to charge and discharge, respectively, providing conditions for the ZVS of S₂.

Stage 6 (t_2′~t₃): at t2′, the driving signal G2 of S2 rises, and then S2 realizes ZVS. The current value passing through S₂ at the opening moment is the difference between I Lra1 and ILb. VAB drops to 0, and the voltage applied at both ends of Lb equals -VCc, which is in a deep demagnetization state. ILb drops rapidly. The voltage applied in the ports of La1 and La2 is Vc2 and -Vc3, respectively, in the charging and discharging state. In this stage, the resonator resonates at two resonant frequencies, fr and fm. The condition of resonant frequency fm is like that of the above stage 2.

Stage 7 (t₃~t_3′): at t₃, S₅ is turned off, S₂ and S₃ remain on, and the dead time between S₅ and S₆ is entered again. Then, the junction capacitors of S₅ and S₆ begin to charge and discharge, respectively, providing conditions for the ZVS of S₆. At the same time, in this stage, the rectifier bridge starts to reverse pilot, and the excitation inductor L_m exits the resonant link.

Stage 8 (t_3′~t_4′): at t_3′, the driving signal G₆ of S₆ rises, and then S₆ realizes ZVS. The current value passing through S₆ at the opening moment is the difference between the inductor current I_Lb and the resonant current I_Lr. The input voltage V_CB of the resonator drops to 0. The voltage applied at both ends of L_b is 0, and L_b is in the continuous current state. I_Lb remains unchanged. The rising and falling rates of I_La1 and I_La2 remain the same, but the direction reverses at this stage. In the resonator cavity, only the resonant inductor and the resonant capacitor participate in the resonance. The resonant current I_Lr decreases as a sine wave with the resonant frequency f_r. The excitation inductor voltage V_Lm is affected by the reverse output voltage V_o clamp, and I_Lm gradually decreases.

Stage 9 (t_4′~t₄): at t_4′, S₂ is turned off, S₆ remains open, and I_La1 and I_La2 reach the highest and lowest values, respectively. The dead time between S₂ and S₁ starts again. The junction capacitors of S₁ and S₂ begin to discharge and charge, respectively. At t₄, the driving signal of S₁ rises, and S₁ realizes ZVS. The current value passing through S₁ at the opening moment is the difference between I_Lb and I_La1; then, the next cycle is entered.

(2) Mode Y2:

The proposed power unit SDBuck-LLC works in mode Y2 roughly the same as in mode X1. The main differences are as follows:

(a)

In stage 4 of mode Y2, the voltage applied at both ends of L_b is V_i-V_Cc, which is negative at this time, in a low demagnetization state, and I_Lb slowly decreases.

(b)

The deep excitation state time corresponding to stages 1, 2, and 3 is lengthened, and the resonant negative half-cycle corresponding to this period is also lengthened.

(c)

The deep demagnetization state time corresponding to stages 6 and 7 is shortened, and the resonant positive half-period corresponding to this period is also shortened.

3.2. Characteristics of DC Voltage Gain

The presence of the auxiliary network shown in Figure 1 does not affect the voltage gain of each mode of the power unit, and the overall gain of the converter can be obtained by analyzing the two-stage converter gain separately. Define M_Buck as the DC gain of the front-stage buck converter and M_LLC as the DC gain of the back-stage half-bridge LLC resonant converter; then, the gain of the power unit is:

$$M_{\mathrm{dc}}=M_{\mathrm{Buck}}•M_{\mathrm{LLC}}$$

(1)

Through the above modal analysis, V_AB is a square wave with a duty cycle of D₁ and an amplitude of V_i. V_CB is a square wave with a duty cycle of 0.5 and an amplitude of V_Cc. For buck inductor L_b, according to the volt-second balance principle, it can be obtained:

$$D_1{V}_{\mathrm{i}}=(1-0.5)V_{\mathrm{cc}}$$

(2)

Namely:

$$M_{Buck}=V_{Cc}/V_i=2D_1$$

(3)

Based on fundamental wave analysis, the steady-state equivalent circuit of the SDBuck-LLC resonant converter studied in this paper is shown in Figure 8.

First, the following parameter definitions are listed below:

$$\mathrm{Equivalent} \mathrm{resistance} R_{\mathrm{eq}}: R_{eq}=n_{\mathrm{T}}{}^2{R}_{o.ac}=\frac{8n_{\mathrm{T}}{}^2}{{\pi }^2}{R}_o$$

(4)

$$\mathrm{Quality} \mathrm{Factor} \mathrm{Q}: Q=\frac{1}{R_{\mathrm{eq}}}\sqrt{\frac{L_{\mathrm{r}}}{C_{\mathrm{r}}}}$$

(5)

$$\mathrm{Normalized} \mathrm{frequency} f_{\mathrm{n}}: f_n=f_s/f_{sn}$$

(6)

$$\mathrm{Inductance} \mathrm{coefficient} \lambda : \lambda =L_r/L_m$$

(7)

$$\mathrm{Resonant} \mathrm{angular} {\omega }_{\mathrm{r}}: {\omega }_{\mathrm{r}}=\sqrt{\frac{1}{L_{\mathrm{r}}{C}_{\mathrm{r}}}}$$

(8)

According to the steady-state equivalent circuit shown in Figure 8, the input impedance Zin can be calculated by Equation (9).

$$Z_{in}(j\omega )=jh\omega L_r-\frac{j}{h\omega C_r}+jh\omega L_m//R_{eq}$$

(9)

The transfer function of the h harmonic of the resonator can be calculated by Equation (10).

$$H_h(j\omega )=\frac{1}{n_T}\cdot \frac{jh\omega L_m//R_{eq}}{(jh\omega L_m//R_{eq})+jh\omega L_r-\frac{j}{h\omega C_r}}$$

(10)

Therefore, the gain M_LLC of the half-bridge LLC resonant circuit can be obtained in Equation (11).

$$M_{LLC}=\frac{V_O}{V_{\mathrm{Cc}}}=\frac{1}{2}\Vert H_1(j2\pi f_e)\Vert =\frac{1}{2n_T\sqrt{(1+\lambda -\frac{\lambda }{f_n^2}{)}^2+Q^2\cdot (f_n-\frac{1}{f_n}{)}^2}}$$

(11)

LLC resonant converters mainly adjust the output voltage by changing the switching frequency. Thus, a wide input voltage range corresponds to a wide switching frequency adjustment range, reducing the converter efficiency. In practical application, for ZVS realization and efficiency improvement, the switching frequency of the switching tube should be near the resonant frequency f_r as far as possible. Thus, M_LLC is 0.5. The integrated converter proposed in this paper works at the resonant frequency point.

In summary, the ideal DC gain of the SDBuck-LLC converter is:

$$M_{\mathrm{dc}}=\frac{D_1}{n_T}$$

(12)

3.3. Voltage Stress and Power Characteristics

The voltage stress of a power device is one of the critical theoretical bases for its selection. Based on the modal analysis of mode X1, the power unit’s voltage stress of each power device is described in detail. In stage 1 and stage 2, the switching tubes S₁, S₆, S₄, and inductor L_b form a loop with the input end, and the output diode D₂ and D₃ are on. The switching tube S₂ and S₃ need to jointly withstand the input voltage V_i, and the voltage at both ends of the inductor L_b is also V_i. The diode D₁ and D₄ must withstand the output voltage V_o, and the switching tube S₅ must withstand the capacitor voltage V_Cc.

In stage 6, the switch tube S₂, S₃, S₅, buck inductor L_b, and capacitor C_c form a voltage loop, and the output diodes D₁ and D₄ are on. The switching tubes S₁ and S₄ must withstand the input voltage V_i jointly, and the voltage at both ends of the inductor L_b is V_Cc. The diode D₂ and D₃ must withstand the output voltage V_o, and the switch tube S₆ must withstand the capacitor voltage V_Cc.

Therefore, the voltage stress of the switching tube S₁~S₄ is:

$$V_{\mathrm{S}1\text{-}\max }=V_{\mathrm{S}2\text{-}\max }=V_{\mathrm{S}3\text{-}\max }=V_{\mathrm{S}4\text{-}\max }=V_{\mathrm{i}}/2$$

(13)

The voltage stress of the switching tube S₅, S₆ is:

$$V_{\mathrm{S}5\text{-}\max }=V_{\mathrm{S}6\text{-}\max }=V_{\mathrm{Cc}}=2D_1{V}_{\mathrm{i}}$$

(14)

The voltage stress of diode D₁~D₄ is:

$$V_{\mathrm{D}1\text{-}\max }=V_{\mathrm{D}2\text{-}\max }=V_{\mathrm{D}3\text{-}\max }=V_{\mathrm{D}4\text{-}\max }=V_{\mathrm{o}}=D_1{V}_{\mathrm{i}}$$

(15)

According to the above modal analysis, the current expression of inductor L_b in mode X1, Y2 can be obtained as follows; I_p is the current value of the buck inductor when S₁ is turned on, and it is also the minimum current value in its cycle.

$$I_{\mathrm{Lb}\text{-}\mathrm{X}1\mathrm{Y}2}(t)=\{\begin{array}{c}{I}_p+V_{\mathrm{i}}t/L_{\mathrm{b}}\\ I_p+(V_{\mathrm{Cc}}\phi T_{\mathrm{s}}+(V_{\mathrm{i}}-V_{\mathrm{Cc}})t)/L_{\mathrm{b}}\\ I_p+(V_{\mathrm{Cc}}\phi T_{\mathrm{s}}+V_{\mathrm{i}}{D}_1{T}_{\mathrm{s}}-V_{\mathrm{Cc}}t)/L_{\mathrm{b}}\\ I_p\end{array}\begin{array}{c}0\le t\le \phi T_{\mathrm{s}}\\ \phi T_{\mathrm{s}}\le t\le D_1{T}_{\mathrm{s}}\\ D_1{T}_{\mathrm{s}}\le t\le (\phi +0.5)T_{\mathrm{s}}\\ (\phi +0.5)T_{\mathrm{s}}\le t\le T_{\mathrm{s}}\end{array}$$

(16)

It shows that the inductance L_b and phase-shift angle affect the inductor current’s peak value. The larger the inductance L_b, the smaller the peak value of inductance current and its effective value, and the smaller the on-loss of the converter.

$$P_{\mathrm{i}}=P_{\mathrm{o}}=\frac{1}{T_{\mathrm{s}}}{\displaystyle {\int }_{t_0}^{t_4}{V}_{\mathrm{AB}}^{}(t)I_{\mathrm{Lb}}^{}(t)\mathrm{d}t=}\frac{1}{T_{\mathrm{s}}}{\displaystyle {\int }_{t_0}^{t_4}{V}_{\mathrm{CD}}^{}(t)I_{\mathrm{Lb}}^{}(t)\mathrm{d}t}$$

(17)

$$P_{\mathrm{X}1\mathrm{Y}2}=0.5I_{\mathrm{p}}{V}_{\mathrm{Cc}}+\frac{V_{{}_{\mathrm{Cc}}}^2{T}_{\mathrm{s}}}{4L_{\mathrm{b}}}(-\frac{{\phi }^2}{D_1}+2\phi -D_1+0.5)$$

(18)

According to Equation (17), the transmission power of the converter under the ideal conditions of mode X1, Y2 can be obtained, as shown in Equation (18).

It can be seen from the above equations that P, Ip, D1, and φ are mutually restricted under the premise that the other parameters of the converter device are determined. When the input voltage is determined, the duty cycle D1 is also determined, and Ip is closely related to the transmission power P and phase shift φT_s.

Figure 9 shows the relationship between output power P, duty cycle D1, and inductance Lb under different phase shifts φT_s when fs = 80 k, Vo = 400 V, and I_p = 3 A in modes X1 and Y2. Obviously, with the increase in phase shift φT_s, the modes X1 and Y2 of the converter gradually tend to work at a higher duty cycle, and the power that can be transmitted also increases. Moreover, the value of inductance L_b also affects the power that can be transmitted; the more significant the L_b, the weaker the power transmission capacity.

3.4. Soft-Switching Characteristics

Through modal analysis, it can be found that the ZVS realization of switching tube S₁~S₄ is mainly determined by inductor current I_Lb, I_La1, and I_La2. The ZVS realization of switching tube S₅~S₆ is mainly determined by inductor current I_Lb and resonant current I_Lr. Taking mode X1 as an example, the switching tubes S₂ and S₃ are off at t_4′ time. Before the switching tube S₄ and S₁’s driving signal rises, the auxiliary inductors L_a1 and L_a2 will provide a reverse bias current. The junction capacitance of the switching tube S₄ and S₁ gradually begins to discharge, and the drain-source voltage V_ds1 and V_ds4 rapidly drops to 0. From that point, the driving signal of the switching tubes S₁ and S₄ begins to rise, and S₁ and S₄ realize ZVS. For the switching tube S₂ and S₃, the switching tubes S₁ and S₄ are off at t₂ time. Before the switching tube S₂ and S₃’s driving signal rises, the inductors L_a1, L_a2, and L_b provide reverse currents. The junction capacitance of the switching tube S₂ and S₃ gradually begins to discharge, and the drain-to-source voltage V_ds2 and V_ds3 rapidly drops to 0. From that point, the driving signal of the switching tube S₂ and S₃ begins to rise, and S₂ and S₃ realize ZVS. For the switching tube S₅, the switching tube S₆ is off at t_1′, and before the drive signal of S₅ rises, the buck inductor L_b will provide a reverse current for S₅. The junction capacitance of S₅ gradually discharges, and the drain-to-source voltage V_ds5 rapidly drops to 0. After that, the drive signal of S₅ begins to rise, and S₅ realizes ZVS. For the switching tube S₆, the switching tube S₅ is off at t₃, and before the driving signal of the switching tube S₆ rises, the reverse current comes from the resonant inductor L_r. The junction capacitance of the switching tube S₆ gradually begins to discharge, and the drain-to-source voltage V_ds6 rapidly drops to 0. After that, the driving signal of the switching tube S₆ begins to rise, and S₆ realizes ZVS. It is defined that the complete charge and discharge current of the junction capacitor is ΔI_ZVS. To ensure that the junction capacitor can discharge to 0 to meet ZVS in each switching dead time, the instantaneous current value of the switching tubes at the opening time must be less than −ΔI_ZVS.

Therefore, the ZVS condition of each switching tube in the power unit can be expressed by the following equation:

$$I_{\mathrm{S}1\text{-}\mathrm{on}}=I_{\mathrm{S}4\text{-}\mathrm{on}}=I_{\mathrm{Lb}}(t_0)-I_{\mathrm{La}1}(t_0)\le -\Delta I_{\mathrm{ZVS}}$$

(19)

$$I_{\mathrm{S}2\text{-}\mathrm{on}}=I_{\mathrm{S}3\text{-}\mathrm{on}}=I_{\mathrm{La}1}(t_{2’})-I_{\mathrm{Lb}}(t_{2’})\le -\Delta I_{\mathrm{ZVS}}$$

(20)

$$I_{\mathrm{S}5\text{-}\mathrm{on}}=I_{\mathrm{Lr}}(t_1)-I_{\mathrm{Lb}}(t_1)\le -\Delta I_{\mathrm{ZVS}}$$

(21)

$$I_{\mathrm{S}6\text{-}\mathrm{on}}=I_{\mathrm{Lb}}(t_{3’})-I_{\mathrm{Lr}}(t_{3’})\le -\Delta I_{\mathrm{ZVS}}$$

(22)

By extension of the power expression mentioned above, Equation (23) can be obtained.

$$I_{\mathrm{p}}=\frac{2P_{\mathrm{X}1\mathrm{Y}2}}{V_{\mathrm{Cc}}}-\frac{V_{{}_{\mathrm{Cc}}}^2{T}_{\mathrm{s}}}{2L_{\mathrm{b}}{V}_{\mathrm{Cc}}}(-\frac{{\phi }^2}{D_1}+2\phi -D_1+0.5)$$

(23)

Then, Equation (24) can be obtained:

$$I_{\mathrm{Lb}}(t_{3’})=I_{\mathrm{Lb}}(t_0)=I_{\mathrm{p}}$$

(24)

According to the above analysis, when the converter is in the half-load or no-load state, its ZVS condition is easier to achieve than the full-load state. Therefore, the following analysis only considers the ZVS condition of the converter at full load. I_La1(t_2′) and I_Lb(t_2′) are constant negative and positive values, respectively, so the inherent characteristics of S₃ and S₂ meet the ZVS condition in a wide operating range. The ZVS conditions of S₁, S₄, S₅, and S₆ need to be analyzed according to specific working conditions.

The Fourier expansion expression of the input voltage V_CB of the resonator is shown as follows:

$$V_{\mathrm{CB}}=(1-D_2)V_{\mathrm{Cc}}+V_{\mathrm{sh}}$$

(25)

$$V_{sh}={\displaystyle {\sum }_{h=1}^{\infty }\frac{\sqrt{2}{V}_{\mathrm{Cc}}}{h\pi }}\sqrt{1-\cos (2h\pi D_2)}\cdot \sin (2h\pi f_{\mathrm{s}}t+{\theta }_h)$$

(26)

Among them,

$${\theta }_h={\tan }^{-1}(\frac{\sin (2h\pi D_2)}{1-\cos (2h\pi D_2)})=\frac{\pi }{2}-h{D}_2\cdot \pi$$

According to the resonator transfer function shown in Equation (10), the expressions of excitation inductance current I_Lm and equivalent load current I_oe in the steady-state equivalent circuit shown in Figure 8 can be easily derived.

$$I_{\mathrm{Lm}}=n\cdot {\displaystyle {\sum }_{\mathrm{h}=1}^{\infty }\frac{H_{\mathrm{h}}{V}_{\mathrm{CBh}}}{jh\omega L_m}}$$

(27)

$$I_{\mathrm{oe}}=n\cdot {\displaystyle {\sum }_{h=1}^{\infty }\frac{H_h{V}_{\mathrm{CBh}}}{R_{eq}}}$$

(28)

The resonant current I_Lr can be obtained by adding the above two formulas.

$$\begin{array}{l}{I}_{Lr}(t)={\displaystyle {\sum }_{h=1}^{\infty }\frac{\sqrt{2}{V}_{\mathrm{Cc}}}{h\pi }}\sqrt{1-\cos (2h\pi D_2)}\\ \cdot \{\frac{\left|n_{\mathrm{T}}\cdot H_h\right|}{R_{eq}}\sin (2h\pi f_{\mathrm{s}}t+{\theta }_h+\angle (n_{\mathrm{T}}\cdot H_h))\\ -\frac{\left|n_{\mathrm{T}}\cdot H_h\right|}{h\omega L_m}\cos (2h\pi f_{\mathrm{s}}t+{\theta }_h+\angle (n_{\mathrm{T}}\cdot H_h))\}\end{array}$$

(29)

When fs = 80 k, P = 6.25 kW, and V_o = 400 V, the relationship between the opening current I_S5on of S₅ and I_S6on of S₆, duty cycle D₁, phase shift φT_s, and buck inductance L_b can be obtained by combining the inductance expression (16) derived above, as shown in Figure 10 and Figure 11, respectively. Considering the transmission power and voltage level comprehensively, the value of ΔI_ZVS is 1.5 A, and the dark-colored plane in the figure is the reference plane of I_on = −1.5 A. It can be found that the ZVS range of S₆ and S₅ is relatively wide. When φ is less than 0.1, ZVS of S₅ cannot be realized under the condition of a low-duty cycle. The increase in inductance L_b causes the opening current of S₅ to increase. When the duty cycle of S₆ is more significant than 0.3, there are working points where S₆ cannot realize ZVS. But with the increase of phase shift φT_s or the decrease of inductance L_b, the working range meeting the ZVS condition will gradually expand.

According to the volt-second balance of L_a1, namely (1 − D₁)T_sV_c2 = D₁T_sV_c1, and the symmetry of the series-type double-buck circuit (V_c1 + V_c2 = V_c3 + V_c4 = V_i/2), it can be calculated:

$$V_{\mathrm{c}1}=(1-D_1)V_{\mathrm{i}}/2$$

(30)

$$V_{\mathrm{c}2}=D_1{V}_{\mathrm{i}}/2$$

(31)

The peak value of the auxiliary inductance current can be calculated by the following equation:

$$\left|i_{La1-pk+}\right|=\left|i_{La1-pk-}\right|=\frac{1}{L_{a1}}{\displaystyle \underset{D_1{T}_s/2}{\int }{V}_{c1}dt=\frac{D_1(1-D_1)}{4f_s{L}_{\mathrm{a}1}}}{V}_{\mathrm{i}}$$

(32)

$$I_{\mathrm{S}1\text{-}\mathrm{on}}=I_{\mathrm{S}4\text{-}\mathrm{on}}=I_{\mathrm{p}}-\frac{D_1(1-D_1)}{4f_s{L}_{\mathrm{a}1}}{V}_{\mathrm{i}}$$

(33)

When f_s = 80 k, P = 6.25 kW, V_o = 400 V, and L_b = 75 μH, the relationship between the opening current I_S1on and I_S4on of S₁ and S₄, duty cycle D₁, phase shift φT_s, and auxiliary inductance L_a1 can be obtained, as shown in Figure 12. The gray plane in the figure is the reference plane of I_on = −1.5 A. The increase in phase shift φT_s reduces the ZVS difficulty of S₁ and S₄; the decrease of auxiliary inductance L_a1 increases the negative bias current when the switching tube is opened, making ZVS easier to realize. At the same time, the introduced bias current will lead to a slight increase in the conduction loss. From this point of view, the value of the auxiliary inductance L_a1 should not be too small.

4. Experimental Verification

4.1. Experimental Prototype

An experimental prototype of 6.25~7 kW was designed and developed to prove the feasibility of the proposed power unit topology and the correctness of the above analysis. It meets the requirements of a wide input voltage range of 750 V~1430 V.

Table 3. Experimental prototype parameters.

Parameters	Values	Parameters	Values
Input voltage (Vi)	750 V~1430 V	Rated output power (Po*)	6.25~7 kW
Output voltage (Vo)	400 V	Rated switching frequency (fsn)	80 kHz
Resonant inductor (Lr)	14.3 μH	Transformer turns ratio (nT)	1:1
Input capacitance (C1~C4)	50 μF	Auxiliary inductors (La1, La2)	180 μH
Phase shift (φ)	0.15	Resonant inductor (Lb)	75 μH
Clamp capacitor (Cc)	55 μF	Resonant capacitance (Cr)	276.6 nF

shows the device parameters of the experimental prototype, and Figure 13 shows the experimental prototype.

4.2. Experimental Scheme

The DC converter engineering prototype meets the needs of 6–10 kV medium-voltage DC power grid access, including eight power units, with one power unit redundancy switching capability. When eight power units operate, the input voltage range of a single power unit is 750~1250 V, the output voltage is 400 V, and the output power is 6.25 kW. When seven power units operate, the input voltage range of a single power unit is 860~1430 V, and the output power is 7.15 kW.

Figure 14 shows the steady-state experimental waveforms under different input voltages and rated power conditions when eight power units work. V_Tp is the input voltage on the primary side of the transformer. Figure 14a,b corresponds to the steady-state waveforms when the input voltage of the power unit is 750 V and D₁ = 0.55. The power unit works in mode Y2. As shown in the figure, the amplitude of V_AB is equal to the input voltage, which is 750 V. The amplitude of V_CB, the input voltage of the resonator, is equal to the clamp capacitor voltage V_Cc, which is 800 V. Under D₂ = 0.5 and nT = 1, the output voltage is stable at 400 V. Currently, the current offset provided by the auxiliary network is the lowest, and it is the most difficult with which to realize ZVS. Figure 14c,d corresponds to the steady-state waveforms when the input voltage of the power unit is 1250 V, D₁ = 0.34, and mode X1. As shown in the figure, the V_AB amplitude equals the input voltage, which is 1250 V. V_CB amplitude, namely the input voltage of the resonator, is equal to the clamp capacitor voltage V_Cc, which is still 800 V. In these two operating modes, each electrical parameters of the LLC resonator are the same. Figure 15 shows the steady-state experimental waveforms when the input voltage of the power unit is 1400 V when seven power units operate. The output power is 7 kW, D₁ = 0.29, and the power unit works in mode X1. As shown in the figure, the V_AB amplitude equals the input voltage, which is 1400 V. The V_CB amplitude is equal to the clamp capacitor voltage V_Cc, which is still 800 V.

Figure 16 shows the ZVS waveforms of each switching tube at different input voltages under full load conditions. Due to the symmetric relationship between S₁ and S₄, and S₂, and S₃, only related waveforms of S₁ and S₂ are shown in this paper. Figure 16a,c,e,g respectively shows the drain-source voltage and gate-source voltage waveforms of S₁, S₂, S₅, and S₆ when the input voltage is 750 V under full-load conditions. It can be seen that S₁ and S₆ are in the most difficult ZVS condition in the whole working range. The time difference between the falling edge of drain-source voltage and the rising edge of gate-source voltage of S₁ is less than 100 ns. The time difference between the falling edge of drain-source voltage and the rising edge of gate-source voltage of S₆ is only 20 ns. Figure 16b,d,f,h respectively show the drain-source voltage and gate-source voltage waveforms of S₁, S₂, S₅, and S₆ when the input voltage is 1250 V under full-load conditions. The time difference between the drain-source voltage falling edge and the gate-source voltage rising edge of each switching tube is more incredible than 160 ns, which can quickly achieve ZVS.

Figure 17 shows the ZVS waveforms of each switching tube at different input voltages under a 20% load condition (1200 W). Figure 17a,c,e,g respectively corresponds to the ZVS waveforms of S₁, S₂, S₅, and S₆ when the input voltage is 750 V. Figure 17b,d,f,h respectively corresponds to the ZVS waveforms of S₁, S₂, S₅, and S₆ when the input voltage is 1250 V. It can be seen that under light load conditions, there is a long-time difference between the drain-source voltage falling edge and the gate-source voltage rising edge. Thus, ZVS can be easily realized. In summary, ZVS can be realized in a wide input voltage and output power range for all switching tubes for the proposed SDBuck-LLC resonant converter. Figure 18 shows the efficiency comparison of the power unit under different input voltages. The variation curves of converter efficiency with output power are shown under input voltage 750 V, 950 V, and 1250 V, respectively. The power of each operating point is measured by the power analyzer HIOKI-PW6001. As seen in Figure 18, the efficiency of the power unit decreases slightly with the increase in the input voltage. Still, the efficiency under full-load conditions is higher than 95% in a wide input voltage range.

5. Conclusions

A DC transformer is an efficient power electronic equipment with DC voltage conversion and DC energy distribution abilities, which is the key technology for the development and construction of a DC power grid. This paper studied the DC converter for renewable energy access, and a Buck-LLC integrated modular combined DC converter was proposed. Great breakthroughs were made in theoretical research and engineering prototype development. The topology can meet the requirements of a wide voltage range on the medium voltage side. The converter takes SDBuck-LLC as its power unit, which consists of an auxiliary network, series buck, integrated LLC resonant circuit, isolation transformer, and rectifier circuit. The circuit structure adopts an integrated design and has a high-power density. The duty cycle of a series double-buck circuit can be adjusted to suit the application of a wide input voltage range. Through the auxiliary circuit and the phase shift φT_s introduced, all the switching tubes can realize ZVS in a wide input voltage range. Thus, the turn-on loss is eliminated, and the overall conversion efficiency of the converter is improved. The experimental prototype of the power unit was designed, the experimental results of the prototype were shown, and the feasibility of the proposed power unit was verified. The work in this paper is helpful for subsequent research on DC converters, such as the analysis of the electromagnetic energy interaction mechanism inside the DC converter, the construction of a complete and accurate loss model of the DC converter, and the exploration of the core factors affecting the operation efficiency of the DC converter. Therefore, this work lays a foundation for proposing a globally oriented theory and method for the optimization of the operation efficiency of the DC converter.