A Novel Framework of Genetic Algorithm and Spectre to Optimize Delay and Power Consumption in Designing Dynamic Comparators

Abstract

In integrated circuit (IC) design, analog circuits contribute significantly as the interface between real and digital world signals. Although they make up a relatively small portion of the overall circuit, their design process is often most time-consuming, mostly from the phase of manual iteration of circuit parameters to meet design specifications. Therefore, the design automation of analog circuits with the help of efficient optimization techniques arises as a promising candidate to address the issue. Among optimization algorithms, while the genetic algorithm (GA) has been shown to be effective in finding near-optimal solutions, it has not been extensively applied to the field of analog circuit design. Hence, this paper proposes a method to utilize GA in the optimization of a widely used circuit topology, namely the comparator. The comparator is considered the fundamental block in the design of most analog-to-digital converters (ADCs). For high-speed ADCs, dynamic comparators are usually chosen for the purpose of high speed and power efficiency. In summary, this paper introduces an innovative GA-Spectre architecture to optimize the dynamic comparator with respect to delay and power consumption. The post-optimized results are optimistic with a 72.61 ps delay and 3.11 µW power dissipation.

1. Introduction

Comparators are considered the heart of analog-to-digital converters (ADCs). They are used as a means to convert from analog domain signals to digital domain signals in modern signal processing and communications. In the design of high-speed ADCs, low-power and high-speed comparators are of great demand [1]. Thanks to strong positive feedback and dynamic bias provided by a pair of cross-coupled inverters as the latching stage, dynamic comparators have higher speed and less static power consumption compared to static comparators [2]. Therefore, with a view to optimizing comparators’ performance with respect to speed and power consumption, the dynamic comparator is chosen as a feasible candidate.

The analog circuit design consists of three main stages: topology selection, component sizing, and layout extraction. In the design of the comparator, this paper focuses on the first two stages. Both stages must ensure that the resulting circuit meets the specifications [3,4]. Since the first phase completes with the topology of the dynamic comparator, the second phase involves choosing the size of components to meet design specifications. Due to the repetitive task of manual iteration of circuit parameters, this sizing procedure is considered time-consuming and monotonous [4,5]. Hence, automation in the process of optimizing the sizes of circuits’ components is critical to the ability to design high-performance circuits quickly [6].

To address the issue of laborious circuit sizing in analog circuit design, effective optimization techniques are crucial. Automated component sizing for analog circuit optimization can be classified as equation-based methods and simulation-based methods. On the basis of circuit analysis, equation-based methods utilize posynomial or monomial functions built on circuit parameters to represent specific circuit performances of interest. Despite the fast execution time and high certainty of reaching a global optimum, deriving such equations is often challenging and time-consuming. Moreover, to obtain explicit and closed-form expressions for circuit performances, various approximations and simplifications are usually applied, at the expense of MOSFET’s higher-order effects, hence the model’s accuracy and completeness. By contrast, simulation-based counterparts are independent of analytical functions but instead rely on SPICE simulation data. In the optimization procedure, these methods handle fitness functions (or objective functions) and design constraints in the form of black box functions, which are evaluated by simulated results. This approach might ensure better accuracy, generality, and convenience. Consequently, our optimization system in this research is chosen to be simulation-based.

Among various existing equation-free optimization methods, the genetic algorithm (GA), based on the Darwinian principle of natural selection and concepts of natural genetics, has been found to be an effective solution to large search spaces without being trapped in local minima [5]. In spite of GA’s advantages, it has not been extensively applied to the field of circuit design. To the authors’ best experience and knowledge, the algorithm is mostly implemented in the design of operational amplifiers as in [5,6] and has not been utilized for the case of the dynamic comparator. Furthermore, the design of [6,7] uses the HSPICE simulator for circuit simulations, which normally requires an additional step of using scripting languages for collecting necessary data. Alternatively, the Spectre simulator allows the use of the SKILL programming language’s syntax in Ocean-based scripts. In view of the role of the Spectre simulator in the overall optimization system, the flexibility of SKILL programming establishes the authors’ preference of Spectre over its HSPICE counterpart in terms of manipulating output data.

In recognition of GA’s strengths and Spectre’s convenience of data output, this paper proposed a GA-Spectre model that might break new ground as the prototype for the optimization problem of propagation delay and power dissipation for the dynamic comparator design. With only 100 iterations of GA, the optimized dynamic comparator achieved a power-delay product (PDP) of 0.2258 fJ, including an average delay of 72.61 ps and power consumption of 3.11 µW at a 1 GHz clock frequency and 1.2 V supply voltage. These are desirable and promising values for assessment parameters, especially for the case of PDP since this work’s PDP surpasses its counterparts in the works of [8,9,10,11]. More importantly, thanks to its flexibility and adaptability, our GA-Spectre framework could also be the optimization tool for different circuits, which is likely to revolutionize the mindset and work approach of analog circuit design engineers.

The remaining part of the paper is organized as follows. Section 2 demonstrates the operation of the single-tail dynamic comparator as well as its delay and power analysis. Subsequently, Section 3 illustrates the optimization process, including GA’s flow and the proposed GA-Spectre model to optimize the delay and power of the dynamic comparator. Simulation results and discussion are presented in Section 4, followed by the conclusion of the paper in Section 5.

2. Dynamic Comparator Analysis

2.1. Working Principle of the Single-Tail Dynamic Comparator

The operation of the conventional single-tail dynamic comparator depicted in Figure 1 consists of two phases [12]:

Reset phase: The reset phase starts when clk = 0. In this phase, the reset transistors ${\mathrm{M}}_8$ and ${\mathrm{M}}_9$ are on while the tail transistor ${\mathrm{M}}_1$ is off. As a result, output nodes out+ and out− are pulled up to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$, which ensures the initial condition as well as a valid logic level for the comparator.

Comparison phase (decision-making phase): The comparison phase starts when clk = ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$. In this phase, the reset transistors ${\mathrm{M}}_8$ and ${\mathrm{M}}_9$ are off while the tail transistor ${\mathrm{M}}_1$ is on. The output nodes out+ and out−, previously precharged to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$, turn ${\mathrm{M}}_4$ and ${\mathrm{M}}_5$ on. Also, these two output nodes begin to discharge their voltages, which is still high enough to keep ${\mathrm{M}}_4$ and ${\mathrm{M}}_5$ on. The discharging rate of out+ and out− depends on the voltages at two input nodes in+ and in−.

When in+ > in−: Out+ discharges at a faster rate compared to out−. This means that the voltage at out+ drops to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{|\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}|$ before out−, making ${\mathrm{M}}_7$ turn on before ${\mathrm{M}}_6$. Since (${\mathrm{M}}_4,{\mathrm{M}}_6$) and ${(\mathrm{M}}_5,{\mathrm{M}}_7)$ together form back-to-back inverters, the latch regeneration is activated. Hence, out+ and out− are pulled down to GND and pulled up to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$, respectively.

When in+ < in−: The circuit works in the opposite manner with the final result of out+ and out− being pulled up to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ and pulled down to GND, respectively.

In summary, during the comparison phase:

$$\mathrm{i}\mathrm{n}+>\mathrm{i}\mathrm{n}-\Rightarrow \left\{\begin{array}{c}\mathrm{o}\mathrm{u}\mathrm{t}+=\mathrm{G}\mathrm{N}\mathrm{D}\\ \mathrm{out}-={\mathrm{V}}_{\mathrm{D}\mathrm{D}}\end{array}\right.$$

$$\mathrm{i}\mathrm{n}+<\mathrm{i}\mathrm{n}-\Rightarrow \left\{\begin{array}{c}\mathrm{o}\mathrm{u}\mathrm{t}+={\mathrm{V}}_{\mathrm{D}\mathrm{D}}\\ \mathrm{o}\mathrm{u}\mathrm{t}-=\mathrm{G}\mathrm{N}\mathrm{D}\end{array}\right..$$

2.2. Delay Analysis

The propagation delay is one of the key features of a comparator. It consists of two parts:

Delay for the capacitors ${\mathrm{C}}_0$ and ${\mathrm{C}}_1$ to discharge to the point when ${\mathrm{M}}_6$ and ${\mathrm{M}}_7$ turn on:

$${\mathrm{t}}_0=\frac{{\mathrm{C}}_{\mathrm{i}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|}{{\mathrm{I}}_3}\approx \frac{{\mathrm{C}}_{\mathrm{i}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|}{\frac{{\mathrm{I}}_1}{2}}=2\frac{{\mathrm{C}}_{\mathrm{i}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|}{{\mathrm{I}}_1}$$

(1)

where ${\mathrm{C}}_{\mathrm{i}}$ is the load capacitor at the output nodes with equal values (i = 0, 1 and ${\mathrm{C}}_0={\mathrm{C}}_1$); ${\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}$ is the threshold voltage of p-channel MOSFETs ${\mathrm{M}}_6,{\mathrm{M}}_7$; and ${\mathrm{I}}_1,{\mathrm{I}}_3$ are the drain currents through ${\mathrm{M}}_1,{\mathrm{M}}_3$, respectively.

Delay from the two cross-coupled inverters:

Since the threshold voltage of the comparator is considered to be half of the supply voltage, or $\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}}{2}$, it means that

$$∆{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}=\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}}{2}$$

(2)

where $∆{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}$ is the output voltage swing and ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ is the supply voltage.

Therefore, the latch delay is calculated as

$${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}=\frac{{\mathrm{C}}_{\mathrm{i}}}{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}\ln \left(\frac{∆{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}}}{∆{\mathrm{V}}_0}\right)=\frac{{\mathrm{C}}_{\mathrm{i}}}{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}\ln \left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}/2}{∆{\mathrm{V}}_0}\right)$$

(3)

where $\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}$ is the equivalent transconductance of the latch and $∆{\mathrm{V}}_0$ is the output voltage difference.

Also, at time ${\mathrm{t}}_0$:

$$∆{\mathrm{V}}_0=\left|{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}+}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}\right|=\left|\left({\mathrm{V}}_{\mathrm{D}\mathrm{D}}-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\right)-\left({\mathrm{V}}_{\mathrm{D}\mathrm{D}}-\frac{{\mathrm{I}}_2{\mathrm{t}}_0}{{\mathrm{C}}_{\mathrm{i}}}\right)=\left|\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|-\frac{{\mathrm{I}}_2{\mathrm{t}}_0}{{\mathrm{C}}_{\mathrm{i}}}\right|=\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\left(1-\frac{{\mathrm{I}}_2}{{\mathrm{I}}_3}\right)\right|=\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\frac{{∆\mathrm{I}}_{\mathrm{i}\mathrm{n}}}{{\mathrm{I}}_3}$$

(4)

where ${\mathrm{I}}_3$ is the drain current through ${\mathrm{M}}_3$ and $∆{\mathrm{I}}_{\mathrm{i}\mathrm{n}}$ is the current difference at the input ends.

Since ${\mathrm{I}}_3\approx \frac{{\mathrm{I}}_1}{2}$:

$$∆{\mathrm{V}}_0=\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\frac{{∆\mathrm{I}}_{\mathrm{i}\mathrm{n}}}{{\mathrm{I}}_1/2}=\frac{2\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\sqrt{{\mathsf{\beta }}_{\mathrm{2,3}}{\mathrm{I}}_1}}{{\mathrm{I}}_1}∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}=2\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\sqrt{\frac{{\mathsf{\beta }}_{\mathrm{2,3}}}{{\mathrm{I}}_1}}∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(5)

where ${\mathsf{\beta }}_{\mathrm{2,3}}\equiv {\mathsf{\beta }}_2,{\mathsf{\beta }}_3$ are the current factors of ${\mathrm{M}}_2,{\mathrm{M}}_3,$ respectively.

Substitute (5) into (3):

$${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}=\frac{{\mathrm{C}}_{\mathrm{i}}}{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}\ln \left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}/2}{2\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\sqrt{{\mathsf{\beta }}_{\mathrm{2,3}}/{\mathrm{I}}_1}∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}\right)=\frac{{\mathrm{C}}_{\mathrm{i}}}{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}\ln \left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}}{4\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}\sqrt{\frac{{\mathrm{I}}_1}{{\mathsf{\beta }}_{\mathrm{2,3}}}}\right)$$

(6)

The total delay is the sum of its two parts:

$${\mathrm{t}}_{\mathrm{d}\mathrm{e}\mathrm{l}\mathrm{a}\mathrm{y}}={\mathrm{t}}_0+{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}=2\frac{{\mathrm{C}}_{\mathrm{i}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|}{{\mathrm{I}}_1}+\frac{{\mathrm{C}}_{\mathrm{i}}}{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}\ln \left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}}{4\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}\sqrt{\frac{{\mathrm{I}}_1}{{\mathsf{\beta }}_{\mathrm{2,3}}}}\right)$$

(7)

The simulation results illustrate that ${\mathrm{t}}_0$ dominates ${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}$ [1] and ${\mathrm{t}}_{\mathrm{d}\mathrm{e}\mathrm{l}\mathrm{a}\mathrm{y}}$ follows the change in ${\mathrm{t}}_0$. In other words, when ${\mathrm{I}}_1$ decreases, ${\mathrm{t}}_0$ increases and ${\mathrm{t}}_{\mathrm{d}\mathrm{e}\mathrm{l}\mathrm{a}\mathrm{y}}$ hence increases, and vice versa.

2.3. Power Analysis

In order to prevent inaccuracies at boundaries between operating regions, instead of MOSFET’s existing models, its time-variant model is applied to analyze the power of the conventional dynamic comparator [13]. The formula for drain current applicable to all operating regions is expressed in the work of [14] as

$${\mathrm{I}}_{\mathrm{D}}={\mathrm{I}}_{\mathrm{Z}}\left[{\ln }^2\left(1+{\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{G}\mathrm{S}}-{\mathrm{V}}_{\mathrm{T}}}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}}\right)-{\ln }^2\left(1+{\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{G}\mathrm{S}}-{\mathrm{V}}_{\mathrm{T}}-\mathrm{n}{\mathrm{V}}_{\mathrm{D}\mathrm{S}}}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}}\right)\right]$$

(8)

where ${\mathrm{V}}_{\mathrm{G}\mathrm{S}}$ is the gate–source potential difference, ${\mathrm{V}}_{\mathrm{T}}$ is the threshold voltage, ${\mathrm{V}}_{\mathrm{D}\mathrm{S}}$ is the drain–source potential difference, and ${\mathsf{\varphi }}_{\mathrm{t}}$ is the thermal voltage $\frac{\mathrm{k}\mathrm{T}}{\mathrm{q}}$.

${\mathrm{I}}_{\mathrm{Z}}$ and $\mathrm{n}$ are given by

$${\mathrm{I}}_{\mathrm{Z}}=2\mathsf{\mu }{\mathrm{C}}_{\mathrm{o}\mathrm{x}}\frac{\mathrm{W}}{\mathrm{L}}\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}^2$$

(9)

$$\mathrm{n}={\left[1-\frac{\mathsf{\gamma }}{2\sqrt{{\mathrm{V}}_{\mathrm{G}\mathrm{B}}-{\mathrm{V}}_{\mathrm{T}0}+{\left(\mathsf{\gamma }/2+\sqrt{2{\mathsf{\varphi }}_{\mathrm{F}}}\right)}^2}}\right]}^{-1}$$

(10)

where $\mathsf{\gamma }$ is the body-effect coefficient, ${\mathrm{V}}_{\mathrm{G}\mathrm{B}}$ is the gate-bulk potential difference, ${\mathrm{V}}_{\mathrm{T}0}$ is the threshold voltage with zero source-bulk voltage ${\mathrm{V}}_{\mathrm{S}\mathrm{B}}$, ${\mathsf{\varphi }}_{\mathrm{F}}=\frac{\mathrm{k}\mathrm{T}}{\mathrm{q}}\ln \left(\frac{{\mathrm{N}}_{\mathrm{s}\mathrm{u}\mathrm{b}}}{{\mathrm{n}}_{\mathrm{i}}}\right)$, k is Boltzmann’s constant, q is the electron charge, ${\mathrm{N}}_{\mathrm{s}\mathrm{u}\mathrm{b}}$ is the doping density of the subtrate, and ${\mathrm{n}}_{\mathrm{i}}$ is the density of electrons in undoped silicon.

For one period of comparison, the average power of the supply voltage is calculated as

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}{\mathrm{r}}_{\mathrm{a}\mathrm{v}\mathrm{g}}=\frac{1}{\mathrm{T}}{\int }_0^{\mathrm{T}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}\mathrm{d}\mathrm{t}={\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\int }_0^{\mathrm{T}}{\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}\mathrm{d}\mathrm{t}$$

(11)

where ${\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}$ is the frequency of the comparator’s clock, ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ is the supply voltage, and ${\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}$ is the current drawn from the supply voltage.

When clk = 0 (reset phase), in order to charge the output nodes to ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$, a current is drawn from the supply voltage source.

When clk = ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ (decision-making phase), assuming that in+ > in−, according to the working principle of the conventional dynamic comparator explained above, ${\mathrm{M}}_7$ will turn on before ${\mathrm{M}}_6$. Since ${\mathrm{M}}_5$ has already been on, there is a current drawn from ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ from ${\mathrm{M}}_7$. Therefore, during this comparison phase, ${\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}$ is equivalent to the current through ${\mathrm{M}}_7$. Meanwhile, as the voltage at out− discharges to the ground, ${\mathrm{M}}_5$ will be off and there will be no current drawn from ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$. As a result, such a comparator is classified as dynamic [13].

To calculate the average power during the comparison phase, we apply the time-variant model for current through ${\mathrm{M}}_7$ described in (8) to the formula in (11):

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}{\mathrm{r}}_{\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\mathrm{I}}_7{\int }_{{\mathrm{t}}_0}^{{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}\left[{\ln }^2\left(1+{\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{DD}}-{\mathrm{V}}_{\mathrm{out}-}\left(\mathrm{t}\right)-\left|{\mathrm{V}}_{\mathrm{THP}}\right|}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}}\right)-{\mathrm{l}\mathrm{n}}^2\left(1+{\mathrm{e}}^{\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}\left(\mathrm{t}\right)-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|-\mathrm{n}\left({\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}+}\left(\mathrm{t}\right)\right)}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}}\right)\right]\mathrm{d}\mathrm{t}$$

(12)

where the lower and upper bound of the integral in (12), ${\mathrm{t}}_0$ and ${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}$, respectively, are clarified in the delay analysis part.

For the integral in (12) to be solvable, it is necessary that the approximation ${\ln }^2\left(1+{\mathrm{e}}^{\mathrm{x}}\right)\approx {\ln }^2\left({\mathrm{e}}^{\mathrm{x}}\right)={\mathrm{x}}^2$ when ${\mathrm{e}}^{\mathrm{x}}\gg 1$ is used. Since the exponential terms of (12) are much larger than 1, the mentioned approximation is valid.

Therefore:

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}{\mathrm{r}}_{\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\mathrm{I}}_7{\int }_{{\mathrm{t}}_0}^{{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}\left[{\left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}\left(\mathrm{t}\right)-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}\right)}^2-{\left(\frac{{\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}-}\left(\mathrm{t}\right)-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|-\mathrm{n}\left({\mathrm{V}}_{\mathrm{D}\mathrm{D}}-{\mathrm{V}}_{\mathrm{o}\mathrm{u}\mathrm{t}+}\left(\mathrm{t}\right)\right)}{2\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}}\right)}^2\right]\mathrm{d}\mathrm{t}$$

(13)

Simplifying the integral in (13), the closed-form expression for power is obtained as

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}{\mathrm{r}}_{\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\mathrm{I}}_7\left(\frac{1}{8\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}^2}\right){\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\left[2\mathrm{k}-\mathrm{n}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|+\left(2\mathrm{k}+\mathrm{n}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\right){\mathrm{e}}^{\frac{-2\left({\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}-{\mathrm{t}}_0\right)}{{\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}}-4\mathrm{k}{\mathrm{e}}^{-\frac{{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}-{\mathrm{t}}_0}{{\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}}\right]$$

(14)

where $\mathrm{k}={\mathrm{V}}_{\mathrm{D}\mathrm{D}}-\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|$ and ${\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}=\frac{\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}}{{\mathrm{C}}_{\mathrm{i}}}$ ($\mathrm{g}{\mathrm{m}}_{\mathrm{e}\mathrm{q}}$ is the equivalent transconductance of the latch as mentioned in the delay analysis).

For the case in+ < in−, power dissipation can be obtained by substituting ${\mathrm{I}}_6$ with ${\mathrm{I}}_7$ in the formula of (14):

$$\mathrm{P}\mathrm{o}\mathrm{w}\mathrm{e}{\mathrm{r}}_{\mathrm{a}\mathrm{v}\mathrm{g}}={\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}{\mathrm{V}}_{\mathrm{D}\mathrm{D}}{\mathrm{I}}_6\left(\frac{1}{8\mathrm{n}{\mathsf{\varphi }}_{\mathrm{t}}^2}\right){\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\left[2\mathrm{k}-\mathrm{n}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|+\left(2\mathrm{k}+\mathrm{n}\left|{\mathrm{V}}_{\mathrm{T}\mathrm{H}\mathrm{P}}\right|\right){\mathrm{e}}^{\frac{-2\left({\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}-{\mathrm{t}}_0\right)}{{\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}}-4\mathrm{k}{\mathrm{e}}^{-\frac{{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}-{\mathrm{t}}_0}{{\mathsf{\tau }}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}}}\right]$$

(15)

2.4. Cadence Virtuoso Simulation

The conventional dynamic comparator is designed and simulated in the 65 nm technology of the TSMCN65 process. The frequency at which the circuit functions is ${\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}$ = 1 GHz and the supply voltage is ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ = 1.2 V. The voltage at node in− is constant at 1 V as a reference voltage, while in+ is a pulse voltage source with the maximum and minimum value of 1.005 V and 0.995 V, respectively, and a frequency of 100 MHz. With this input configuration, $∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$ = 5 mV.

Figure 2 shows the transient simulation of the conventional comparator in one clock period that consists of both the comparison and the reset phase. ${\mathrm{t}}_0$ and ${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}$ are the parameters explained above in Section 2. The total propagation delay of the dynamic comparator is the sum of ${\mathrm{t}}_0$ and ${\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}$ in Figure 2, ${\mathrm{t}}_{\mathrm{d}\mathrm{e}\mathrm{l}\mathrm{a}\mathrm{y}}={\mathrm{t}}_0+{\mathrm{t}}_{\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{c}\mathrm{h}}$.

Figure 3 demonstrates the transient simulation of the current ${\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}$ drawn from the supply voltage ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ in one period from 0 to 1 ns. To calculate the power dissipation of the dynamic comparator, we integrate ${\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}$ with respect to time from 0 to 1 ns and multiply with ${\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}$ and ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ as in Equation (11) to obtain the result.

3. Optimization by Genetic Algorithm

3.1. Genetic Algorithm (GA)

The genetic algorithm (GA) is one of the evolutionary computation methods used for a wide variety of optimization problems. GA’s basis is the principle of natural selection, in which suitable individuals in a specific environment survive and reproduce while others are eliminated [15]. With the idea of “survival to the fittest”, better solutions are generated thanks to the successive evolution of generations.

The implementation of GA is described in the flowchart of Figure 4:

As illustrated in Figure 4, rather than a single solution, GA utilizes a population of individuals for parallel search in the problem space. The algorithm starts by initializing a population of a fixed size with randomly created solutions. These solutions, usually encoded in a bitstring of a fixed length, are modeled as chromosomes. The chromosomes consist of genes, which are represented by one bit or a group of bits. Every generation, the bitstrings of chromosomes are decoded into their actual representation. Then, based on a fitness function, the fitness values of all individuals are evaluated to find the best individual in the current population. These fitness values evaluate how close the current solution is to the predetermined target or the optimal solution of the problem. After this step, the stop condition, including the number of iterations or the comparison with the target, is considered. If this condition is not met, the algorithm continues with the selection process.

According to the fitness value, a subgroup of chromosomes—the parents—is selected to create the new population of offspring by the process of crossover and mutation. During crossover, two parents are randomly selected from the set of chosen parents; their bitstrings are separated into parts at the same location and swapped together to create two child chromosomes for the next generation. In order to prevent the solutions from becoming stuck at local optima, the next step involves the mutation process, which can be as simple as inverting one bit in the bitstring or more complicated as complete gene modifications [15]. The crossover and mutation steps are implemented with certain probabilities ${\mathrm{r}}_{\mathrm{c}\mathrm{r}\mathrm{o}\mathrm{s}\mathrm{s}}$ and ${\mathrm{r}}_{\mathrm{m}\mathrm{u}\mathrm{t}}$ inside the range [0, 1], respectively. Since a new population has already been created, the algorithm continues with the decoding and fitness calculation. When the fitness results of the children population are available, the best chromosome can be found. Afterward, the terminating condition is re-evaluated. GA stops only when this condition is true; otherwise, the loop of regeneration carries on. The output result of GA is the decoded solution of the chromosome with the best fitness value.

From another viewpoint, GA can also be summarized by Pseudocode 1:

Pseudocode 1: Genetic algorithm (GA)

decoded_solution genetic_algorithm() {   population = initial_population();   best = calculate_fitness(decode(population));   while (!stop_condition) {     parents = select(population);     children = crossover(parents);     new_population = mutation(children);     best = calculate_fitness(decode (new_population));   }   return decode(best); }

3.2. Proposed GA-Spectre Model to Optimize Delay and Power of the Dynamic Comparator

When applying GA to optimization problems, the structure of the algorithm almost remains unchanged. Meanwhile, it is necessary to make suitable modifications to the step of fitness calculation for specific problems. For the optimization of analog circuit design, the “Calculate fitness” block in Figure 4 consists of two substeps. The first one is delay and power simulations, which are executed by the Cadence Virtuoso tool in the TSMCN65 process, with the help of the Spectre simulation platform. The remaining step is the evaluation of fitness values according to delay and power data collected in the previous step.

In this research, GA is implemented by the Python programming language since Python is currently considered the most widely used programming language and has various built-in libraries for AI algorithms’ programming. Also, Spectre is chosen as the circuit simulator for the whole design as an alternative to related studies. Circuit simulations in the works of [6,7] are performed by HSPICE, whose output data are mostly presented in the simulator’s predetermined format. Thus, scripting languages are usually necessary to create files containing output results of compatible format for Python processing of GA. On the other hand, it is possible for SKILL programming’s syntax to be integrated in Ocean-based scripts of the Spectre simulator. This means that simulation results can be arranged in users’ desirable format without further use of scripting languages. On account of its function in the optimization system and convenience in output data format, Spectre is preferably chosen as a practical candidate for circuit simulations.

The interrelation between Spectre and Python is described as follows: At first, the values for the population of design variables are created by Python and sent to Spectre via an Ocean-based script. This Ocean script is responsible for automated circuit simulations based on received numbers and the results are sent back and further processed by the Python script to evaluate fitness scores of each individual. This repetitive process carries on until the algorithm reaches its stopping point. The mentioned Spectre-Python correlation is further clarified by the block diagram in Figure 5:

Regarding the case of optimizing the delay and power of the dynamic comparator, first and foremost, determining the optimization variables—parameters that mainly contribute to delay and power results—is essential. Since we use the TSMCN65 process for the design, the lengths of all the MOSFETs in the circuit are set to 65 nm. According to the delay analysis in Section 2, since $∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}$ of the dynamic comparator is fixed at 5 mV, ${\mathrm{I}}_1$ and ${\mathrm{C}}_{\mathrm{i}}$ are responsible for delay adjustment. Therefore, we declare two delay-related variables: the width of ${\mathrm{M}}_1$ (${\mathrm{W}}_1$) and the capacitors’ values $\left({\mathrm{C}}_{\mathrm{i}}\right)$. Similarly, as the values of ${\mathrm{V}}_{\mathrm{D}\mathrm{D}}$ and the frequency of the clock signal clk are assigned to 1.2 V and 1 GHz, respectively, our power-related variables are determined based on the current ${\mathrm{I}}_{\mathrm{s}\mathrm{u}\mathrm{p}\mathrm{p}\mathrm{l}\mathrm{y}}$, which is the sum of four currents flowing through ${\mathrm{M}}_6,{\mathrm{M}}_7,{\mathrm{M}}_8,\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{M}}_9.$ Due to the symmetry of the circuit, the widths of ${\mathrm{M}}_6$ and ${\mathrm{M}}_7$, and ${\mathrm{M}}_8$ and ${\mathrm{M}}_9$ should be equal. Hence, we declare two more variables: the width of ${\mathrm{M}}_6$ and ${\mathrm{M}}_7$ $\left({\mathrm{W}}_{67}\right)$ and the width of ${\mathrm{M}}_8$ and ${\mathrm{M}}_9$ $\left({\mathrm{W}}_{89}\right)$. For the remaining MOSFETs, the widths of ${\mathrm{M}}_2\left({\mathrm{W}}_2\right)$ and ${\mathrm{M}}_3\left({\mathrm{W}}_3\right)$, and ${\mathrm{M}}_4\left({\mathrm{W}}_4\right)$ and ${\mathrm{M}}_5\left({\mathrm{W}}_5\right)$ are also set to equal values to ensure the circuit’s symmetry. For optimal performance of delay and power consumption, the simulation results indicate that ${\mathrm{W}}_2={\mathrm{W}}_3=0.21\mathrm{\mu }\mathrm{m},\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{W}}_4={\mathrm{W}}_5=0.12\mathrm{\mu }\mathrm{m}$. In total, we need four optimization variables, namely ${\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89},\mathrm{a}\mathrm{n}\mathrm{d}{\mathrm{C}}_{\mathrm{i}}$. In order to satisfy the range of the process and assure the functional correctness of the conventional dynamic comparator, the simulation results indicate that the bounds for the four above-mentioned variables are [0.12 µm; 2 µm], [0.12 µm; 2 µm], [0.12 µm; 2 µm], and [0.1 fF; 0.8 fF], respectively.

For subsequent GA initializing steps, the number of bits for each chromosome representation is defined to be 16 bits and the population size is chosen to be six individuals per population, correspondingly. While crossover has a high probability, the probability of mutation is typically low; the authors in [16] showed that ${\mathrm{r}}_{\mathrm{c}\mathrm{r}\mathrm{o}\mathrm{s}\mathrm{s}}$ and ${\mathrm{r}}_{\mathrm{m}\mathrm{u}\mathrm{t}}$ are inside the ranges [0.8; 0.95] and [0.001; 0.05], respectively. Finally, the choice of a suitable fitness function is also critical. The figure of merit (FoM) to compare the performance of dynamic comparators can be either energy efficiency as in [8] or PDP as in [17]. With a view to optimizing both delay and power of the dynamic comparator, we choose the FoM in the form of PDP as the fitness function for GA. The comparator is considered to perform better with a lower value of PDP, which means that a lower PDP is equivalent to higher fitness values.

In other words, our optimization problem can be summarized as

$$\begin{array}{c}\mathrm{minimize}\mathrm{PDP}({\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89},{\mathrm{C}}_{\mathrm{i}})\hfill \\ \mathrm{subject}\mathrm{to}\mathrm{L}=65\mathrm{nm},{\mathrm{W}}_2={\mathrm{W}}_3=210\mathrm{nm},{\mathrm{W}}_4={\mathrm{W}}_5=120\mathrm{nm}\hfill \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}∆{\mathrm{V}}_{\mathrm{i}\mathrm{n}}=5\mathrm{mV},{\mathrm{V}}_{\mathrm{D}\mathrm{D}}=1.2\mathrm{V},{\mathrm{f}}_{\mathrm{c}\mathrm{l}\mathrm{k}}=1\mathrm{GHz}\hfill \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}0.12\mathsf{\mu }\mathrm{m}\le {\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89}\le 2\mathsf{\mu }\mathrm{m}\hfill \\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}0.1\mathrm{fF}{\le \mathrm{C}}_{\mathrm{i}}\le 0.8\mathrm{fF}\hfill \end{array}$$

4. Results and Discussion

The simulation results indicate that the lowest value for PDP of 0.2254 fJ is achieved for the case of ${\mathrm{r}}_{\mathrm{c}\mathrm{r}\mathrm{o}\mathrm{s}\mathrm{s}}$ = 0.8 and ${\mathrm{r}}_{\mathrm{m}\mathrm{u}\mathrm{t}}$ = 0.05. With PDP = 0.2254 fJ, the delay and power of the conventional dynamic comparator are 72.48 ps and 3.11 µW, respectively. PDP fitness values as well as the delay and power over 100 iterations of GA are illustrated in Figure 6 and Figure 7, respectively.

As can be clearly observed in Figure 7, the values for delay and power vary in an unpredictable and non-monotonous manner. However, their corresponding PDP in Figure 6 decreases monotonously throughout the 100 iterations. Since GA produces chromosomes with better fitness values at the end of each iteration, PDP’s downward trend conforms to the working principle of the algorithm. In terms of the variables declared for GA, the optimal set $\left({\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89},{\mathrm{C}}_{\mathrm{i}}\right)$ = (0.4463 µm, 0.1277 µm, 0.1553 µm, 0.1 fF) is obtained after 100 iterations of the algorithm. Nevertheless, it is worth noticing that the process grid of the TSMCN65 process is 5 nm. This means that the widths of ${\mathrm{M}}_1,{\mathrm{M}}_6,{\mathrm{M}}_7,{\mathrm{M}}_8,{\mathrm{M}}_9$ need to be rounded to their closest feasible values as $\left({\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89}\right)$ = (0.445 µm, 0.13 µm, 0.155 µm). Re-simulated results with the set $\left({\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89}{,\mathrm{C}}_{\mathrm{i}}\right)$ = (0.445 µm, 0.13 µm, 0.155 µm, 0.1 fF) vary slightly with the final values of 72.61 ps for delay, 3.11 µW for power consumption, and 0.2258 fJ for PDP.

The post-optimization sizes of all MOSFETs in the circuit are presented in

Table 1. Post-optimization transistors’ sizes.

Device	Size (W/L)
${\mathrm{M}}_1$	0.445 µm/65 nm
${\mathrm{M}}_2,{\mathrm{M}}_3$	0.21 µm/65 nm
${\mathrm{M}}_4,{\mathrm{M}}_5$	0.12 µm/65 nm
${\mathrm{M}}_6,{\mathrm{M}}_7$	0.13 µm/65 nm
${\mathrm{M}}_8,{\mathrm{M}}_9$	0.155 µm/65 nm
${\mathrm{C}}_0,{\mathrm{C}}_1$	0.1 fF

:

Table 2. Performance summary of different dynamic comparator designs.

Parameters	References
	[1]	[8]	[9]	[10]	[11]	This Work
CMOS Process (nm)	90	65	65	90	40	65
Supply voltage (V)	1.2	1	1.2	1	1.1	1.2
Clock frequency (GHz)	3.07	20	6	1	6	1
Average delay (ps)	410	14.28	42.7	51.76	54	72.61
Power dissipation (µW)	0.24	67.8	381	32.62	288	3.11
PDP (fJ)	0.0984	0.968	16.3	1.67	15.552	0.2258
Energy per conversion (fJ/conv.)	0.07818	3.39	63.5	32.62	48	3.11
Kickback noise (mV)	N/A	N/A	N/A	N/A	N/A	122

summarizes the performance of the conventional dynamic comparator of this research and other research works:

As the conventional dynamic comparator in this work has zero static power consumption, its power consumption at 1 GHz is much lower than that of the circuit of [10]. Since clock frequency is directly proportional to power dissipation as presented in Equation (11), the designs of [8,9,11] with higher clock frequency exhibit a higher power than our design, which is reasonable. Meanwhile, the power consumption in [1] is still lower despite operating at higher frequency. The parameter energy per conversion, which is equal to the ratio of power over sampling frequency (or clock frequency), is therefore needed to evaluate dynamic comparators’ performance with respect to power. From Table 2, it is clear that our research work has the second-lowest energy per conversion value at 3.11 fJ per conversion.

In addition, compared to [9,10,11], our work has approximately a 20% higher average delay. On the contrary, our average delay is less than one-fifth in comparison with the delay of [1]. Because delay and power trade off with each other, PDP is utilized as the FoM in the case of optimizing both parameters. With respect to PDP, our design obtains the second-best value of 0.2258 fJ versus the lowest number of 0.0984 fJ by [1].

For further assessment of our optimization system, the optimization platform of the Analog Design Environment (ADE) GXL, which offers both local and global optimization of circuit performances of interest, can be utilized as a suitable reference model. For setup steps, PDP is chosen as the optimization function, and the optimization variables and their bounds are similar to the GA-Spectre-based system. Regarding ADE GXL’s local optimization, the post-optimization transistors’ sizes $\left({\mathrm{W}}_1,{\mathrm{W}}_{67},{\mathrm{W}}_{89}{,\mathrm{C}}_{\mathrm{i}}\right)$ = (0.445 µm, 0.13 µm, 0.155 µm, 0.1 fF) obtained from the GA-Spectre framework are set as the reference points. With regard to global optimization from ADE GXL, due to our constrained data, the C version Feasible Sequential Quadratic Programming (CFSQP) is selected by the Spectre simulator as the optimization algorithm. It is worth acknowledging that while the CFSQP utilizes a single individual for each iteration rather than a population of individuals, GA in our system is implemented on a population of six individuals per iteration. Hence, for a decent comparison, the PDP result of 100 iterations of our GA-based optimization system should be compared with that of 6 × 100 = 600 iterations of the ADE GXL’s global optimization tool.

Table 3. Comparison between different optimization models.

Parameters	Optimization Model
	ADE GXL’s Local Optimization	ADE GXL’s Global Optimization	This Work’s GA-Based Optimization
PDP (fJ)	0.227	0.236	0.2258

indicates that the result of PDP acquired by our optimization system is lower and has a higher convergence rate compared to that of ADE GXL’s local as well as global optimization tool.

Figure 8 depicts the layout of the conventional dynamic comparator, which occupies an area of approximately 198.4 µ${\mathrm{m}}^2$ (16 µm × 12.4 µm). Additionally,

Table 4. Layout summary of different dynamic comparator designs.

Parameters	References
	[1]	[8]	[9]	[10]	[11]	This Work
CMOS Process (nm)	90	65	65	90	40	65
Estimated dimension (µm × µm)	N/A	12.22 × 15	10.9 × 13	7.2 × 8.1	13.5 × 4.5	16 × 12.4
Estimated area (µ${\mathrm{m}}^2$)	N/A	183.3	141.7	58.32	60.75	198.4

demonstrates layout parameters of different designs while

Table 5. Comparison between pre-layout and post-layout simulation results of this work’s comparator.

Parameters	Pre-Layout	Post-Layout
Average delay (ps)	72.61	82.32
Power dissipation (µW)	3.11	3.58
PDP (fJ)	0.2258	0.2947
Energy per conversion (fJ/conv.)	3.11	3.58
Kickback noise (mV)	122	163

represents a comparison between pre-layout and post-layout simulation results.

5. Conclusions

GA can be considered a novel approach of using a software algorithm to optimize analog circuits. Instead of a trial-and-error process of circuit sizing, the GA-Spectre model solves the problem in a much more effective and time-saving manner. This paper proposes a new GA-Spectre model to design the dynamic comparator and successfully applies this model to optimize the dynamic comparator with a result of 72.61 ps of delay and 3.11 µW of power dissipation. Hence, the algorithm proves to be a promising solution to the optimal circuit’s parameters. Since the mentioned GA-Spectre architecture could also be applied to optimization problems of different circuits, it might be the driving force to transform the way analog circuit engineers work.