Reconfiguration Using Bio-Inspired Conduction Mode of Field-Effect Transistors toward the Creation of Recyclable Devices

Abstract

A bio-inspired conduction mode in silicon-based field-effect transistors was studied here using the frequency-dependent reconfiguration principle in a size-reduced circuit architecture. Analog circuits comprising neuromorphic and reconfigurable behavior were analyzed across their physical quantities using a set of equations governing circuit performance. Practical examples were built, analyzed, and discussed from a phenomenological viewpoint. Upon exploiting their reconfiguration properties when semiconductor devices and passive components are interconnected, novel operating principles might inspire optimized signal processing and manufacturing facilities to design circular device-based complex systems.

1. Introduction

To challenge the semiconductor industry’s trend toward focusing on the shrinkage of CMOS transistors, where run-time faults occur during storing and processing into digital circuit architectures because many complex operations are computed [1], it is desirable to find the best way to divide large networks into smaller simple circuits, similar to biological circuits. For example, a good compromise between the shortcomings of digital processing and the benefits of analog neuromorphic architecture is needed to devise a reconfigurable circuit capable of simulating digital signal processing and neuron ionic activity in real time. It is well known that analog circuits can model biological activity even faster than it happens in real life, use fewer active and passive components to operate at a lower voltage, to model the synapses that are associated with artificial neurons, which are always in flux and constantly being reinforced or phased out to mimic the way human neurons behave [2,3,4].

Scientific evidence from modern events in the context of the COVID-19 pandemic has perturbed the lives of humans, leading us to question where our civilization is headed, allowing us to promote sustainable engineering in the electronics industry, where the interrelation of environmental, social, and economic dimensions must force further research on innovative modes of production and their impact on the environment and human health worldwide [5].

The growing demand for consumer electronics has led to unsustainable amounts of waste products and adverse impacts, which are not expected to change in the coming decades. However, at present, several publications have emphasized waste reduction and recycling policies [6,7]: (1) policymakers are actively encouraging the repair and life extension of electrical and electronic equipment; (2) responsible recycling when consumers return electronic products to the point of purchase; (3) pro-active approaches to delaying the consignment of waste products to landfills through resource-efficient manufacturing; (4) recycling to decrease demand for new metal production and to reduce carbon footprints; and (5) using recyclable materials and understanding their breakdown mechanisms to avoid waste.

The scope that the circularity approach must address is still unclear; however, taking advantage of a bio-inspired conduction mode in field-effect transistors could be crucial to solving existing challenges in the electronics industry, where in recent years it has been confirmed that CMOS technology is flexible enough to integrate complex digital systems that can contain many millions of small elementary circuits constructed using a reduced number of transistors. However, the complexity of these systems could be lessened by seeking and applying unusual conduction modes, which might play an important role in preventing new waste products in the circuits’ premature end-of-life stage if the repair/reuse and remanufacture of any application-specific industry-scale building blocks are incorporated. Hence, this work studies a bio-inspired conduction mode in field-effect transistors to suggest future directions for designing recyclable devices as part of a sustainable cycle. Possibilities for circuit architecture, including two circuit properties—neuron-like spike generation and reconfigurable signal processing—will be detailed in Section 2. Practical examples using two field-effect transistor types will be covered in Section 3. Finally, conclusions about this research are presented in Section 4.

2. Circuit Architecture

Due to the biological brain’s ability to quickly process large quantities of simultaneous information in a small package, which is the result of the coordinated action of many highly interconnected brain areas, previous research has focused on modeling those individual parts of the human brain, which is composed of 100 billon nerve cells called neurons, whose biological activity consists of talking to each other by means of dendrites and axons, which transmit electrical impulses, fire biological neurons, and center integration and spike generation from one neuron to another [8].

Because bioprocessing in the nervous system occurs at the junctions between neurons (known as synapses), the learning of new information depends on how closely any two neurons are linked. The circuits depicted in Figure 1 contain one inductor series connected to the active device, which can follow the non-linear ionic activity of a neuron, such as a biological neuron. Meanwhile, Neuron 1, through the external stimulus of the region known as the soma, is equivalent to the inductor and can send a signal down the axon, which is equivalent to the junction capacity of each active device, creating a synapse with Neuron 2, where integration and spike generation at the output of each active device can be collected as electrical impulses, as shown in Figure 1 [9]. Here, the equivalent-circuit linear functions of two active devices [10,11], namely, a field-effect transistor (FET) and a metal oxide semiconductor field-effect transistor (MOSFET), will follow p–n-junction-like behavior at the gate–source junction, being roughly analogous to a physical circuit quantity arranged into state equations governing circuit performance, as explained below:

2.1. Circuit Based on FET

It is instructive to analyze the current paths into two basic operation modes to give a qualitative idea of the phenomenological response involved in operating the circuit architecture of Figure 1. The detailed description of each mode is given below:

Mode 1: At the beginning, the gate–source junction is forward biasing across the series inductor connected at V_IN, where electrons are injected from the n region into the p⁺ regions, and holes are injected from the p⁺ regions into the n region, which allows the inductor to store enough energy. The gate–source capacitance, C_GS, initially gets charged through the p⁺–n junction, but channel formation is missing, as shown in Figure 2a.

The equation governing this operation mode is

$${\mathrm{V}}_{\mathrm{IN}}=\mathrm{L}\frac{\mathrm{d}{\mathrm{I}}_{\mathrm{G}}}{\mathrm{dt}}=\mathrm{L}\frac{{\mathrm{d}}^2{\mathrm{Q}}_{\mathrm{G}}}{{\mathrm{dt}}^2},$$

(1)

Mode 2: When the polarity of V_IN is inverted and the gate–source junction is reverse biasing, two conduction stages happen. (a) Due to the reverse energy stored in the inductor, C_GS becomes oppositely charged until it begins its discharge action across gate–source resistance, r_GS. Accordingly, transient channel resistance along the source–drain junction occurs, equivalent to an ON-state. (b) Due to the reduced charge-handling capacity in C_GS and the higher inductor voltage of V_L compared with V_IN, the C_GS becomes forward charged while it exchanges energy with the inductor, until it begins its discharge action across r_GS. Thus, conduction along the source–drain junction will be missing, which is equivalent to an OFF-state. As such, these conduction states together assemble an electrical impulse, which is dependent on the fluctuation of the electric field into the n region (channel length), as shown in Figure 2b. The equations governing this operation mode are

$$\frac{{\mathrm{Q}}_{\mathrm{G}}}{{\mathrm{C}}_{\mathrm{G}\mathrm{S}}}+{\mathsf{\Phi }}_{\mathrm{B}}=\mathrm{L}\frac{{\mathrm{d}}^2{\mathrm{Q}}_{\mathrm{G}}}{{\mathrm{dt}}^2},$$

(2)

$$\frac{{\mathrm{dQ}}_{\mathrm{G}}}{\mathrm{d}\mathrm{t}}=\frac{{\mathrm{Q}}_{\mathrm{G}}}{{{\mathrm{r}}_{\mathrm{G}\mathrm{S}}\mathrm{C}}_{\mathrm{G}\mathrm{S}}},$$

(3)

2.2. Circuit Based on MOSFET

The phenomenological response predicted to serve as a mutual description between the physical structure and equivalent circuit through current paths is related to the two basic operating modes in the circuit architecture of Figure 1. Detailed descriptions of each mode are given below:

Mode 1: At the beginning, the gate–source junction is forward biasing across the series inductor connected at V_IN, where two transitory conduction stages occur. (a) Bulk charge distribution can be induced into the p region when channel capacitance, C_CH, is charged through channel resistance, r_CH, via electric field action along the source–drain junction. (b) Due to the reduced charge-handling capacity in C_CH and reverse energy stored in the inductor, a decrease in the charge toward the gate–source junction is observed when the gate–source capacitance, C_GS, is charged through gate–source resistance, r_GS. Hence, the resistance along the source–drain junction obeys the charge fluctuation at low-level injection, where two equivalent states, the so-called ON-state and OFF-state, are achieved. These states assemble an electrical impulse, as shown in Figure 3. The equations governing this operation mode are

$$\mathrm{L}\frac{{\mathrm{d}}^2{\mathrm{Q}}_{\mathrm{G}1}}{{\mathrm{dt}}^2}+{\mathrm{r}}_{\mathrm{C}\mathrm{H}}\frac{\mathrm{d}{\mathrm{Q}}_{\mathrm{G}1}}{\mathrm{d}\mathrm{t}}+\frac{{\mathrm{Q}}_{\mathrm{G}1}}{{\mathrm{C}}_{\mathrm{C}\mathrm{H}}}={\mathrm{V}}_{\mathrm{I}\mathrm{N}},$$

(4)

$$\frac{{\mathrm{Q}}_{\mathrm{G}1}}{{\mathrm{C}}_{\mathrm{G}\mathrm{S}}}+{\mathrm{r}}_{\mathrm{G}\mathrm{S}}\frac{{\mathrm{d}\mathrm{Q}}_{\mathrm{G}1}}{\mathrm{d}\mathrm{t}}={\mathrm{V}}_{\mathrm{T}},$$

(5)

Mode 2: Due to the reduced reverse energy stored in the series inductor and charge stored along the source–drain junction during Mode 1, three conduction stages can arise: (a) Surface charge can be distributed at high-level injection to induce the n-channel, when C_GS is charged across r_GS. (b) The C_CH is weakly charged across channel resistance, r_CH, while the surface charge quickly begins to be deficient as a function of the reduced charge-handling capacity in C_CH, which is distributed toward the interface of the n⁺–p junction. (c) The inductor exchanges residual energy with C_CH through r_CH and is empty when a blocking state in the n⁺–p junction is attained. Accordingly, the charge distribution along the n-channel length obeys the charge fluctuation via a higher electric field condition, where two equivalent states, the so-called ON-state and OFF-state, assemble a different electrical impulse, as shown in Figure 4. The equations governing this operation mode are

$$\mathrm{L}\frac{{\mathrm{d}}^2{\mathrm{Q}}_{\mathrm{G}2}}{{\mathrm{dt}}^2}+{\mathrm{r}}_{\mathrm{G}\mathrm{S}}\frac{\mathrm{d}{\mathrm{Q}}_{\mathrm{G}2}}{\mathrm{d}\mathrm{t}}+\frac{{\mathrm{Q}}_{\mathrm{G}2}}{{\mathrm{C}}_{\mathrm{G}\mathrm{S}}}=-\mathrm{L}\frac{{\mathrm{d}}^2{\mathrm{Q}}_{\mathrm{G}1}}{{\mathrm{d}\mathrm{t}}^2},$$

(6)

$$\frac{{\mathrm{Q}}_{\mathrm{G}2}}{{\mathrm{C}}_{\mathrm{C}\mathrm{H}}}+{\mathrm{r}}_{\mathrm{C}\mathrm{H}}\frac{{\mathrm{d}\mathrm{Q}}_{\mathrm{G}2}}{\mathrm{d}\mathrm{t}}={\mathsf{\Phi }}_{\mathrm{S}},$$

(7)

The empirical discussion on the p–n junction action in each FET or MOSFET device as a function of the physical parameters, as well as expected solutions for earlier equations governing each operating mode, are specified in Appendix A.

3. Circular Devices

Actions for the development of electrical and electronic equipment toward more energy-efficient and green manufacturing routes must follow, for example, a paradigm change in design for passive components (e.g., resistors, capacitors, and inductors) and nonlinear active devices (e.g., diodes, transistors, and memristors). Thus, bridges of collaboration among society, academia, and industry are needed to transform each stage into a circular scenario, as projected in Figure 5. Here, it is essential to describe four aspects in which a sustainable cycle might succeed:

• Domestic and industrial waste is an issue that requires urgent attention and adversely impacts economic, environmental, and health factors. Manufacturers of printed circuit boards (PCBs) and the silicon semiconductor industry have so far followed a traditional linear economy value chain, leading to high volumes of waste production and loss of value at the end of life. For example, to replace the traditional tracks on PCBs, conductive materials must possess stability and electrical functionality with existing materials, and to replace the existing semiconductor devices (SDs), their charge transport properties depend on reconfigurable charge carrier mobility and higher thermal stability. Therefore, cellulose, as one of the attractive substrate materials because of its flexibility, thermal stability, and simple synthesis technique, can be designed for easier dismantling opportunities, enabling electronics innovation [12,13], while next-generation SDs can be created with biodegradable materials, such as silicon nanomembranes (Si-NM), metal oxides, and conducting polymers [14,15];
• Novel business models can be created through the circulation of new knowledge, leading to innovative technical processes, products, and services focused on initiatives for repair/reuse and redesign into circular economy objectives, using fewer resources and closed-loop material flow, and decreasing negative environmental impacts by including remanufacturing, maintenance, recycling planning, and avoiding the use and generation of hazardous substances. New business models highlight a transition to more sustainable practices regarding waste products that are currently eluding decision makers. Products can be maintained for as long as possible, but before they fail and have to be disposed of, they must be rigorously tested and potentially certified for performance, safety, and reliability for their transformation and reintroduction within a sustainable cycle [16,17];
• Education must highlight the impacts of recovery/recycling approaches on circular vision at every level, offering learning activities from pre-university science to university engineering and technology courses. There are many ways to engage education institutions by creating syllabi focused on recycling at a discrete-component level, where student’s creativity could be considered, taking into account the traditional and uncommon properties of materials, as well as the atypical characteristics of the passive and active devices. Thus, the courses can be planned, for example, using well-known basic circuit theorems that were often conceived decades ago but now have additional mathematical models interrelated with the physics of semiconductors. Moreover, simulation software as design tools must allow the building of next-generation circuit architectures within several innovative functions combined with few components [18,19];
• Due to the specialized nature of the materials, those used in advanced integrated circuits (e.g., digital processors), such as gold, platinum, and palladium, are much less abundant and used sparsely, while copper, a more abundant and densely used material, is categorized as a source of cancerous diseases, and has the largest environmental footprint together with tin, lead, and mercury in terms of human toxicity impact [20]. Accordingly, the electronics industry must solve challenges, such as materials compatibility, thermal stability, unstressed current-handling capacity, and scalable circuit solutions. Thus, the recovery of waste materials (e.g., silicon, iron, copper, and aluminum) can be expected to upgrade the circularity stages by exploiting a material’s unusual properties (e.g., reconfiguration, refurbishment, and reuse) to satisfy the need for an extended product lifecycle and long-term waste mitigation [21,22].

There are practical examples of circular devices using the n-channel FET (type 2N5457; Fairchild Semiconductor) and the n-channel MOSFET (type 2N7000; ON Semiconductor), with an inductor L = 750 μH of 450 turns built using recycled magnetic wire AWG # 32 from out-of-date magnetic components, and bulk winding on a square base with a length of 10 mm and cross-sectional area of 0.25 cm² was experienced. For biasing purposes, resistors R₁ = 2.2 kΩ and R₂ = 47 kΩ were of ¼ W at 5%, and to avoid switching noise due to the power supply current pulses flowing through parasitic inductors, typical Mn-Zn-Graphite batteries were connected in series at each circuit architecture.

To characterize the performance of each circuit architecture, we generated and extracted the voltage waveforms using a function generator (Matrix, MFG-8250A) and digital storage oscilloscope (Tektronix, TDS1012C), respectively. Based on the principles detailed in the foregoing section, the tested current–voltage characteristics from the manufacturer’s datasheet for each silicon-based active device have been correlated in accordance with the physical semiconductor models [23,24]. Therefore, semiconductor parameters were computed, and the values are summarized in

Table 1. Physical parameters of the 2N5457 transistor.

Static	Nomenclature	Value
donor concentration	ND	5 × 1015 cm−3
acceptor concentration	NA	2 × 1017 cm−3
dielectric constant for Si	KSi	11.7
channel transconductance	gm	6.5 × 10−4 mhos
thickness of channel	d	2 μm
effective channel length	L	20 μm
channel width	Z	5000 μm
carrier mobility	μn	12.95 cm2V−1s−1
built-in potential	ΦB	0.7548 eV
Dynamic	Nomenclature	Value
input voltage	VIN	2 V
gate–source resistance	rGS	11.36 Ω
gate–source capacitance	CGS	8.80 pF
cut-off frequency	f	1 MHz

and

Table 2. Physical parameters of the 2N7000 transistor.

Static	Nomenclature	Value
donor concentration	ND	5 × 1017 cm−3
acceptor concentration	NA	2 × 1015 cm−3
dielectric constant for Si	KSi	11.7
dielectric constant for SiO2	KOX	3.9
thickness of the SiO2	XOX	100 nm
channel transconductance	gm	2 × 10−3 mhos
effective channel length	L	20 μm
channel width	Z	2000 μm
carrier mobility	μn	400 cm2V−1s−1
surface potential	ΦS	1.5097 eV
Dynamic	Nomenclature	Value
input voltage	VIN	5 V
turn-on voltage	VT	0.4257 V
gate–source resistance	rGS	0.1032 Ω
gate–source capacitance	CGS	219.6 pF
channel resistance	rCH	125 Ω
channel capacitance	CCH	9.29 pF
cut-off frequency	f	40 MHz

for 2N5457 and 2N7000, respectively. Next, physical behavior under the biasing conditions established for the practical examples is discussed:

3.1. Reconfigurable Conduction Mode in FET

Figure 6a shows how reconfigurable behavior can occur in the circuit architecture when operating at 200 kHz, which is caused by the negative square-wave pulse depending on the amplitude of three voltages, V_IN. Their physical operating principle, whose experimental waveforms are displayed in Figure 6b–d, can be discussed as follows: At V_IN = 200 mV, the gate and source regions on the FET (see Figure 3) operate through the wide space-charge region, which is similar to the p⁺–n junction, where an adequate electric field is produced after a certain number of charge carries (electrons and holes) have flowed. Thus, this behavior corresponds with a logic circuit. At V_IN = 1 V, the distribution of the charge carries within the p⁺–n junction through the narrow space-charge region, where a reduced electric field allows their transient diffusion into the n-channel’s length, whose behavior is equivalent to the neuron-like spikes that are generated in neuromorphic circuits. At V_IN = 2.5 V, the transient diffusion begins to be negligible near the p⁺–n junction, which is just below the lowly doped n-region, meaning that decreasing neuron-like activity in a reduced space-charge region under a lower electric field is attained.

3.2. Reconfigurable Conduction Mode in MOSFET

To confirm that a MOSFET can operate in an unusual conduction mode, the circuit architecture in Figure 7a was built. Figure 7b–d show the resulting output waveforms, V_OUT, when a square-wave pulse with V_IN = 5.6 V corresponding to a TTL level was applied. Because the distribution of the charge carried in the n-channel depends on the bias condition in the p–n⁺ junction and the space-charge capacitance at the gate–source junction, the circuit must operate at a variable frequency, as follows:

At f = 160 kHz, charge accumulation in the gate–source junction and low-level injection force a transient diffusion of the carries along the n-channel, which means that neuron-like spikes are generated at the zero square-wave pulse. At f = 175 kHz, the saturation of the space-charge capacitance and high-level injection due to a constant electric field along the n-channel occurs at positive and zero square-wave pulses, resulting in a correspondingly higher number of neuron-like spikes during the transient diffusion phenomena. At f = 250 kHz, the velocity of the charge carried along the n-channel is higher than the velocity for the exchange of energy between the inductor and space-charge capacitance arising in the lowly doped p-region [25]; therefore, charge accumulation through this p–n⁺ junction allows a delayed conduction, which obeys the well-known logic circuit performance [26].

As a result, the synthesis of neuron-like spikes has already taken place during the square-wave pulse transfer across the inductor by the time the signal reaches each space-charge capacitance to exchange energy, such as the nonlinear LC circuit at the resonance condition [27,28], integrating over the drain–source junction until the spikes are generated, as shown in Figure 6 and Figure 7, respectively.

The neuromorphic behavior of the underlying hardware is divided up between hardware that processes similar to how the body of a neuron functions and hardware that processes the way that axons work, and practical examples have focused on building biological activity using simple circuit architectures operating at higher voltage (>1 volts) in comparison to around 0.1 volts in human neurons, which means that electrical impulses can be generated and transmitted using flexible power consumption [29,30].

Likewise, with increasing amplitude or frequency in the input square-wave pulse, the transferred signal across the FET or MOSFET is always at the ready, responding upon receiving a stimulus, similar to how logic circuits in computer processors execute functions in discrete time steps.

3.3. Validation of the Reconfiguration Principle

The small-signal equivalent circuit models suggested in Figure 1 consider intrinsic elements mainly affected by the conduction of current drain and gate–source voltage_, as well as those limited in response below the cut-off frequency, whereas extrinsic elements extracted from circuits continuously scaling down the gate length, which leads to increased operation frequency, have made FET devices a critical technology in the design of monolithic microwave integrated circuits (MMICs), where parasitic resistances, capacitances, and inductances that are often bias-independent are included to model the coupling effects and substrate losses, and the distributed effect at the gate channel and distributed the resistances are mainly caused by the lightly doped extensions of the drain and source diffusions, and are frequency-dependent [31].

The noise sources that are generated by the basic mechanisms responsible for the anomalous current flows can be correlated with the transient conduction mode described in Appendix A to provide insight into how noise would affect the bio-inspired conduction mode in the practical examples provided by Figure 6 and Figure 7 as a function of physical quantities. To discover the interaction of the charge carriers (electrons and holes) from the surface region with the surface states and the bulk in the semiconductor, the shot noise can be produced by transient changes in drift and diffusion flows in the case of an FET, determined by the density of impurities N_TT ~ 10¹⁰ cm⁻³ and/or defect centers within the depletion n-region, whereas the occupation of interface states would be determined by effective surface-state density N_SS ~ 10¹² cm⁻² in the case of a MOSFET near the dielectric region, which can result in fluctuations in the channel conduction, giving rise to a flicker noise [32,33].

Because the equivalent circuits in Figure 1 link the device’s physical structure to its circuit behavior, it allows us to predict the valid performance of the circuits at the proposed operating conditions; therefore, based on the physical quantities in

Table A1. Estimated physical quantities under transient conduction mode.

Device	${\mathbf{N}}_{\mathbf{D}}^{\mathbf{*}}$ (cm−3)	${\mathbf{N}}_{\mathbf{A}}^{\mathbf{*}}$ (cm−3)	${\mathbf{Q}}_{\mathbf{F}}$ (A-sec)	${\mathbf{Q}}_{\mathbf{R}}$ (A-sec)
2N5457	3.43 × 1013	1.37 × 1015	~5 × 10−11	~6 × 10−12
2N7000	4.96 × 1013	1.98 × 1011	~2 × 10−9	~1.5 × 10−10
	2.75 × 1013	1.11 × 1011	~5 × 10−10	~2 × 10−11

, as described in Appendix A, the dominant operation mode for the practical examples corresponds to the nonlinear transient conduction, which satisfies at ${\mathrm{N}}_{\mathrm{D}}^{\mathrm{*}}$, ${\mathrm{N}}_{\mathrm{A}}^{\mathrm{*}}$ ≥ N_TT in the case of an FET and ${\mathrm{N}}_{\mathrm{A}}^{\mathrm{*}}$X_OX, ${\mathrm{N}}_{\mathrm{D}}^{\mathrm{*}}$X_OX ≥ N_SS in the case of a MOSFET, attaining a reconfigurable behavior at room temperature during the reduced flow of dynamic charge ${\mathrm{Q}}_{\mathrm{F}}\left(\mathrm{t}\right)$ and ${\mathrm{Q}}_{\mathrm{R}}\left(0\right)$ at medium-frequency range (<1 MHz), where input parasitic resistances and capacitances might be negligible in comparison with the dynamic physical parameters of Table 1 and Table 2, as well as the inductor L > > gate–source parasitic inductances.

4. Conclusions

This research focused on frequency-dependent reconfiguration based on a bio-inspired conduction mode, analyzing its considerable dynamic properties, such as an exchange of energy between the inductor and the space-charge capacitances of an FET or MOSFET device to enable nonlinear transient conduction restricted by noise sources. As a result of applying intuition, physical analysis, and basic experiments, circuit architectures optimized for signal processing and size for easier dismantling and an extended time of operation have been proposed and validated in this work to overcome the practical circuits in the design of monolithic high-frequency integrated circuits using emerging materials and semiconductor technologies to achieve scalable solutions within a circularity-based paradigm change to support novel and feasible waste management processes in the electronics industry over the next few years.