# Broadband Modeling and Simulation Strategy for Conducted Emissions of Power Electronic Systems Up to 400 MHz

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## Abstract

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## 1. Introduction

^{®}[12]. This software uses vector fitting to obtain a circuit representation of the computed structure, which is then solved in a transient simulation. With the known currents and voltages at the circuit ports, the radiated fields around the 3D structure can be computed. The authors use a SPICE model of the switches and investigate resonances in the radiated fields up to 1 GHz.

- Which parts of the system are best characterized by solving Maxwell’s Equations, and which method must be to solve them?
- Which parts of the system must be characterized by measurement?
- What is needed to efficiently generate a transistor model, and what are its accuracy limits?
- With which method are all the above-mentioned components combined into a system simulation that predicts emissions?

## 2. Measurement Setup

#### 2.1. Device under Test (DUT)

^{TM}IGOT60R070D1 by Infineon [17]. The Gate signal is generated with an external waveform generator and processed on the board with an auxiliary gate driving circuit. Two DC link capacitors [18] of nominally 1 $\mathsf{\mu}$F (designated ${C}_{100}$, ${C}_{101}$) are connected between the DC+ and DC− nodes. The load is an RL series circuit attached between the switched node and DC+. It is composed of a power resistor with aluminum housing and a high current power inductor with nominal values of 10 $\mathsf{\Omega}$ and 10 $\mathsf{\mu}$H and approximately 15 cm wire on both ends, see Figure 3.

#### 2.2. Conducted Emission (CE) Measurement Setup

#### 2.3. Differential and Common Mode Impedance of the Load

## 3. Modeling

#### 3.1. Three-Dimensional EM Model of PCB and Measurement Setup

#### 3.2. Component Modeling

#### 3.2.1. Face Lumped Elements

#### 3.2.2. Face Lumped Ports

#### 3.3. EM Solver and Computational Effort

#### 3.4. S-Parameter Model

#### 3.5. Vector Fitting

^{−3}is recommended by the CST support). However, this accuracy is only maintained in the circuit simulation if the same impedances are used as loads in the time domain simulation. If the component models attached to the vector-fitted SPICE model have a frequency dependent impedance that significantly deviates from the impedance that was used in the fitting process, the fitting error might be amplified and lead to inaccurate results in the transient circuit simulation. Our tests have shown that this amplification is more probable with an increasing number of ports.

#### 3.6. Assembly

#### 3.6.1. Transistor Model

#### 3.6.2. DC Link Capacitors

#### 3.6.3. LISN Model

#### 3.6.4. Load Model

#### 3.7. Time Domain Simulation

#### 3.8. Summary Workflow

- Import the odb++ database of the PCB into the CST Studio Suite.
- Define material properties in the 3D model.

- Define surface lumped elements for all external components which:
- Are known to exhibit an accurate and reliable behavior;
- Do not experience fast switching load currents;

and define their electrical R, L, and C behavior. - Define surface lumped ports for all external components that experience fast switching load currents.
- Run 3D FEM simulations to obtain the S-Parameters of the defined ports and export the results into a S-Parameter model (Touchstone file). The usage of a direct solver is recommended to increase computational efficiency.
- Validate the S-Parameter model using AC simulations.
- Generate a SPICE model from the S-Parameter model by using vector fitting and monitor the fitting error.
- Develop a suitable equivalent circuit model of the transistors, capacitors, and LISN.
- Characterize the load in terms of differential mode and common mode measurements and extract:
- A simplified equivalent circuit RLC load model; or
- A vector-fitted load model.

- Connect models of the transistor, capacitor, LISN, and load to the vector-fitted SPICE model of the PCB and run a transient simulation with the desired supply voltage and control signals.
- Apply a suitable EMI receiver model to the transient simulation results to obtain your conducted EMC behavior.

## 4. Results

## 5. Discussion

## 6. Conclusions

- The accuracy of the common mode load measurements is enhanced;
- The transistor model includes voltage-dependent effects of the drain-source resistor ${R}_{p}$.

## Author Contributions

## Funding

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## References

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**Figure 2.**Schematic view of the conducted emission test setup. Parasitic coupling capacitances between PCB, load, and underlying GND plane are displayed in red. The EMI receiver is connected to the output of the positive supply LISN P. The unused output of LISN M is terminated by 50 $\mathsf{\Omega}$.

**Figure 3.**Measurement concept to obtain DM and CM load impedance for circuit simulations, reflecting the setup of interest. The CM measurement captures the overall coupling capacitance towards the common ground plane.

**Figure 4.**Time domain signals captured with an oscilloscope while the DUT was supplied with 10 V. The differential voltage at the load is measured between DC+ and the switched node.

**Figure 5.**Photo of the conducted emission measurement setup. The EMI receiver was connected to the output of the positive supply LISN P. Common GND is the metallic plane. The unused output of LISN M was terminated by 50 $\mathsf{\Omega}$. Wires between DUT PCB and LISNs were 30 cm long.

**Figure 6.**(

**a**) Measurement of the load’s series impedance with a 2-port VNA. (

**b**) Measurement of the coupling capacitance between load and GND plane to obtain the value of ${C}_{\mathrm{CM},\mathrm{load}}$. Here, only one port of the VNA is used, with both wires soldered to the inner conductor of the SMA connector. Reference is the metal fixture connected to the GND plane.

**Figure 7.**(

**a**,

**b**) are the top and bottom views of the 3D model of the test PCB. The 3D geometry of the PCB is imported from odb++ data files. (

**c**) detailed stackup of the test PCB using 4 metal layers.

**Figure 8.**Three-dimensional model of the complete test setup including the test PCB, the metal reference table with a distance of $H\phantom{\rule{3.33333pt}{0ex}}=\phantom{\rule{3.33333pt}{0ex}}$50 mm, and the supply cables. The LISN networks are connected to LISN M/P, and the load is connected between Load out and Loadp. (

**a**) top view; (

**b**) front view.

**Figure 9.**(

**a**,

**b**) Face lumped elements to model the ideal electrical behavior of resistors, inductors, and capacitors which are not part of the halfbridge circuit. (

**c**) Face lumped ports to investigate the impact of the capacitors between DC+ and DC− on the EMC’s behavior. (

**d**) Face lumped ports to investigate the impact of the transistors on the EMC behavior.

**Figure 11.**Block diagram for the Validation of the S-Parameter model by using an AC analysis. (

**a**) Drain and Source of HS- and LS-switch are shorted and other ports are left open. (

**b**) Capacitors ${C}_{100}$ and ${C}_{101}$ are connected and the other ports are left open.

**Figure 12.**Validation of S-Parameter model by using an AC analysis. (

**a**) Input impedance observed between LISN P and LISN M when Drain and Source of HS- and LS-switch are shorted (see Figure 11a). (

**b**) Input impedance observed between LISN P and LISN M when the capacitors ${C}_{100}$ and ${C}_{101}$ are connected and the other ports are left open (see Figure 11b).

**Figure 15.**Top-level circuit schematic for the system simulation including the vector-fitted PCB model discussed in Section 3.5 and component models for transistors, capacitors, LISNs, and load.

**Figure 16.**Equivalent circuit model of the mounted transistor. The parameter values are comprised in Table 3.

**Figure 17.**Drain -Source voltage of the high side (HS) transistor (see Figure 15) with an ideal and smooth switching behavior.

**Figure 19.**Equivalent circuit model of the mounted capacitors. The parameter values are shown in Table 4.

**Figure 21.**(

**a**) Simulated and measured LISN impedance of port 1 (${Z}_{11}$). (

**b**) Comparison of simulated conducted emissions using the equivalent circuit (EC) LISN model from Figure 20 and a vector-fitted (VF) LISN model extracted from 3-port S-Parameter measurements of the LISN. Up to 350 MHz no difference between EC LISN model and VF LISN model can be observed.

**Figure 22.**Equivalent circuit model of the connected load. (

**a**) Simple RLC circuit model describing only the first parallel resonance and the CM capacitance towards the metal table. (

**b**) Equivalent circuit model generated from the DM measurement utilizing vector fitting. The parameter values are comprised in Table 6.

**Figure 24.**Simulated time domain signals of the assembly shown in Figure 15 with a supply voltage of 10 V. (

**a**) High side transistor gate voltage ${V}_{HS,\phantom{\rule{3.33333pt}{0ex}}gate}$, drain-source voltage ${V}_{HS,\phantom{\rule{3.33333pt}{0ex}}DS}$, and the positive supply line voltage ${V}_{DC+}$. (

**b**) Low side transistor gate voltage ${V}_{LS,\phantom{\rule{3.33333pt}{0ex}}gate}$ and drain-source voltage ${V}_{LS,\phantom{\rule{3.33333pt}{0ex}}DS}$. (

**c**) LISN P output voltage.

**Figure 25.**Comparison between measured and simulated conducted emissions with ${V}_{DC}$ = 10 V and ${V}_{DC}$ = 60 V. (

**a**,

**b**) Simplified RLC load model and ${R}_{p}$ = 0 $\mathsf{\Omega}$. (

**c**,

**d**) Simplified RLC load model and ${R}_{p}$ = 10 $\mathsf{\Omega}$.

**Figure 26.**Comparison between measured and simulated conducted emissions with ${V}_{DC}$ = 10 V and ${V}_{DC}$ = 60 V. (

**a**,

**b**) VF load model and ${R}_{p}$ = 0 $\mathsf{\Omega}$. (

**c**,

**d**) VF load model and ${R}_{p}$ = 10 $\mathsf{\Omega}$.

Material | Material Parameters |
---|---|

Copper | ${\sigma}_{cu}$ = $5.8e7\frac{S}{m}$ |

Core | ${\epsilon}_{{r}_{core}}$ = 4.4 |

Prepreg | ${\epsilon}_{{r}_{prepreg}}$ = 3.9 |

Solder mask | ${\epsilon}_{{r}_{m}}$ = 3.5 |

**Table 2.**Computational effort of the 3D numerical simulations using an Intel Xeon E5-2680V2 (10 × 2.8 GHz) and a peak memory usage of 18.9 GB. The results were obtained by using FEM in the frequency domain with tetrahedral mesh cells.

Mesh Cells | Mesh Generation Time | Computational Time | Total Simulation Time |
---|---|---|---|

(4 Mesh Adaption Runs) | (One Frequency Sample) | ||

588,687 | 30 min | approx 4 min | 1 h 17 min |

**Table 3.**Parameters of the transistor model depicted in Figure 16. Two different values for ${R}_{p}$ are considered to study their impact on the conducted emissions.

${\mathit{R}}_{\mathit{on}}$ | ${\mathit{C}}_{\mathit{p}}$ | ${\mathit{R}}_{\mathit{p}}$ | ${\mathit{D}}_{\mathit{p}}$ (${\mathit{R}}_{\mathit{on}}$) |
---|---|---|---|

70 m$\mathsf{\Omega}$ | 200 pF | 0 $\mathsf{\Omega}$ | 100 m$\mathsf{\Omega}$ |

10 $\mathsf{\Omega}$ |

${\mathit{C}}_{\mathit{C}}$ | ${\mathit{L}}_{\mathit{C}}$ (ESL) | ${\mathit{R}}_{\mathit{C}}$ (ESR) |
---|---|---|

0.55 $\mathsf{\mu}$F | 3 nH | 12 m$\mathsf{\Omega}$ |

${\mathit{L}}_{\mathit{lisn}}$ | ${\mathit{C}}_{\mathit{lisn}}$ | ${\mathit{R}}_{\mathit{lisn}}$ | ${\mathit{R}}_{\mathit{EMI}}$ |
---|---|---|---|

5 $\mathsf{\mu}$F | 100 nF | 1 k$\mathsf{\Omega}$ | 50 $\mathsf{\Omega}$ |

**Table 6.**Parameters of the load model depicted in Figure 22. The parameters ${R}_{load}$ and ${L}_{load}$ describe the connected resistor and inductor. The values for ${C}_{load}$, ${R}_{par}$, ${C}_{CM,RLCload}$, and ${C}_{CM,VFload}$ were extracted from DM and CM measurements to model the first parallel self-resonance of the inductor and the capacitive coupling towards the metal table.

${\mathit{R}}_{\mathit{load}}$ | ${\mathit{L}}_{\mathit{load}}$ | ${\mathit{C}}_{\mathit{load}}$ | ${\mathit{R}}_{\mathit{par}}$ | ${\mathit{C}}_{\mathit{CM},\phantom{\rule{3.33333pt}{0ex}}\mathit{RLC}\phantom{\rule{3.33333pt}{0ex}}\mathit{load}}$ | ${\mathit{C}}_{\mathit{CM},\phantom{\rule{3.33333pt}{0ex}}\mathit{VF}\phantom{\rule{3.33333pt}{0ex}}\mathit{load}}$ |
---|---|---|---|---|---|

10 $\mathsf{\Omega}$ | 12 $\mathsf{\mu}$H | 12 pF | 4000 $\mathsf{\Omega}$ | 3.6 pF | 14.4 pF |

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## Share and Cite

**MDPI and ACS Style**

Riener, C.; Hackl, H.; Hansen, J.; Barchanski, A.; Bauernfeind, T.; Pak, A.; Auinger, B. Broadband Modeling and Simulation Strategy for Conducted Emissions of Power Electronic Systems Up to 400 MHz. *Electronics* **2022**, *11*, 4217.
https://doi.org/10.3390/electronics11244217

**AMA Style**

Riener C, Hackl H, Hansen J, Barchanski A, Bauernfeind T, Pak A, Auinger B. Broadband Modeling and Simulation Strategy for Conducted Emissions of Power Electronic Systems Up to 400 MHz. *Electronics*. 2022; 11(24):4217.
https://doi.org/10.3390/electronics11244217

**Chicago/Turabian Style**

Riener, Christian, Herbert Hackl, Jan Hansen, Andreas Barchanski, Thomas Bauernfeind, Amin Pak, and Bernhard Auinger. 2022. "Broadband Modeling and Simulation Strategy for Conducted Emissions of Power Electronic Systems Up to 400 MHz" *Electronics* 11, no. 24: 4217.
https://doi.org/10.3390/electronics11244217