1. Introduction
Static random-access memory (SRAM) has been used in speed-sensitive cache due to its fast speed with low power. However, the conventional 6T-SRAM has encountered severe challenges in the implementation of large-capacity memory due to the large cell size (~80 F
2–120 F
2). A memory technology with comparable speed but higher density has been urged by the development of on-chip memory [
1,
2,
3]. In the past fifty years, various new devices have become the driving force for the development of the semiconductor industry. Specifically, in the past decade, semiconductor memory has driven an explosive growth in the industry. However, although the complementary metal–oxide–semiconductor (CMOS) logic devices have reached the physical limits by landing at the sub-5 nm technology node, the scaling of CMOS memory is still far behind due to technical difficulties. The use of the storage capacitor and its leakage in conventional memory technology is the major bottleneck impeding further down-scaling, which seriously hinder the further development of semiconductor memory [
4,
5,
6,
7,
8]. Therefore, a variety of new structures and new materials have been used to realize advanced semiconductor memories to overcome the shortcomings of traditional memory devices.
Band–band tunneling mechanisms have been extensively studied and applied to semiconductor devices with various structures, such as tunneling transistors. Studies have shown that devices based on this mechanism have the characteristics of fast speed and low power consumption, which makes it possible to study a semiconductor memory device based on the band–band tunneling mechanism. Compared with semiconductor memory based on the hot carrier injection mechanism and F-N tunneling mechanism, devices based on band-to-band tunneling have the advantages of low operation voltage and high speed [
9,
10,
11,
12,
13]. In order to meet the requirements of fast-speed, high-density, and low-power memory, alternative architectures have been considered as promising candidates to replace the current product. In this paper, we propose a design of a high-density memory (HDM) that utilizes tunneling current for program and erase operations based on the band-to-band tunneling effect.
The structure of the HDM was modified on the basis of traditional floating gate memory. Through simulation, we integrated the process of HDM and logic device, and we realized the device structure in the form of simulation. The simulation results of device characteristics and process steps were based on TCAD tools. Through the simulation results, we could clearly see that the band-to-band tunneling of electrons caused the tunneling current, and the tunneling occurred in the gate-drain overlap region when negative voltage was applied on the gate (VCG < 0) and positive voltage was applied on the drain (VD > 0). The simulation results indicated that the HDM has superior performance such as lower power consumption, high density (8 F2), higher speed (operation speed less than 5 ns), and enhanced anti-interference capability (~1 s), which indicate that the HDM may have potential application values in high-density SoC cache.
3. Simulation Results and Discussion
Based on the device structure described above, the electrical characteristics of this device were simulated in addition to the process simulation using the TCAD tools. The electrical simulation process simulates the program, erase, read, retention, and other characteristics of the device. These electrical simulation results showed that the device has excellent storage characteristics, making it a new solution for semiconductor memory in the future. The operation voltage and time of each electrode of the device are shown in
Table 1. The band-to-band generation rate was calculated during the simulation process by the Kane BTBT E2 model, which is expressed as follows [
14,
15,
16,
17]:
where G
BTBT is tunneling efficiency, and A
BTBT and B
BTBT are tunneling constants. The programming operation of HDM consists of two processes, namely write-0 and write-1. Through these two different write operations, the device has two different storage states of 0 and 1. The difference between write-0 and write-1 processes lies in the difference in V
D voltage in the two processes. Larger V
D voltage suggests higher programming efficiency under the same operating time, so different numbers of carriers are written into the floating gate. The equivalent circuit is shown in
Figure 3. During the program operation, the C
fg is charged by BTBT tunneling. The band-to-band tunneling rate profile of the write-1 operation and the bandgap during the write-1 operation are shown in
Figure 4a,b, respectively.
According to the simulation results, the tunneling rates of the write-1 and write-0 processes were 1.551 × 10
27 cm
−3s
−1 and 4.812 × 10
28 cm
−3s
−1, respectively. This means that during the write-1 process, more carriers were written into the floating gate. Such tunneling follows the mechanism of band-to-band tunneling, and it occurred in the region of the tunneling window (shown in
Figure 1) with V
CG = −1.5 V and V
D = 1.2 V. In this process, the energy band is stretched by the vertical electric field induced by V
CG. Under the horizontal electric field formed by V
D, the tunneling electrons flow to the drain, which causes the rise in FG potential. The write-1 and write-0 processes induce two different FG potentials so that during the read operation, we can obtain two different currents. As no vertical electric field is stretching the energy band, the bandgap broadens during the hold operation and tunneling is not likely to occur for the electrons. Under the application of the horizontal electric field, the carriers are trapped in the floating gate, preserving the information in a long-term manner. The length of the retention time is directly related to the size of the holding voltage, and the storage time of the information can be changed by changing the size of the retention voltage.
Figure 4c,d show the normalized tunneling current and FG potential curves of the HDM extracted from the second cycle because the currents are more stable and reproducible from our previous simulation experience. One operation period consists of the erase, retention, write-0, write-1, and read steps, as shown in
Figure 4c,d. The operation voltages of the source and substrate were 0 V during the operation period, and the V
D and V
CG changed along with different operations. The operation time of each step was 5 ns. The simulation results showed that the device can achieve high-speed and continuous voltage operation, and has excellent storage performance and reliability. Compared with the traditional floating-gate semiconductor memory device, the device has a lower operating voltage and a faster operating speed, and the information retention time can be adjusted by tuning the retention voltage, which enables both volatile and nonvolatile memory capabilities in the device. In addition, compared with traditional dynamic random-access memory, this device has a faster speed, longer retention time (>1 s), and no capacitance bottleneck, which makes this device promising for future stand-alone and on-chip memory applications.
The change in drain current (I
D) during the second operation period is shown in
Figure 4c. The CG voltage of the write-0 operation was the same as that of write-1, but the drain voltage of the write-1 operation was twice as high as that of write-0, resulting in the different amounts of tunneling electrons during the write operation. As discussed above, a different threshold voltage shift was observed with the change in FG potential. A different read current was obtained when the same read voltage was applied for read-0 and read-1 operations. The difference between the currents of read-0 and read-1 was larger than 2 μA (0.74 μA and 3.12 μA, respectively), which is sufficiently distinguishable. Besides, the leakage was lower than 10
−12 A of I
D during the hold step, which indicates that the device is reliable in the operation period.
Figure 4d shows the change in FG potential during the second operation period. The erase voltages were V
CG = 1.2 V and V
D = 0.6 V. The potential of FG decreased as expected due to the effect of the vertical electric field. The erase operation made the device return to the initial state. The write-1 voltages were V
CG = −1.5 V and V
D = 1.2 V, and the write-1 voltages were V
CG = −1.5 V and V
D = 0.6 V. The FG potential increased during the write-0 and write-1 operations due to the band-to-band tunneling, and the charge was stored into the FG, which will change the potential of the FG. The FG potentials were 0.02 V and 0.10 V after the write-0 and write-1 operations, respectively. The different FG potential resulted in the difference in V
th during the read operation. As a result, we can obtain the read currents mentioned above, and the state “0” and state “1” can be distinguished by checking and comparing the read current. The change in the FG potential during the second operation period was consistent with I
D, which shows that the electrical performance of the device is very reliable.
During the write-0 and write-1 operations, the variation in FG potential is shown in
Figure 5a. With different write-0 and write-1 voltages (V
D = 0.6 V and 1.2 V, respectively, and higher programming efficiency under the condition of large V
D), the different amounts of charges are stored in the FG, so that the information of “0” and “1” can be established. The retention characteristic curve is shown in
Figure 5b. State-0 and state-1 profiles are separately saved after write-0 and write-1 operations for further simulation. The operation voltages of retention characterization were V
CG = 0 V and V
D = 0.6 V. According to the simulation results, the retention time of state-0 and state-1 can reach up to ~1 s, which means the device does not have to be refreshed frequently. Due to the existence of the tunneling window region, a leakage current from the FG to drain always exists, and the FG potential and the drain potential are slowly consistent during the standby step. The increment in standby time of the HDM can be performed by altering V
D, which can affect the volatile and nonvolatile properties of the device. Therefore, the long retention time can be obtained by increasing the hold voltage V
D if necessary.
The disturbance persistence capability is an important property of a memory array. As the array operation of the HDM is page-operated, the disturbance of the word line voltage (V
CG) can be ignored, while all disturbance is attributed by the bit line voltage (V
D). Moreover, the write-0 and write-1 operations share the same programming mechanism of varying V
D. In this work, four types of crosstalk mechanisms were presented, and the crosstalk performance of the HDM is shown in
Figure 5c,d. The second operation cycle was used for crosstalk calculation, which is also consistent with previous studies. The state-0 and state-1 profiles were loaded to carry out the simulation by TCAD. The disturb time of state-0 and state-1 V
D-write-1 disturb remained ~1 s, as shown in
Figure 5c, when disturb voltages were V
CG = −1.5 V and V
D = 1.2 V. The operation time of the write process was 5 ns, which means the memory array can be written ~10
8 times. The disturb voltages of V
D-read disturb were V
CG = 0.6 V and V
D = 1.2 V, and the state-0 and state-1 V
D-read disturb remained ~1 s, as shown in
Figure 5d, which indicates that the memory array can be executed by the read operation for ~10
8 times continuously. The simulation results of the four types of V
D disturb showed that HDM structure preserved very reliable performance within a memory array operation. The main characteristics are compared with SRAM in
Table 2.