# Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Background

#### 2.1. In-Memory-Computation Architecture

#### 2.2. Spin Transfer Torque Write Circuit

#### 2.3. Spin-Hall Effect Assisted Spin Transfer Torque Write Circuit

## 3. Voltage Gated Spin Orbit Torque: Mechanism and Novel Write Circuit

## 4. Logic Gates Based on IMC

## 5. IMC Based Full Adder

## 6. Simulation Results and Discussion

#### 6.1. Write Circuits

#### 6.2. Performance of Logic Gates

#### 6.3. Performance of NV-FA Circuits

## 7. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## Abbreviations

P | Parallel |

AP | Antiparallel |

PL | Pinned layer |

FL | Fixed layer |

BL | Barrier layer |

IMC | In-memory-computation |

MTJ | Magnetic tunnel junction |

p-MTJ | Perpendicular magnetic tunnel junction |

STT | Spin transfer torque |

MRAM | Magnetoresistance random access memory |

SRAM | Static random access memory |

SHE+STT | Spin-Hall effected assisted Spin transfer torque |

VCMA | Voltage controlled magnetic anisotropy |

VG+SOT | Voltage-gated spin orbit torque |

SOI | Spin–orbit interaction |

SOC | Spin orbit coupling |

HM | Heavy metal |

AFM | Antiferromagnetic material |

LLG | Landau–Lifshitz–Gilbert |

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**Figure 1.**General IMC Block diagram consisting of sense amplifier, MOS logic tree along with MTJ pair and MTJ write. The input data presented to the CMOS logic tree are volatile in nature whereas the information stored in the MTJ pair is non-volatile.

**Figure 2.**Conventional STT p−MTJ write circuit, consisting of (

**a**) control circuit and (

**b**) writing core. Bi-directional ${I}_{SW}$ flows through the MTJ pair to switch its state between P and AP.

**Figure 3.**Schematic of SHE+STT p-MTJ write circuit consisting of (

**a**) control circuit and (

**b**) writing core.

**Figure 4.**VCMA effect in VG+SOT. (

**a**) Application of positive Vb causes the accumulation charges across the barrier layer resulting in (

**b**) lowering of Eb, thereby the FL’s magnetic orientation is in meta−stable state. This can assist in switching of MTJ status.

**Figure 5.**Schematic of switching action in VG+SOT. ${V}_{b}$ is applied to lower the ${E}_{B}$. Meanwhile (

**a**) ${\overrightarrow{J}}_{e}$ is forced through through AFM in −Y direction. Accumulation of spin polarized electrons (in −x direction) exerts SOT and alter its magnetic orientation from Z direction towards XY-plane. Under the influence of ${\overrightarrow{H}}_{EX}$ the magnetic orientation in the XY-plane precess and switches to −Z-direction, thereby completing switching of MTJ from P to AP. To switch the MTJ from (

**b**) AP to P, direction of the ${\overrightarrow{J}}_{e}$ is reversed.

**Figure 7.**Circuit for NOR−OR gate based on IMC showing (

**a**) SA, (

**b**) PDN for NOR-OR logic gates and (

**c**) MTJ switching block. Use MOS tree from (

**d**,

**e**) to obtain NAND−AND and XNOR−XOR respectively. Here two terminal p−MTJs are shown for STT logic gates. Replace them by three terminal MTJs to get SHE+STT/VG+SOT logic gates.

**Figure 8.**Simulated waveform for various hybrid logic gates showing inputs (

**a**) CP, (

**b**) A, (

**c**) B and corresponding outputs (

**d**) AND, (

**e**) NAND, (

**f**) OR, (

**g**) NOR, (

**h**) XOR, (

**i**) XNOR.

**Figure 9.**NV-FA based on IMC consisting of (

**a**) SA (

**b**) PDN for SUM and CARRY circuit with (

**c**) MTJ switching block. Here two terminal STT p−MTJ are shown for STT NV−FA. By replacing them with three terminal SHE+STT/VG+STT p−MTJs we can obtain SHE+STT/VG+SOT NVFA circuit.

**Figure 10.**Various inputs; (

**a**) CP, (

**b**) A, (

**c**) B (

**d**) ${C}_{in}$ and corresponding outputs; (

**e**) SUM, (

**f**) CARRY waveform for NV−FA based on IMC.

**Figure 11.**Comparison of (

**a**) total energy dissipation, (

**b**) delay, and (

**c**) EDP among different write circuits.

**Figure 12.**Simulated waveform for (

**b**–

**d**) STT, (

**e**–

**l**) SHE+STT and (

**m**–

**p**) VG+SOT write circuits. The input data (

**a**) IN is common whereas the other enable signals and switching of the MTJ pairs for the different write circuits are shown separately.

**Figure 15.**Comparison of (

**a**) total power dissipation, (

**b**) delay, and (

**c**) PDP between various NV-FA circuits.

**Table 1.**VG+SOT p-MTJ parameters set during the simulation. Rest of the parameters are retained as mentioned in ref. [30].

Parameter | Description | Value |
---|---|---|

TMR(0) | TMR ratio with zero bias | 200% |

Shape | MTJ Surface shape | circle |

$\mathrm{a}$ | MTJ Surface length | 32 nm |

$\mathrm{b}$ | MTJ Surface width | 32 nm |

$\mathrm{r}$ | MTJ Surface radius | 16 nm |

$\mathrm{w}$ | AFM width | 50 nm |

$\mathrm{d}$ | AFM thickness | 3 nm |

$\mathrm{l}$ | AFM length | 60 nm |

${t}_{sl}$ | Free layer thickness | 1.1 nm |

${t}_{ox}$ | MgO barrier thickness | 1.4 nm |

RA | Resistance-area product | 650 $\Omega \xb7$µ${\mathrm{m}}^{2}$ |

MTJ Switching Technique | STT | SHE+STT | VG+SOT |
---|---|---|---|

Writing core Energy/bit (fJ) | 861.9 | 819.4 | 63.07 |

Control circuit Energy/bit (fJ) | 1.28 | 2.88 | 0.837 |

Total Energy/bit (fJ) ^{a} | 863.18 | 822.28 | 63.907 |

Worst case delay (ns) | 5.1 | 0.386 | 2.88 |

Energy delay product ($\times {10}^{-24}$) ^{b} | 4402.21 | 317.4 | 184.05 |

No. of MOS | 22 | 46 | 28 |

Design Type | Min | Max | Mean | Std Divination |
---|---|---|---|---|

Writing core energy/bit (fJ) | 56.52 | 67.08 | 62.33 | 2.782 |

Control circuit energy/bit (fJ) | 0.749 | 0.883 | 0.833 | 0.031 |

Total energy/bit (fJ) | 57.269 | 67.963 | 63.163 | 2.813 |

Gate | NOR-OR | NAND-AND | XNOR-XOR | ||||||
---|---|---|---|---|---|---|---|---|---|

p-MTJ | STT | SHE+STT | VG+SOT | STT | SHE+STT | VG+SOT | STT | SHE+STT | VG+SOT |

Static | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ | 0 ${}^{a}$ |

power (nW) | (55.83 ${}^{b}$) | (53.51 ${}^{b}$) | (68.16 ${}^{b}$) | (55.48 ${}^{b}$) | (53.99 ${}^{b}$) | (62.96 ${}^{b}$) | (57.92 ${}^{b}$) | (58.89 ${}^{b}$) | (68.14 ${}^{b}$) |

Dynamic power (nW) | 25.59 | 26.99 | 8.9 | 28.95 | 28.33 | 16.72 | 32.75 | 30.4 | 19.34 |

Total power (nW) | 81.42 ${}^{c}$ | 80.5 ${}^{c}$ | 77.06 ${}^{c}$ | 84.43 ${}^{c}$ | 82.32 ${}^{c}$ | 79.68 ${}^{c}$ | 90.67 ${}^{c}$ | 89.29 ${}^{c}$ | 87.48 ${}^{c}$ |

Delay (ps) | 112.43 | 97.86 | 995.02 | 85.93 | 85.04 | 769.14 | 125.12 | 76.47 | 989.14 |

PDP (aJ) | 9.15 | 7.87 | 76.67 | 7.25 | 7 | 61.28 | 11.34 | 6.82 | 86.52 |

**Table 5.**Performance comparison between various NV-FA with STT, SHE+STT, and VG+SOT p-MTJs operating at a frequency of 100 MHz.

NVFA | STT | SHE+STT | VG+SOT |
---|---|---|---|

Static power (nW) | 0 ${}^{a}$ (119.4 ${}^{b}$) | 0 ${}^{a}$ (119.75 ${}^{b}$) | 0 ${}^{a}$ (145.7 ${}^{b}$) |

Dynamic power (nW) | 46.36 | 43.73 | 12.99 |

Total power (nW) | 165.76 ${}^{c}$ | 163.48 ${}^{c}$ | 158.69 ${}^{c}$ |

Delay (ps) | 114.95 | 115.67 | 876.14 |

PDP (aJ) | 19.05 | 18.9 | 139.03 |

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**MDPI and ACS Style**

Barla, P.; Shivarama, H.; Deepa, G.; Ujjwal, U.
Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation. *J. Low Power Electron. Appl.* **2024**, *14*, 3.
https://doi.org/10.3390/jlpea14010003

**AMA Style**

Barla P, Shivarama H, Deepa G, Ujjwal U.
Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation. *Journal of Low Power Electronics and Applications*. 2024; 14(1):3.
https://doi.org/10.3390/jlpea14010003

**Chicago/Turabian Style**

Barla, Prashanth, Hemalatha Shivarama, Ganesan Deepa, and Ujjwal Ujjwal.
2024. "Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation" *Journal of Low Power Electronics and Applications* 14, no. 1: 3.
https://doi.org/10.3390/jlpea14010003