Design and Assessment of Hybrid MTJ/CMOS Circuits for In-Memory-Computation

Abstract

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) circuits based on in-memory-computation (IMC) architecture is considered as the next-generation candidate for the digital integrated circuits. However, the energy consumption during the MTJ write process is a matter of concern in these hybrid circuits. In this regard, we have developed a novel write circuit for the contemporary three-terminal perpendicular-MTJs that works on the voltage-gated spin orbit torque (VG+SOT) switching mechanism to store the information in hybrid circuits for IMC architecture. Investigation of the novel write circuit reveals a remarkable reduction in the total energy consumption (and energy delay product) of 92.59% (95.81) and 92.28% (42.03%) than the conventional spin transfer torque (STT) and spin-Hall effect assisted STT (SHE+STT) write circuits, respectively. Further, we have developed all the hybrid logic gates followed by nonvolatile full adders (NV-FAs) using VG+SOT, STT, and SHE+STT MTJs. Simulation results show that with the VG+SOT NOR-OR, NAND-AND, XNOR-XOR, and NV-FA circuits, the reduction in the total power dissipation is 5.35% (4.27%), 5.62% (3.2%), 3.51% (2.02%), and 4.46% (2.93%) compared to STT (SHE+STT) MTJs respectively.

1. Introduction

In recent years, deep learning and artificial intelligence applications such as image classification, object detection, speech recognition, natural language processing, etc., have been remarkably successful due to their efficient software algorithms [1,2,3]. However, the hardware supporting these applications still works based on the conventional von-Neumann architecture, where the memory and computational units are separated, and bus/interconnects facilitate communication between the two. As a result, power wastage due to the frequent movement of signals between memory and computational units is remarkably high [4,5]. To add, the delay in these signals is also considerably high for large systems. Meanwhile, at the device level, miniaturization of CMOS poses challenges such as increased power dissipation because of the secondary effects [6]. Though there is constant advancement at the device level, it is clear that one can not solely depend on a single CMOS technology to fulfill all the present-day requirements [7]. In the present scenario, a high demand for a high-speed and power-efficient hardware design exists. To address this, in-memory-computation (IMC) is well-positioned to date [5,8,9,10]. The idea in IMC is to merge the memory and computation to avoid frequent data movement by providing low-power, high-speed computation. Some literature suggests SRAM as a memory for IMC [11,12,13,14]. However, the shortcomings, such as inherent leakage current, the necessity of large numbered transistors to store a single bit, the occupancy of large silicon area, etc., outweigh its other benefits [1]. This triggered a huge interest in the utilization of spintronic devices for IMC [15,16]. The spintronic devices are non-volatile memory (NVM) devices, where along with charge, spin of electrons also carries information. Among all spintronic devices, MRAM is the most promising due to its advantages such as higher endurance, fast read/write speeds, long data retention time, scalability, 3D fabrication, and ease of integration with the existing CMOS technology [1,17,18,19]. To store information bit, MRAM relies on the relative spin orientation of electrons that tunnel across the barrier layer (BL) sandwiched between two ferromagnetic materials, of which one is the free layer (FL) and the other is the pinned layer (PL). Thus forming a magnetic tunnel junction (MTJ). The MTJ is in a low resistance ($R_P$) parallel (P) state when both PL and FL are in the same direction; on the contrary, MTJ is in a high resistance ($R_{AP}$) anti-parallel (AP) state when PL and FL points in the opposite direction. The material used for the PL and FL is CoFe-based, and for BL is MgO. This is due to the achievement of high tunneling magnetoresistance (TMR) with CoFeB/MgO/CoFeB MTJs [20]. Altering the state of MTJ between ($R_{AP}$) and ($R_P$) is called MTJ switching/writing. There are several p-MTJ switching mechanisms such as spin transfer torque (STT) [21,22], spin-Hall effect assisted spin transfer torque (SHE+STT) [23,24], voltage assisted MTJ switching [25,26,27] etc. Among all, the recently presented voltage-gated spin orbit torque (VG+SOT) switching mechanism [28,29,30] has attracted the attention of many researchers due to its numerous advantages and is suitable for many applications [31,32]. In VG+SOT, MTJ switching is achieved with the combination of voltage and SHE effect. Encouraged by the developments in the VG+SOT MTJs, we have developed a novel write circuit for the VG+SOT for the IMC architecture. This write circuit is compared with the conventional STT and SHE+STT write circuits in terms of write energy, worst-case write delay, and energy-delay product (EDP). Then we developed all the hybrid logic gates, such as NOR-OR, NAND-AND, and XNOR-XOR followed by three non-volatile full adder (NV-FA) circuits using different MTJs such as STT, SHE+STT, and VG+SOT based on IMC architecture. The performance of all these circuits has been studied in terms of power dissipation, worst-case read delay, and power delay product (PDP). The rest of the paper is organized as follows: The background of IMC architecture, conventional STT and SHE+STT write circuit and their brief working is presented in the Section 2. In Section 3, we have explained the switching mechanism of VG+SOT MTJ and presented the novel VG+SOT write circuit, followed by its working. Then, in the Section 4 we have developed all the hybrid logic gates, i.e., NOR-OR, NAND-AND, XNOR-XOR. In Section 5, we have explained the design and working of NV-FA. The Section 6 presents performance evaluation of all the write circuits, hybrid logic gates and NV-FAs developed based on different MTJs for the IMC architecture. Finally, the paper is concluded in Section 7.

2. Background

2.1. In-Memory-Computation Architecture

The general structure for the IMC architecture is presented in Figure 1. It consists of (a) sense amplifier (SA), (b) pull-down logic network (PDN) block, and (c) MTJ write block. The SA is nothing but a current-controlled amplifier that senses the logic operations performed by the PDN to produce output (OUT${}^{+}$) and its complement (OUT${}^{-}$). The PDN is a hybrid circuit having CMOS tree integrated with MTJ pair. It performs the logic operation on the input data, result of which is produced by the SA. The integration of MTJ with CMOS is possible due to their resistance compatibility., viz, the $R_P$ is higher than $R_{ON}$. On the contrary, $R_{AP}$ is less than $R_{OFF}$. Where $R_{ON}$ and $R_{OFF}$ are CMOS ON and OFF resistances, respectively. The combined resistances of CMOS and MTJ in the left arm ($R_L$) and right arm ($R_R$) decide the corresponding rate of flow of current in the left arm ($I_L$) and right arm ($I_R$). Here we use a pair of MTJ to store a single bit of information. We assume MTJ pair with AP-P state always stores bit 0. Conversely, if the MTJ pair is in P-AP state, we assume information bit 1 is stored. It is noteworthy that the MTJ pair is always complementary to each other. The IMC operates in (a) pre-charge and (b) evaluation phase where the clock pulse (CP) is at 0 and 1, respectively. In the pre-charge phase, inputs are applied to the PDN and both, OUT${}^{+}$ and OUT${}^{-}$ are raised to logic 1. During the evaluation phase, logical operations are performed on these inputs at the PDN to produce corresponding OUT${}^{+}$ and OUT${}^{-}$. The OUT${}^{+}$ and OUT${}^{-}$ values depend upon the $R_L$ and $R_R$, which in-turn depend on $I_L$ and $I_R$. That is, $R_L$ and $R_R$ have inverse relations with $I_L$ and $I_R$ currents to produce OUT${}^{+}$ and OUT${}^{-}$. For instance, $R_L>R_R$ results in $I_L<I_R$ and produce OUT${}^{+}$ = 0 and OUT${}^{-}$ = 1. Otherwise when $R_L<R_R$ results in $I_L>I_R$ and produce OUT${}^{+}$ = 1 and OUT${}^{-}$ = 0.

Based on magnetic anisotropy, there are two types of MTJs. i.e., in-plane magnetic anisotropy MTJ (i-MTJ) and perpendicular-plane magnetic anisotropy MTJ (p-MTJ). Depending upon the type of MTJ (i-MTJ/p-MTJ), several switching techniques have been developed. The p-MTJ is superior due to smaller size, larger thermal stability, smaller switching current, ease of scaling compared to the i-MTJ [33]. Hence, we have focused on the p-MTJ devices in our work.

2.2. Spin Transfer Torque Write Circuit

The conventional STT p-MTJ switching circuit is presented in Figure 2 [6]. MTJ pair MTJ0-MTJ1 are used to store single-bit information. Bi-directional current ( $I_{SW}$) is used for changing the status of MTJs between AP and P. When EN = 0, the $I_{SW}$ flow is disabled. On the contrary, $I_{SW}$ flows in the writing core only when EN = 1. Assume bit 1 needs to be written into the MTJ pair, which was earlier stored with bit 0, i.e., its configuration must be changed from AP-P to P-AP. Switching is initiated upon asserting EN = 1 and IN = 1. Now the transistors MN1, and MP0 are OFF, whereas MN0 and MP1 are ON. This forces the $I_{SW}$ via the path Vdda-MP1-MTJ1-MTJ0-MN0-GND. Hence, the switching of the MTJ pair, i.e., P-AP, is achieved. Similarly, switching the MTJ pair from P-AP to AP-P to store bit 0 can be achieved by making EN = 1 and IN = 0.

Simple structure, ease of working, and potential to achieve higher density circuits make the STT-MTJs one of the most suitable commercial products [21,34]. However, the STT-MTJ suffers from several disadvantages. Frequent flow of $I_{SW}$ to switch the status of MTJ can break down the BL over a period of time. Apart from that, as the read and write paths are the same in the STT-MTJ, there is a chance of erroneous writing into the MTJ while the reading current passes through it, causing a read disturbance error. Most significantly, the STT-MTJ suffers the incubation delay, which is stochastic in nature. As a result, the switching delay of STT-MTJ is large, making it less favorable for high-speed applications.

2.3. Spin-Hall Effect Assisted Spin Transfer Torque Write Circuit

Some of the disadvantages of the STT writing mechanism are overcome with the three terminal SHE+STT p-MTJ [23,24]. For example, a separate read and write path of SHE+STT MTJ overcomes the read disturbance error. Meanwhile, the SHE effect considerably reduces the STT current, thereby eliminating the chances of BL breakdown. Furthermore, the incubation delay observed during the writing of STT-MTJ disappears in the SHE+STT p-MTJ, making it suitable for high-speed applications. Figure 3 shows the conventional SHE+STT p-MTJ switching circuit [35]. Compared with the STT p-MTJ switching circuit, an ENSHE input signal with EN and IN signals is present here. ENSHE controls the flow of SHE current. If we assume writing the MTJ pair with the information bit 1, then signals IN, EN, and ENSHE are asserted to logic 1. So the transistors MP0 and MN2 are OFF, whereas the rest are ON. This simultaneously initiates the flow of SHE current ($I_{SHE}$) and STT current $I_{STT}$. Path for $I_{SHE}$ is Vdda-MP1-MTJ0-MN1-GND and Vdda-MP3-MTJ1-MN3-GND. Whereas the $I_{STT}$ path is, Vdda-MP1-MTJ0-MN0-GND and Vdda-MP2-MTJ1-MN3-GND. As a result, the MTJ pair enters into the meta-stable state. After a small period, the ENSHE signal is made as logic 0. Hence, the transistors MN1 and MP3 are turned OFF to cease the $I_{SHE}$ flow. Whereas the $I_{STT}$ continues to flow and completes the switching of p-MTJ into P-AP, and information bit 1 is written. In a similar way, writing the information 0 into the MTJ pair can be done by making IN = 0.

Though SHE+STT p-MTJ is comparatively better than STT-MTJ, it suffers from the joule heating effect and ohmic losses due to the flow of current. Meanwhile, to handle these currents, one needs transistors with large size causing area overhead [36].

3. Voltage Gated Spin Orbit Torque: Mechanism and Novel Write Circuit

One significant method to overcome the ohmic loss and joule heating effect is incorporating the voltage to switch the p-MTJ status. Recent literature reveals that applying a voltage across p-MTJ can alter its magnetic anisotropy [37,38,39,40]. This effect is called voltage-controlled magnetic anisotropy (VCMA). The VCMA effect can switch the MTJ status. However, achieving deterministic MTJ switching with the VCMA effect requires either a precise voltage pulse or external assistance from a magnetic field or a small STT/SHE current. Since generating a precise voltage pulse or producing an external magnetic field in practical conditions is challenging [41,42], some circuits were developed with two terminal p-MTJs with VCMA+STT switching regime [42,43,44]. However, applying STT current poses the disadvantages of dielectric breakdown and read disturbance errors. Given this, a combination of VCMA in conjunction with SHE is employed to switch the MTJ status deterministically. Hence, a new type of p-MTJ switching regime called VG+SOT has been developed that combines the advantages of VCMA and SHE [45,46,47,48]. The VG+SOT p-MTJ is formed by mounting the combination PL/BL/FL on top of antiferromagnetic material (AFM) such as IrMn3 [49,50] as shown in the Figure 4a. The AFM material in VG+SOT p-MTJ generates SOT and provides an in-plane exchange bias (${\overrightarrow{H}}_{EX}$). However, the ${\overrightarrow{H}}_{EX}$ developed here is weak. Hence, the SOT alone can not switch the MTJ deterministically. Nevertheless, with assistance from the VCMA effect, the SOT generated can accurately switch the FL’s magnetic orientation in VG+SOT p-MTJ [30,51]. VCMA effect is generated by applying a small voltage ($V_b$), greater than or equal to the critical voltage ($V_c$) across the p-MTJ that lowers the energy barrier ($E_b$) (Figure 4b). This initiates a free precession of FL’s magnetic orientation. At the same time, a SHE current is forced through AFM to fix the FL’s magnetic orientation in a specific direction, i.e., either to P and AP. It is noteworthy that applying a negative $V_b$ increases $E_b$. The relationship between $E_b$ is modeled as a function of $V_b$ and given in the Equation (1) as,

$$E{}_b\left(V{}_b\right)\approx \left[K_i\left(V_b\right)-2\pi M_s^2\left(N_z-N_{x,y}\right)t_f\right]·A.$$

(1)

where $K_i\left(V_b\right)$ is the voltage-dependent interfacial PMA (perpendicular magnetic anisotropy), $M_s$ is the saturation magnetization, $t_f$ is the thickness of the FL, $V_b$ is the bias voltage, A is the sectional area of the MTJ, $N_z$ and $N_{x,y}$ are the demagnetization factors of the MTJ in the perpendicular and in-plane directions. The $V_c$, which is minimum voltage required to completely eliminate $E_b$ is defined by the Equation (2),

$$V{}_c=\Delta \left(0\right)k_{B}T{t}_{\mathrm{ox}}/\xi A.$$

(2)

where $\Delta \left(0\right)$ is thermal stability under zero voltage, $k_B$ is the Boltzmann constant, T is temperature, $t_{ox}$ is the thickness of the oxide layer, and $\xi$ is the VCMA coefficient.

Figure 5 presents the VG+SOT p-MTJ switching mechanism. Consider switching VG+SOT p-MTJ from P to AP state. Here, the unpolarized in-plane electrons (${\overrightarrow{J}}_e$) are forced through the AFM in the −Y direction. Due to a strong spin orbit coupling (SOC), SHE is observed in the AFM, which results in the deflection of opposite spin electrons (which are in $\pm X$ direction) in transverse, $\pm Z$ direction creating a spin current ${\overrightarrow{J}}_s$ in Z-direction. Hence, there is an accumulation of electrons (oriented in −X direction) at the interface of AFM/FL. This exerts SOT to tilt the FL’s magnetic orientation from the Z-direction toward the XY-plane. The presence of in-plane ${\overrightarrow{H}}_{EX}$ causes the FL’s magnetic orientation to precessionally rotate around the field and move toward the direction of ${\overrightarrow{H}}_{EX}$ (here it is Y-direction) by damping action. Meanwhile, the application of VCMA would lower the $E_b$ to switch the FL’s magnetic orientation towards the −Z-direction. Hence, the MTJ switches from AP to P state. Similarly, the switching of the MTJ from P to AP is achieved by reversing the direction of ${\overrightarrow{J}}_e$ (Figure 5b).

The proposed VG+SOT p-MTJ write circuit is presented in Figure 6. The write circuit is disabled when EN = 0, as all the transistors in the writing core are disabled. Upon the application of EN = 1, depending upon the IN signal, the MTJ pair is written with either bit 0 or 1. Assume, previously, bit 0 is stored in the MTJ pair, i.e., it is in AP-P state, and we want to write bit 1, i.e., the MTJ pair needs to be switched to P-AP. This can be initiated by asserting EN = 1, IN = 1, and VC = 1. Hence the intermediate voltages V1, V2, V3 and V4 are at 0101 which turns ON transistors MP1, MN0, MP2, MN3, MP4 and MP5, whereas MP0, MN1, MP3 and MN2 are OFF. As a result, a VCMA voltage (VC) is applied to the MTJ pair; simultaneously, a SOT current ($I_{SOT}$) flowing through the AFM applies a SOT on the FL’s magnetic orientation. The direction of $I_{SOT}$ is Vdd-MP1-MTJ0(T3-T2)-MN0-GND and Vdd-MP2-MTJ1(T2-T3)-MN3-GND. After 200 ps, the VC is disabled whereas the $I_{SOT}$ flows, completing the MTJ pair switching from AP-P to P-AP state. Hence, the writing of bit 1 into the MTJ pair is achieved. Similarly, writing bit 0 into the MTJ pair is achieved by making IN = 0.

4. Logic Gates Based on IMC

We have developed various logic gates based on the IMC architecture, and are presented in Figure 7. We have chosen the contemporary SA [52], which produces a quicker output response and dissipates lower power than its conventional counterpart [53]. For the purpose of explanation, we chose the operation of the NOR-OR logic gate, and the inputs applied are A = 0 and B = 1. During the pre-charge phase, CP = 0, SA transistor N3 is OFF, and P3 is ON. This facilitates sharing the NOR and OR output to reach logic 1 (Vdd-Vth). Meanwhile, inputs A and B are applied to the PDN. Here, the writing of the information (input B) occurs, i.e., MTJ0-MTJ1 are at P-AP state. The circuit enters into the evaluation phase by making CP = 1. Now the SA transistors, N3, is ON whereas P3 is OFF. In the PDN, N5 is OFF; meanwhile, both N4 and N6 are ON. This creates two current paths $I_L$ and $I_R$, i.e., $I_L$ is from NOR-N1-N4-MTJ0-N3-GND. $I_R$ is from OR-N2-N6-MTJ1-N3-GND. As the MTJ0-MTJ1 pair is in P-AP status, the branch resistance $R_L<R_R$, resulting in a quicker discharge of $I_L$ compared to $I_R$. So, the NOR node is discharged to the GND, making it logic 0. On the contrary, the OR node is pulled up to logic 1. Similarly, the working of the circuit for other inputs is realized. In Figure 7a, by replacing the MOS tree with Figure 7d,e, one can realize NAND-AND and XNOR-XOR logic gates respectively. Figure 8 shows the timing diagram of the logic gates for a clock frequency of 100 MHz.

5. IMC Based Full Adder

Having developed all the logic gates, we developed NV-FA based on IMC architecture with different types of MTJs shown in Figure 9. The working of this FA is in line with the IMC based logic gates, where there are two operating phases: pre-charge and evaluation. In the pre-charge (CP = 0), all the outputs, sum (SUM${}^{+}$) and its complement (SUM${}^{-}$), and carry (CARRY${}^{+}$), and its complement (CARRY${}^{-}$) are at logic 1 (Vdd-Vth). Meanwhile, input A, B, and $C_{in}$ are applied to the PDN. During the evaluation (CP = 1), these inputs are processed to produce outputs (SUM${}^{+}$/SUM${}^{-}$ and CARRY${}^{+}$/CARRY${}^{-}$). Imagine the inputs applied in the pre-charge phase are A = 1, B = 0, and $C_{in}$ = 0. During the evaluation phase, both in SUM and CARRY circuits, there are two routes, Path-R1 and Path-R2, from their respective nodes to the GND. This is because, in the PDN of the SUM circuit, transistors M1, M3, M6, and M8 are ON, whereas the other transistors are OFF. The Path-R1 is via SUM${}^{-}$-N1-M1-M3-MTJ1-N3-GND. Path-R2 is via SUM${}^{+}$N2-M6-M8-MTJ0-N3-GND. As $C{i}_{in}$ = 0, the MTJ pair is in AP-P state. So, the total resistance in Path-R1 < Path-R2. Hence, the SUM${}^{-}$ node is pulled down to GND, and the SUM${}^{+}$ node is pulled up to Vdd. Therefore, SUM${}^{+}$ = 1 and SUM${}^{-}$ = 0. Similarly, in the carry circuit, the total resistance in Path-R1 < Path-R2. Path-R1 is via CARRY${}^{-}$N1-M2-M4-MTJ0-N3-GND, and Path-R2 is via CARRY${}^{+}$-N2-M6-M8-MTJ1-N3-GND. So the CARRY${}^{+}$ = 0 and CARRY${}^{-}$ = 1. Likewise, the working of NV-FA for other input combinations can be realized. Figure 10 shows the timing diagram of the IMC based NV-FA for a clock frequency of 100 MHz.

6. Simulation Results and Discussion

To assess the performance of the write, hybrid logic gates, and NV-FA circuits, we performed the simulation using the Cadence Virtuoso tool with 45nm CMOS generic process design kit. The model for the VG+SOT p-MTJ is adopted from Ref. [30], and the parameters used during the simulation work are shown in

Table 1. VG+SOT p-MTJ parameters set during the simulation. Rest of the parameters are retained as mentioned in ref. [30].

Parameter	Description	Value
TMR(0)	TMR ratio with zero bias	200%
Shape	MTJ Surface shape	circle
$\mathrm{a}$	MTJ Surface length	32 nm
$\mathrm{b}$	MTJ Surface width	32 nm
$\mathrm{r}$	MTJ Surface radius	16 nm
$\mathrm{w}$	AFM width	50 nm
$\mathrm{d}$	AFM thickness	3 nm
$\mathrm{l}$	AFM length	60 nm
$t_{sl}$	Free layer thickness	1.1 nm
$t_{ox}$	MgO barrier thickness	1.4 nm
RA	Resistance-area product	650 $\Omega ·$µ${\mathrm{m}}^2$

.

6.1. Write Circuits

Table 2. Performance comparison between STT, SHE+STT, and VG+SOT writing.

MTJ Switching Technique	STT	SHE+STT	VG+SOT
Writing core Energy/bit (fJ)	861.9	819.4	63.07
Control circuit Energy/bit (fJ)	1.28	2.88	0.837
Total Energy/bit (fJ) a	863.18	822.28	63.907
Worst case delay (ns)	5.1	0.386	2.88
Energy delay product ($\times {10}^{-24}$) b	4402.21	317.4	184.05
No. of MOS	22	46	28

${}^a$ = Writing core energy/bit + Control circuit Energy/bit. ${}^b$ = Total energy/bit * Worst case delay.

shows the performance comparison of the various write circuits. We can observe that the control circuit’s energy dissipation is comparatively lower than the writing core. This is because the control circuitry consists of only logic gates, whereas the writing core contains MTJ pair. The energy required to switch the MTJ pair is always higher than the rest of the circuitry. Among all the write circuitry, the least total energy consumption is observed with the VG+SOT p-MTJ circuit, followed by SHE+STT and STT. In writing core, VG+SOT write circuit consumes 92.0% and 92.68% less energy than SHE+STT and STT, respectively. The control circuit of the VG+SOT write circuit consumes 70.93% and 34.6% lower energy than SHE+STT and STT, respectively. The total energy dissipation of VG+SOT write circuit is 92.28%, and 92.59% lower than SHE+STT and STT, respectively. In VG+SOT switching, thanks to the VCMA effect, the p-MTJ’s energy barrier gets lowered, facilitating its switching with an application of $I_{SOT}$ current through the AFM. However, the worst-case write delay of VG+SOT is 86.59% more than SHE+STT write circuitry. Meanwhile, the delay of the VG+SOT write circuit is less than STT by 43.52%. The higher delay in the VG+SOT switching mechanism is because, when $I_{SOT}$ current is applied, the SOT is responsible for tilting FL’s magnetic orientation from its original position towards the XY-plane. Now, the p-MTJ is in a meta-stable state. Switching is assisted by the presence of ${\overrightarrow{H}}_{EX}$, where the FL’s magnetic orientation initially precesses and settles down. The time taken to precess and then settling of FL’s magnetic orientation causes the delay. Meanwhile, with SHE+STT switching, once the magnetic orientation is in the XY plane, its precession is almost zero, and STT torque forces switching of p-MTJ quickly. Hence, the delay is the least. However, with STT switching, due to the stochastic nature of STT p-MTJ, there is an initial delay in misaligning the FL’s magnetic orientation from its initial position. This results in higher delay. The EDP, product of total energy dissipation and worst case write delay of VG+SOT write circuit, is lesser than the rest. The EDP of the VG+SOT write circuit is 42.03% and 95.81% lower than SHE+STT and STT write circuits, respectively. Regarding the number of transistors, the STT write circuitry uses only 22 MOS, whereas the SHE+STT write circuitry uses almost double, i.e., 46 MOS transistors. However, the VG+SOT write circuitry uses only 6 additional MOS (i.e., 28) compared to STT. Figure 11 shows a bar chart plot of the total energy consumption, worst-case write delay, and the EDP among the various write circuits. In Figure 12, we have presented the simulated waveform for all the write circuits together. To begin with, bit 1 is stored in the MTJ pair. At T1, writing of the bit 0 is initiated, followed by writing of the bit 1 at T2. We have also shown redundant write conditions at time T3. Writing the information bit 0/1 is completed after a brief delay as shown in the Table 2.

Overall, the VG+SOT write circuit is superior to its other counterpart except for the write delay. VG+SOT p-MTJ write circuit has an increased write delay compared to the SHE+STT. Recent research has actively identified ferrimagnetic alloy materials, such as cobalt-gadolinium (CoGd), as efficient replacements for the AFM [54], primarily due to their ability to reduce delay significantly. Ferrimagnetic materials can reduce the switching delay to subnanoseconds. However, more effort is required to integrate ferrimagnets with conventional MTJ to develop practical applications [55]. Meanwhile, efforts have been made to develop an efficient all-antiferromagnetic tunnel junction (AATJ) [56]. The AATJ structure is made of Mn3Pt/MgO/Mn3Pt/MnPt combination. With AATJ, although a switching speed in the range of picoseconds can be achieved, the maximum TMR achieved with it is approximately 100% at room temperature. Hence, its practical application is limited.

We have investigated the effect of TMR variation on the VG+SOT write circuit parameters, as shown in Figure 13. Here, we have increased the TMR from 200 to 350 in steps of 50. Notice that as the TMR value increases, the total energy/bit, worst case delay, and EDP decreases slightly. Hence, we can say achieving a higher TMR is vital for the design of efficient hybrid circuits.

It is crucial to study the reliability of the VG+SOT write circuit for the process and mismatch variations that could happen during its fabrication. Hence, we have performed the Monte-Carlo simulations on VG+SOT write circuit by incorporating 3% variations in TMR, $t_{sl}$, and $t_{ox}$ along with CMOS variations, and the results energy/bit are tabulated in

Table 3. Energy consumption of VG+SOT write circuit during Monte-Carlo simulation of 200 runs.

Design Type	Min	Max	Mean	Std Divination
Writing core energy/bit (fJ)	56.52	67.08	62.33	2.782
Control circuit energy/bit (fJ)	0.749	0.883	0.833	0.031
Total energy/bit (fJ)	57.269	67.963	63.163	2.813

. Here, we can notice that the total energy/bit value is always less than ≈68 fJ.

6.2. Performance of Logic Gates

Table 4. Comparison between various logic gates operating at 100 MHz.

Gate	NOR-OR			NAND-AND			XNOR-XOR
p-MTJ	STT	SHE+STT	VG+SOT	STT	SHE+STT	VG+SOT	STT	SHE+STT	VG+SOT
Static	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$	0 ${}^a$
power (nW)	(55.83 ${}^b$)	(53.51 ${}^b$)	(68.16 ${}^b$)	(55.48 ${}^b$)	(53.99 ${}^b$)	(62.96 ${}^b$)	(57.92 ${}^b$)	(58.89 ${}^b$)	(68.14 ${}^b$)
Dynamic power (nW)	25.59	26.99	8.9	28.95	28.33	16.72	32.75	30.4	19.34
Total power (nW)	81.42 ${}^c$	80.5 ${}^c$	77.06 ${}^c$	84.43 ${}^c$	82.32 ${}^c$	79.68 ${}^c$	90.67 ${}^c$	89.29 ${}^c$	87.48 ${}^c$
Delay (ps)	112.43	97.86	995.02	85.93	85.04	769.14	125.12	76.47	989.14
PDP (aJ)	9.15	7.87	76.67	7.25	7	61.28	11.34	6.82	86.52

Note: Write circuit has been excluded in the tabulated values. Static, dynamic and total power dissipation are the average values. ${}^a$ In standby mode power is switched off, resulting in zero static power. ${}^b$ Static power dissipation in steady state condition. ${}^c$ Total power dissipation = static power + dynamic power in active mode.

shows the performance comparison of logic gates with different p-MTJ circuits. The static power dissipation of all the logic gates is considered to be zero. This is because as a nonvolatile MTJ pair is utilized to store input B, we can turn off the supply in the standby mode without losing the stored bit. During active mode, the bit stored is readily available for computation without the write/restoration process. However, there is a steady-state power dissipation observed with gates, as shown in Table 4. In the NOR-OR gates, the dynamic power dissipation of the VG+SOT is least followed by STT and SHE+STT based gates. VG+SOT consumes 65.22% and 67.02% lower dynamic power than STT and SHE+STT NOR-OR gates respectively. The total power dissipation of VG+SOT is least followed by SHE+STT and STT. VG+SOT gate dissipates 4.27%, and 5.35% lower total power than SHE+STT and STT gates, respectively. The worst-case read delay of SHE+STT based NOR-OR gates least followed by STT, and VG+SOT. SHE+STT based NOR-OR gate’s worst case read delay is 12.95%, and 90.16% lower than STT, and VG+SOT, respectively. The PDP is calculated by multiplying total power with worst case read delay. The PDP SHE+STT based NOR-OR gate is least followed by STT and VG+SOT. The PDP of the SHE+STT gate is 13.98% and 89.73% lower than the STT and VG+SOT gates, respectively.

In the NAND-AND gates, the dynamic power dissipation of the VG+SOT is least followed by SHE+STT and STT based gates. VG+SOT consumes 40.98% and 42.24% lower dynamic power than SHE+STT and STT gates respectively. The total power dissipation of VG+SOT is least followed by SHE+STT and STT. VG+SOT gate dissipates 3.2% and 5.62% lower total power than SHE+STT and STT gates, respectively. The worst-case read delay of SHE+STT based NAND-AND gates least followed by STT and VG+SOT. SHE+STT based gate’s worst-case read delay is 1.03% and 88.94% lower than STT and VG+SOT, respectively. The PDP SHE+STT based NAND-AND gates is least followed by STT and VG+SOT. The PDP of SHE+STT gate is 3.44%, and 88.57% lower than STT and VG+SOT gates, respectively.

In the XNOR-XOR gates, the dynamic power dissipation of the VG+SOT is least followed by SHE+STT and STT based gates. VG+SOT consumes 36.38% and 40.96% lower dynamic power than SHE+STT and STT gates respectively. The total power dissipation of VG+SOT is least followed by SHE+STT and STT. VG+SOT gate dissipates 2.02% and 3.51% lower total power than SHE+STT and STT gates, respectively. The worst-case read delay of SHE+STT based XNOR-XOR gates least followed by STT and VG+SOT. SHE+STT based gate’s worst-case read delay is 38.88% and 92.26% lower than STT and VG+SOT respectively. The PDP SHE+STT based XNOR-XOR gates is least followed by STT and VG+SOT. The PDP of SHE+STT is 39.85%, 92.11% lower than STT and VG+SOT based gates respectively.

We can observe that total power dissipation in all the logic gates is the least with VG+SOT logic gates, followed by SHE+STT and STT. However, the read delay of SHE+STT based logic gates is lower. This is because the IrMn3, AFM material in VG+SOT p-MTJ has higher resistivity, i.e., 278 µ$\Omega$cm [30], whereas the Ta, HM material in SHE+STT p-MTJ has a lower resistivity of 190 µ$\Omega$cm [57]. A higher resistivity of IrMn3 poses a higher resistance in the discharge current path with VG+SOT based logic gates, resulting in higher read delay. However, we know that based on the inputs, during the evaluation phase, one of the outputs (either OUT${}^{+}$ or OUT${}^{-}$) is discharged to GND, whereas the other one is raised to Vdd. Here, the value of OUT${}^{+}$ and OUT${}^{-}$ is constant, whereas the discharge path resistance of VG+SOT is more due to the higher resistivity of AFM. Hence, we observe a lower power dissipation with VG+SOT circuits. Nevertheless, a higher delay causes a larger PDP with VG+SOT based logic gates. Figure 14 shows the bar chart plot of the dynamic, total power dissipation, worst-case read delay, and PDP for various logic gates circuits.

6.3. Performance of NV-FA Circuits

Table 5. Performance comparison between various NV-FA with STT, SHE+STT, and VG+SOT p-MTJs operating at a frequency of 100 MHz.

NVFA	STT	SHE+STT	VG+SOT
Static power (nW)	0 ${}^a$ (119.4 ${}^b$)	0 ${}^a$ (119.75 ${}^b$)	0 ${}^a$ (145.7 ${}^b$)
Dynamic power (nW)	46.36	43.73	12.99
Total power (nW)	165.76 ${}^c$	163.48 ${}^c$	158.69 ${}^c$
Delay (ps)	114.95	115.67	876.14
PDP (aJ)	19.05	18.9	139.03

Note: Write circuit has been excluded in the tabulated values. Static, dynamic and total power dissipation are the average values. ${}^a$ In standby mode power is switched off, resulting in zero static power. ${}^b$ Static power dissipation in steady state condition. ${}^c$ Total power dissipation = static power + dynamic power in active mode.

show the performance comparison of NV-FA circuits with various p-MTJs.

The dynamic power dissipation of the VG+SOT based NV-FA is least followed by SHE+STT and STT based NV-FA. VG+SOT based NV-FA consumes 70.29% and 71.98% lower dynamic power than SHE+STT and STT NV-FAs, respectively. The total power dissipation of VG+SOT based NV-FA is least followed by SHE+STT and STT. VG+SOT NV-FA dissipates 2.93% and 4.26% lower power than SHE+STT and STT NV-FA, respectively. The worst case read delay of STT based NV-FA is least followed by SHE+STT, and VG+SOT based NV-FAs. STT based NV-FA’s worst case read delay is 0.62% and 86.87% lower than SHE+STT and VG+SOT based NV-FA, respectively. The PDP SHE+STT NV-FA is least followed by STT and VG+SOT. The PDP of SHE+STT NV-FA is 0.78% and 86.4% lower than STT and VG+SOT based NV-FAs respectively. The reason for the increased read delay and PDP is the same as that of VG+SOT logic gates discussed in the previous section. Figure 15 shows the bar chart plot of the dynamic, total power dissipation, worst-case read delay, and PDP for various NV-FA circuits.

7. Conclusions

In this paper, we have developed a novel write circuit for VG+SOT p-MTJs based on IMC architecture. Simulation results show that the novel write circuit consumes significantly less energy and EDP than conventional STT and SHE+STT write circuits. However, the worst-case write delay of the novel write circuit is more than the others. Then we developed all the logic gates, such as NOR-OR, NAND-AND, and XNOR-XOR, followed by three different types NV-FA with VG+SOT, STT, and SHE+STT p-MTJs based on IMC architecture. Results obtained from the simulation reveal that VG+SOT-based logic gates and NV-FA dissipate lower power than their other counterparts. Based on the results of this paper, we foresee a higher usage of VG+SOT-based hybrid circuits in low-power applications in the future.