MultiPorted GCeDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism^{ †}
Abstract
:1. Introduction
Contributions
 This work presents the first reported 2R2W and 6R2W GCeDRAM memory, as well as a general design guideline for Nported dynamic memories.
 The resulting bitcell is the smallest multiported memory reported in the literature.
 A novel opportunistic refresh port approach for dynamic memory arrays with NRMW access ports is provided.
 The proposed array can be dynamically configured to support an internal refresh operation without sacrificing memory availability.
2. MultiPorted Gain Cell Design
2.1. 2R2W Cell Design and Operating Mechanism
2.2. Expanding the Number of Read Ports
3. Implementation and Simulation Results
3.1. 2R2W Bitcell Layout
3.2. Expanding the Layout to Accommodate Additional Read Ports
3.3. Simulation Results
4. Configurable Operation
4.1. NRMW Operation Mode
4.2. Internal Refresh Mode
4.3. High Performance Opportunistic Refresh Port Mode
 The previous data is written back into the array at the current cycle.
 There is no data in the buffer.
Algorithm 1 Refresh Controller Algorithm 

5. Comparison to SRAM
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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6T SRAM [54]  8T 1W1R SRAM [54]  8T 2WR SRAM [3]  10T 1W2R SRAM [2]  Conventional 2TNMOS GainCell [34]  Proposed 4T GainCell [This Work]  

Technology Node  28 nm FDSOI  28 nm FDSOI  65 nm CMOS  45 nm CMOS  28 nm FDSOI  28 nm FDSOI 
Supply Voltage  0.7 V  0.48–0.7 V  1.2 V  1 V  0.9 V  0.9 V 
Availability  100%  100%  100%  100%  97.3% *  100% 
Cell Size  $0.325\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.42\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.71\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.8\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.152\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.23\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$ 
Ratio to 6TSRAM  1 X  1.3 X  1.44 X  2.14 X  0.47 X  0.71 X 
Data Retention Time  Static  Static  Static  Static  $9.6\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}\mathrm{s}$  $11\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}\mathrm{s}$ 
Leakage Power (In 28 nm FDSOI)  12.9 pW/bit  16.3 pW/bit  13.1 pW/bit  16.7 pW/bit  576 fW/bit  1.25 pW/bit 
6T 1W5R Gain Cell [This Work]  16T 1W5R SRAM [5]  9T 1W8R Gain Cell [This Work]  20T 1W8R SRAM [4]  12T 6W6R Gain Cell [This Work]  16T 3W3R/6W6R SRAM [16]  

Technology Node  28 nm FDSOI  90 nm CMOS  28 nm FDSOI  40 nm CMOS  28 nm FDSOI  7 nm CMOS 
Supply Voltage  0.9 V  Not Reported  0.9 V  1.1 V  0.9 V  0.9 V 
Availability *  97.3% *  100%  97.3% *  100%  99.1% *  100% 
Cell Size  $0.55\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $7.35\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $1.04\phantom{\rule{3.33333pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $3.12\phantom{\rule{4pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $1.78\phantom{\rule{4pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$  $0.39\phantom{\rule{4pt}{0ex}}{\mathsf{\mu}\mathrm{m}}^{2}$ 
Ratio to 6TSRAM  1.7 X  7.36 X  3.2 X  12.9 X  5.46 X  14.25 X 
Data Retention Time  $21.8\phantom{\rule{4pt}{0ex}}\mathsf{\mu}\mathrm{s}$  Static  $23.5\phantom{\rule{4pt}{0ex}}\mathsf{\mu}\mathrm{s}$  Static  $15.2\phantom{\rule{4pt}{0ex}}\mathsf{\mu}\mathrm{s}$  Static 
Leakage Power (In 28 nm FDSOI)  3.12 pW/bit  34.6 pW/bit  3.45 pW/bit  90 pW/bit  12.6 pW/bit  108 pW/bit 
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Golman, R.; Giterman, R.; Teman, A. MultiPorted GCeDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism. J. Low Power Electron. Appl. 2024, 14, 2. https://doi.org/10.3390/jlpea14010002
Golman R, Giterman R, Teman A. MultiPorted GCeDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism. Journal of Low Power Electronics and Applications. 2024; 14(1):2. https://doi.org/10.3390/jlpea14010002
Chicago/Turabian StyleGolman, Roman, Robert Giterman, and Adam Teman. 2024. "MultiPorted GCeDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism" Journal of Low Power Electronics and Applications 14, no. 1: 2. https://doi.org/10.3390/jlpea14010002