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Communication

Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition

by
Po-Chou Chen
1,
Shu-Mei Chang
1,
Hao-Chung Kuo
2,
Fu-Cheng Chang
2,
Yu-An Li
3 and
Chao-Cheng Ting
2,*
1
Institute of Organic and Polymeric Materials, National Taipei University of Technology, Taipei 10608, Taiwan
2
Department of Photonics & Institute of Electro-Optical Engineering, College of Electrical and Computer Engineering, National Chiao Tung University, Hsinchu City 30010, Taiwan
3
Pure Metallica Co., Ltd., Taipei City 11493, Taiwan
*
Author to whom correspondence should be addressed.
Coatings 2022, 12(9), 1308; https://doi.org/10.3390/coatings12091308
Submission received: 1 August 2022 / Revised: 29 August 2022 / Accepted: 30 August 2022 / Published: 7 September 2022
(This article belongs to the Special Issue Technologies of Coatings and Surface Hardening for Tool Industry II)
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Abstract

:
In this research, a 14 nm high-performance computing application-specific integrated circuit was coated with a 5–20 nm Al2O3 thin film by atomic layer deposition in room-temperature conditions to study its performance in terms of reliability with different thicknesses. An open/short test, standby current measurement, interface input/output performance test, and phase-locked loops functional test were used to verify chip performance. Furthermore, an unbiased highly accelerated temperature and humidity stress test and a 72 h wear-out test were used to study the effects of the atomic layer deposition coating. The results showed that the coating thickness of 15 nm provided the best performance in the wear-out test, as well as the unbiased highly accelerated temperature humidity stress. This study demonstrates that room-temperature atomic layer deposition is a promising technique for enhancing the reliability of advanced node semiconductor chips.

1. Introduction

Atomic layer deposition (ALD) process technology was first developed in the 1970s. In 1977, Dr. Tuomo Suntola of Finland officially applied for the first patent related to ALD technology [1,2,3]. Between 1983 and 1998, ALD technology was applied to the production of electronic displays at Helsinki Airport, Finland. In the late 1990s, as the semiconductor industry began to introduce ALD processes, a large amount of research and development funding and manpower was invested into the rapid growth of ALD process technology. In the year 2007, Intel used ALD process technology to grow a hafnium oxide (HfO2) gate-oxide layer for a metal-oxide-semiconductor field-effect transistor on a 45 nm microprocessor, further establishing the importance of ALD process technology in the semiconductor industry [4].
ALD is a surface-chemical reaction-based technology featuring excellent atomic thickness accuracy, large area uniformity, and conformity of the film on high-aspect-ratio structures [5].
The coating of thermally fragile substrates by ALD may provide exciting new applications in diverse areas ranging from packaging to microelectronics. For example, thin ALD films may serve as an efficient hole-blocking layer in a complementary metal-oxide-semiconductor image sensor to enhance the signal to noise ratio [6,7]. ALD coatings on polymers may also be important as gas diffusion barriers for flexible electronic devices or organic light-emitting diodes [8,9]. Moreover, applications of ALD processes have been demonstrated at low temperatures of <100 °C [10,11,12,13,14,15,16,17,18]. Room-temperature catalytic SiO2 ALD has been realized using SiCl4 and H2O plus pyridine or NH3 as the catalyst [19,20]. The ALD of ZnSe and CdS has also been demonstrated at room temperature [21]. The ALD technique is widely used in the electronic industry [22]. However, few studies have addressed the advantages of deposition on a packaged chip. Most ALD processes occur at temperatures >100 °C that would degrade organic, polymeric, or biological material. The material normally used for the packaging of semiconductor chips is organic polyimide. As the technology advances, the performance in terms of reliability becomes critical, and sensitivity to moisture in harsh environments becomes a factor when using the chip. In this study, a 14 nm high-performance computing application specific integrated circuit (ASIC) was selected to verify the effect of changing the thickness of the ALD coating on performance in terms of reliability, which was proposed for the first time. An open/short test, standby current measurement, interface input/output performance test, and phase-locked loops (PLL) function test were used to verify the chip yield. The lowest operating voltage (LOV) was used as the performance index for reliability after wear-out tests and unbiased highly accelerated temperature and humidity stress test (uHAST). The ASIC with a 15 nm Al2O3 ALD coating showed the best performance in both the uHAST and the 72 h wear-out test. The reasons for failure of the 25 nm thick coating remain unclear and are worthy of further investigation. The results of this study provide an interesting evaluation of the relationship between ALD coating thickness and performance in terms of reliability, which can pave the way for a new package scheme in advanced semiconductor processes.
The aim of this study is to establish a protective nanoscale thin film using the ALD technology for electronic components in a prepackaged high-performance computing chip, which can improve the electrical performance and reliability after high-temperature and high-humidity stress tests.

2. Materials and Methods

The ALD technique was applied using the Lunamia model LA-1T from Pure Metallica Co., Ltd., Taipei City, Taiwan. The Lunamia is a type of capacitive plasma-enhanced ALD equipment. To apply the plasma ALD coating of the Al2O3 layer, the reaction conditions were trimethylaluminum exposure (from PentaPro Materials Inc., Hsinchu County, Taiwan, purity: 6N), argon purge (from Jing De Gases Co., Ltd., Kaohsiung City, Taiwan, purity: 5N), and oxygen (from Jing De Gases Co., Ltd., purity: 6N) with a plasma power of 100 W. Each step was controlled by the automatic processes described below.
First, the inert gas was introduced into the deionized water tank, as well as water vapor, using a plasma power of 100 W, which covered the substrate with hydroxyl groups, thereby forming a reactive layer (i.e., prereaction seasoning). The precursor was introduced into the chamber, along with the carrier gas Ar, at a flow rate of 500 sccm to form a surface-adsorbed monolayer for later reaction.
Second, the precursor and other byproducts were removed by introducing the inert gas Ar, followed by pumping the chamber to a base pressure of 10−6 Torr. Third, the reaction gas O2 was then introduced, supplemented by plasma. This O2/plasma mixture allowed oxygen radicals to react with the surface-adsorbed Al precursor, thereby forming an alumina monolayer, i.e., the desired material for the ALD process.
The fourth and final step of the ALD reaction cycle involved removal of the excess reaction gas and byproducts by again introducing the inert gas Ar, followed by pumping the chamber to the base pressure. Table 1 lists the ALD process parameters. The O2 process was to ensure the complete oxidation of the trimethylaluminum. The radio frequency (RF) power of 100 W was selected by considering the degree of oxidation with the minimum of substrate reflected power. The soak time was considered for the full diffusion of the precursor for better process uniformity. The Ar purge time was to ensure no aluminum precursor remained forming gas-phase reaction-generating particles.
The thickness and the quality of the ALD coatings were determined by ellipsometry. The desired thickness could be controlled by the cycle number, whereby one ALD cycle deposited 0.24 nm of Al2O3 thin film. The ALD thicknesses of 5–20 nm were selected to study their effect on performance in terms of reliability.
The uHAST was carried out at a temperature of 130 °C and 85% relative humidity (RH) for 96 h at a relative pressure of 2.3 atm. The stressed duration was 96 h under the JESD22-A118 regulation. After an ambient temperature test, various electrical measurements were performed, including an open/short test, power short test, ISB (power standby current test), direct current (DC) characterization test, and lowest operation voltage functional test (0.62–0.78 V) using an Agilent 9300 SOC series (Santa Clara, CA, USA). The uHAST and automatic testing equipment is displayed in Figure 1.

3. Results

3.1. Background of the 14 nm HPC ASIC

The cryptocurrency mining chip is a 14 nm ASIC. This chip operates in harsh conditions when used in high-performance computing. Thus, its reliability is crucial, as cryptocurrency mining machines require reliable computing performance to ensure their profitability. A 14 nm ASIC can provide lower power consumption, along with high computing performance, making it suitable for mining applications.
Figure 2 shows a block diagram illustrating the functions of the 14 nm ASIC. The ASIC consists of five main functional circuits, including the PLL which fundamentally provides the clock source used for controlling the calculation via an automatic feedback design. The PLL clock serves as a gateway to the calculation hash core, which features translated algorithms used to directly operate the software to generate cryptocurrency. The control unit rechecks the calculation result and outputs the data through the IO_OUT pin.

3.2. Yield and Reliability of the ALD-Coated ASIC Chip

Figure 3 illustrates the conditions of the coating structure and the thermal dispatch pathway of the flip-chip land grid array (FCLGA). Two exposed heat sinks were used as the main heat dispatch material. Inside the package, the chip was connected via a copper pillar bump. During high-speed operation, the chip generates tremendous heat and becomes vulnerable to moisture in the environment. In order to prevent its penetration into the chip, different ALD Al2O3 coatings thicknesses were applied, and we studied their effect on performance in terms of reliability.
Figure 4 shows the cross-section FIB image of the 50 nm ALD-coated thin film. The ALD-coated thin film established a uniform and continuous protection layer of the integrated chip. The diagram in Figure 5 (top panel) schematically demonstrates the ALD coating on the 14 nm ASIC. The results showed that the 15 nm thick ALD alumina coating exhibited the lowest operation voltage performance after a 1000 h uHAST, whereby the operation voltage was reduced to 0.62 V, thus indicating its ability to resist harsh conditions. The similar results of a 72 h wear-out test were also performed (not shown here). On the other hand, the chip with a 20 nm thick coating failed the DC 72 h wear-out stress test. The reason for failure was not clear and is worthy of further investigation. It is suspected that the chlorine ion may have reacted with the alumina coating, thereby causing interconnect path damage. The previous work in corrosion research indicated that the existence of Al2O3 accelerated the penetration of the chlorine ion (Cl−) and thus corrosion occurred [24]. The mechanism of how the corrosion induced by moisture and Cl− occurred was also proposed by Fu et al. [25].
Figure 5 shows how the ALD coating protected the printed circuit board (PCB) structure; the alumina layer prevented moisture from penetrating into the main chip, while also facilitating good heat dispatch. The ALD layer established a capped circuit structure, allowing the thermal stress of the surface and the chip to be alleviated. Otherwise, moisture could penetrate through the land grid metal pad and the adjacent plastic substrate due to the difference in thermal expansion coefficient between the metal pad and epoxy polymer molding, thus leading to thermal stress accumulation and thermal strain distribution problems. In our study, the ALD coating alleviated the stress-induced electronic performance decay. The effect of an epoxy molding compound on thermal stresses in IC packages during the manufacturing process were carefully discussed [26,27]. In the study, the failure of the chip was caused by the thermal deformations of the die/EMC bimaterial. The experimental results also showed that the ability to resist the harsh environment varied with the tested thicknesses of 0, 5, 10, 15, and 20 nm, according to 1000 h of an uHAST and 72 h of a wear-out salt-spray test.
Figure 6 illustrates the open/short testing method. A current of 100 mA was collected from the input/output (IO) pad, and the voltage was measured. The ALD coating with a thickness of 20 nm failed the open/short test, according to the criteria listed in the figure (−0.2 to 0.7 V). This may have been due to the thickness of the Al2O3 coating, which caused poor pad connection after the 72 h wear-out test. The sheet resistance test was performed with different ALD thicknesses on the conducting substrate. The sheet resistance was 1.6 × 107 ohm/sq with an Al2O3 thickness of 16 nm.
Table 2 lists the uHAST results with different Al2O3 thicknesses. The chip with a 15 nm thick protection layer demonstrated the lowest operation voltage (0.66 V). It was also discovered that a thinner protection layer led to a higher operation voltage shift. The yield was only 50% with an operation voltage of 0.78 V when the ALD coating thickness was below 10 nm. Figure 7 shows the operation voltage results as a function of ALD thickness before and after the uHAST. Each sample was evaluated under the same stress conditions, thus demonstrating the correlation of voltage shift with thickness. The samples with ALD thicknesses of 15 and 20 nm both surpassed the lowest operation voltage shift after the stress test.

4. Future Aspects

In this study, an ALD fabricated Al2O3 thin film was used to establish a protection layer on the high-performance computing chip, which can also be applied to a bonding wire to form an insulating and heat dispatch layer. Detailed diagrams of these applications are shown in Figure 8. The figure shows the patent design. The original bonding wire is marked “31”, while the functional layers are marked “411” and “412”, i.e., the electromagnetic interference shielding layer or heat dispatch layer. The outer insulating layer is marked “42”. The methodology can also be used in 3D inkjet flexible printed touch sensors to enhance the sensor lifetime [28].

5. Conclusions

In this study, the overall protective layer using the atomic layer deposition technology established after encapsulation with electronic components obviously improved the lifetime in harsh environments. The excavator integrated circuit tested in this paper is prone to generate high heat during operation as a packaging technology in a flip-chip land grid array package type, whereby the stress caused by high temperature can easily destroy the interface between plastic substrates, solder, and metal mats, thereby reducing its service lifetime. The creation of an Al2O3 protective thin film layer with a thickness of 15 nm through atomic layer deposition technology significantly improved the component damage caused by thermal stress. The protective film with a thickness of 15 nm showed the same lowest operation voltage at 0.66 V before and after the 1000 h unbiased highly accelerated temperature and humidity stress test. This research showed that atomic layer deposition can be effectively used to block moisture and oxygen from entering electronic devices, to avoid their rapid deterioration. The protection layer can also improve the mechanical protection and reduce the damage caused by moving collisions, which has potential applications in organic light-emitting diodes, micro light-emitting diodes, and semiconductor packages for resisting moisture. In addition, the atomic layer deposition can be used to fabricate luminescent material layers, biomedicine sensor components, and water-resistant thin films for use in energy engineering and other applications related to coating technology.

6. Patents

The related patents described in this research are pending.

Author Contributions

Methodology, P.-C.C. and S.-M.C.; validation, H.-C.K. and F.-C.C.; writing—original draft preparation, Y.-A.L.; writing—review and editing, C.-C.T. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

The study did not involve humans or animals.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data are available from the corresponding author.

Acknowledgments

The authors acknowledge the reliability evaluation support of the IST group.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. The uHAST (a) and testing equipment (Agilent 9300 SOC series, (b)). Reprinted/adapted with permission from Ref. [23]. 2022, Integrated Service Technology Inc.
Figure 1. The uHAST (a) and testing equipment (Agilent 9300 SOC series, (b)). Reprinted/adapted with permission from Ref. [23]. 2022, Integrated Service Technology Inc.
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Figure 2. The function block diagram illustrating the functions of the14 nm ASIC.
Figure 2. The function block diagram illustrating the functions of the14 nm ASIC.
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Figure 3. Cross section diagram illustrating the conditions of the ALD coating structure (a) and the bottom view of the flip-chip land grid array (b).
Figure 3. Cross section diagram illustrating the conditions of the ALD coating structure (a) and the bottom view of the flip-chip land grid array (b).
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Figure 4. Schematic diagram of the ALD-coated ASIC (top); cross-section FIB image of 50 nm ALD-coated thin film.
Figure 4. Schematic diagram of the ALD-coated ASIC (top); cross-section FIB image of 50 nm ALD-coated thin film.
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Figure 5. Schematic diagram showing the packaged printed circuit board structure and the coated alumina protection layer.
Figure 5. Schematic diagram showing the packaged printed circuit board structure and the coated alumina protection layer.
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Figure 6. The test criteria and methodology of the open/short test.
Figure 6. The test criteria and methodology of the open/short test.
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Figure 7. The Al2O3 thicknesses versus the lowest operating voltage results before and after the 1000 h uHAST.
Figure 7. The Al2O3 thicknesses versus the lowest operating voltage results before and after the 1000 h uHAST.
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Figure 8. Schematic diagram of the bonding wire ALD-coated with Al2O3 thin film.
Figure 8. Schematic diagram of the bonding wire ALD-coated with Al2O3 thin film.
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Table
Table 1. Parameters of the ALD process.
Table 1. Parameters of the ALD process.
Step ProcessTime (s)Pressure (mTorr)RF (W)Gas Flow (sccm)Soak Time (s)
O2 treatment151003005
1st Ar purge3505000
TMA exposure1505000
2nd Ar purge3505000
Table
Table 2. The uHAST results as a function of Al2O3 thickness.
Table 2. The uHAST results as a function of Al2O3 thickness.
Test ItemNon-ALDThickness of ALD-Coated Al2O3 Thin Film
5 nm10 nm15 nm20 nm
Open test100%100%100%100%100%
Short test100%100%100%100%100%
Stand by current100%100%100%100%100%
Input voltage100%100%100%100%100%
Output voltage100%100%100%100%100%
Pull down/pull up100%100%100%100%100%
PLL function test0%0%50%100%100%
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MDPI and ACS Style

Chen, P.-C.; Chang, S.-M.; Kuo, H.-C.; Chang, F.-C.; Li, Y.-A.; Ting, C.-C. Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition. Coatings 2022, 12, 1308. https://doi.org/10.3390/coatings12091308

AMA Style

Chen P-C, Chang S-M, Kuo H-C, Chang F-C, Li Y-A, Ting C-C. Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition. Coatings. 2022; 12(9):1308. https://doi.org/10.3390/coatings12091308

Chicago/Turabian Style

Chen, Po-Chou, Shu-Mei Chang, Hao-Chung Kuo, Fu-Cheng Chang, Yu-An Li, and Chao-Cheng Ting. 2022. "Reliability Enhancement of 14 nm HPC ASIC Using Al2O3 Thin Film Coated with Room-Temperature Atomic Layer Deposition" Coatings 12, no. 9: 1308. https://doi.org/10.3390/coatings12091308

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