# Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications

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*Applied Sciences*: Invited Papers in Electrical, Electronics and Communications Engineering Section)

## Abstract

**:**

## 1. Introduction

## 2. Review

_{2}O

_{3}/BP sandwich structure with the PVCR exceeding 100 at room temperature. Kim et al. [28] considered an m-NDR device based on a BP/(ReS

_{2}+ HfS

_{2}) type-III double-heterostructure and its application to a ternary latch circuit capable of storing three logic states. Liang et al. [29] proposed a Λ-type NDR circuit based on a particular connection of three nMOS transistors with the same length and different widths of the channel. Gan et al. [30] considered a MOS-heterojunction bipolar transistor (HBT) N-type NDR circuit based on three n-channel MOS and one SiGe HBT device with two power supplies. At specific supply voltages, the NDR circuit provides the PVCR of about 8. Chung et al. [31] reported a three-terminal Si-based NDR device by epitaxially growing a resonant interband tunnel diode atop the emitter of a Si/SiGe HBT on a silicon substrate. The device provides an adjustable PVCR. Semenov [32] proposed a Λ-type NDR BJT-metal–oxide–semiconductor FET (MOSFET) circuit applied to periodic and chaotic mode oscillators. Gan et al. [33] considered a novel NDR circuit comprising nMOS transistors and HBT with application to inverter design based on 0.35 µm SiGe technology. Ulansky et al. [34] presented five electronic circuits of NDR VCOs based on a GaAs transistor and single-output BJT CM. Ulansky et al. [35] considered an NDR circuit comprising a FET and a simple BJT CM with multiple outputs that control the slope of the current-voltage curve by changing the number of CM outputs. Yang [36] investigated a resonant tunneling electronic circuit with reactance elements having high and multiple peak-to-valley current density ratios displayed in the NDR curve. Kadioglu [37] considered a monolayer structure based on vanadium phosphide with a current-voltage characteristic having the NDR region. Rathi et al. [38] observed an NDR region in the current-voltage curve in graphene oxide two-terminal device with precise control of carbon-oxygen ratio. The fabricated novel electronic device can find application in switches and oscillators. Sharma et al. [39] synthesized graphene oxide quantum dots based on graphene oxide, cysteine, and H

_{2}O

_{2}having N-type current-voltage characteristics with PVCR of 4.7. Shim et al. [40] demonstrated an NDR device on the base of a phosphorene/rhenium disulfide (BP/ReS

_{2}) heterojunction. It has a high PVCR of 4.2 at room temperature. The peak and valley currents are 3 and 0.7 nA, respectively.

- In most of the published studies, there is no possibility of controlling the PVCR. The PVCR control is available in the NDR devices considered in the studies [26,27,31,39], but the maximum current levels are in the nA and µA ranges. In the NDR circuit [17], the control of PVCR is possible in the mA range by changing the value of one of the resistors.

## 3. Two-Terminal NDR Circuits

_{c}, R

_{d}, an n-channel FET T

_{0}, a current mirror with m (m = 0, 1, 2,…) additional outputs (mirrored current sources), and a power supply V

_{1,2}.

_{2}. In Figure 2, the green curve corresponds to m = 0, the blue curve to m = 1, and the red curve to m = 2. As seen in Figure 2, the current-voltage characteristics have four regions. In the first (0, V

_{X}) and fourth (V

_{Z}, ∞) regions, the current I

_{1}depends only on the voltage V

_{1,2}. In these regions, all transistors are off. In the second region (V

_{X}, V

_{Y}), all transistors are on. Transistor T

_{0}operates in the ohmic region, and current I

_{1}increases. We should also note that the voltage V

_{Y}does not depend on the value of m, i.e., V

_{Yi}= V

_{Y}, i = 0, 1,…, m. In the third region (V

_{Y}, V

_{Z}), transistor T

_{0}operates in the saturation region and current I

_{1}decreases due to a decrease in the gate-source voltage.

_{1}consists of two currents in the NDR region: the current through resistor R

_{c}and m + 1 currents I

_{2}. The current through resistor R

_{c}is due to power supply V

_{1,2}and the drain-current I

_{D}of transistor T

_{0}. Thus, the current I

_{1}is given by

_{X}, V

_{Z}), the current I

_{1}is only due to the power supply voltage V

_{1,2}.

_{FE}, the currents I

_{2}and I

_{D}are approximately identical. The magnitude of the difference in currents I

_{2}and I

_{D}depends on the selected CM.

_{2}and I

_{D}[41]:

_{2}and I

_{D}.

_{A}, the currents I

_{2}and I

_{D}are related as follows [41]:

_{EB3}is the emitter-base voltage of transistor T

_{3}.

_{D}) and slave branch current (I

_{2}). The disadvantage is the difference in collector-emitter voltages V

_{EC}

_{1}and V

_{EC}

_{2}, which is equal to voltage V

_{EB}

_{3}.

_{4}equalizing the collector-emitter voltages of transistors T

_{1}and T

_{2}. Therefore, Equation (4) is reduced to [41]

_{1}in the NDR region is a function of the drain current of transistor T

_{0}, which is an n-channel FET. For the existence of the NDR region, the transistor T

_{0}must have a negative threshold voltage. Therefore, suitable types of transistors are JFET, depletion metal-oxide-semiconductor FET (DMOSFET), MESFET, HEMT, and PHEMT. As shown in Reference [35], the two-terminal NDR circuit with a multiple-output simple CM has an NDR effect when transistor T

_{0}is in saturation mode. In the circuits presented by Figure 3, Figure 4 and Figure 5, transistor T

_{0}should also operate in the saturation mode in the NDR region. Thus, to calculate the current I

_{1}, it is necessary to model the current I

_{D}for the selected type of transistor T

_{0}.

## 4. Modeling the Drain Current of Transistor T_{0}

_{1}in the NDR region, we should know the drain current I

_{D}of the transistor T

_{0}. The modeling of current I

_{D}depends on the type of transistor T

_{0}.

_{0}is a JFET, the Shockley equation well represents the drain current in the saturation region:

_{DSS}is the drain current of transistor T

_{0}at zero bias, V

_{P}is the negative pinch-off voltage, and V

_{GS}is the gate-source voltage.

_{0}is negative and consists of two parts: the voltage due to voltage divider R

_{c}, R

_{d}:

_{c}because of the current through this resistor, i.e.,

_{D}:

_{0}is a MESFET, we can model the current I

_{D}by one of the nonlinear large-signal models [42,43,44]. For example, the popular Curtice model in the saturation region is as follows [42]:

_{DS}is the drain-source voltage, and V

_{TH}is the threshold voltage.

_{DS}we find by applying Kirchhoff’s voltage law to the circuit of Figure 1.

_{D}is the voltage at the drain of transistor T

_{0}.

_{GS}from (11) into (14), we obtain

_{1,2}− V

_{D}) is equal to

_{EB}is the emitter-base voltage of BJT used in the current mirror.

_{D}:

_{D}for the selected two-terminal NDR circuit. Then, by substitution of I

_{D}into (3), (5), or (7), we can calculate the total current I

_{1}.

## 5. Modeling the Negative Differential Resistance

_{diff}for the two-terminal NDR circuits shown in Figure 3, Figure 4 and Figure 5. Substituting current I

_{1}from (3), (5), and (7) into (18) and taking the first derivative of function I

_{1}concerning variable V

_{1,2}, we obtain the following equations for the NDR:

- for the two-terminal NDR circuit with an MCCM,$${R}_{diff}={\left[\frac{d{I}_{D}}{d{V}_{1,2}}\left(\frac{\left(m+1\right)}{1+4/{h}_{FE}+2/{h}_{FE}^{2}}+\frac{{R}_{d}}{{R}_{c}+{R}_{d}}\right)+\frac{1}{{R}_{c}+{R}_{d}}\right]}^{-1},$$
- for the two-terminal NDR circuit with an MWCM,$${R}_{diff}={\left\{\frac{d{I}_{D}}{d{V}_{1,2}}\left[\left(m+1\right)\left(1-\frac{2}{{h}_{FE}^{2}+2{h}_{FE}+2}\right)\left(1+\frac{{V}_{CE2}-{V}_{CE1}}{{V}_{A}}\right)+\frac{{R}_{d}}{{R}_{c}+{R}_{d}}\right]+\frac{1}{{R}_{c}+{R}_{d}}\right\}}^{-1},$$
- and, for the two-terminal NDR circuit with a MIWCM,$${R}_{diff}={\left\{\frac{d{I}_{D}}{d{V}_{1,2}}\left[\left(m+1\right)\left(1-\frac{2}{{h}_{FE}^{2}+2{h}_{FE}+2}\right)+\frac{{R}_{d}}{{R}_{c}+{R}_{d}}\right]+\frac{1}{{R}_{c}+{R}_{d}}\right\}}^{-1}.$$

_{D}/dV

_{1,2}in (19)–(21) cannot be derived analytically. Therefore, we can replace this derivative with the ratio of ΔI

_{D}/ΔV

_{1,2}in the vicinity of the operating point. Then, calculate the increment of current ΔI

_{D}by (12) for a JFET and by (17) for a MESFET, HEMT, or PHEMT.

## 6. Applications

#### 6.1. Negative Differential Resistance Oscillators

_{1}, C

_{2}, and inductor L establish a resonant tank circuit. Capacitor C

_{a}is a feedback element used to improve the start-up of the oscillator. Capacitor C

_{b}serves as a noise killer at the drain of transistor T

_{0}.

_{2}.

_{of}is the offset frequency from the carrier frequency f

_{c}, PN(f

_{of}) is the oscillator phase noise at offset frequency f

_{of}, and P

_{dis}is the oscillator dissipation power. The second term allows us to compare oscillators operating at different frequencies. Thus, this criterion is invariant to the oscillator frequency.

_{diff}| is the absolute value of the NDR at the operating point calculated by (19)–(21), and R

_{Q}is the loaded tank circuit resistance at the resonance.

_{l}is the loaded quality factor of the tank circuit.

#### 6.2. Negative Differential Resistance Voltage-Controlled Oscillators

_{diff}[53].

_{1}and C

_{2}, two oppositely connected varactors, Var

_{1}and Var

_{2}, are used. A voltage source V

_{var}applies dc voltage to the cathodes of varactors. Resistor R

_{0}is linked with the voltage source V

_{var}, preventing the parallel tank circuit’s shunting.

## 7. Results and Discussion

#### 7.1. Simulation and Calculation of Current-Voltage Characteristics

_{0}, we use MMBFU310LT1 and BFT92W as transistors in current mirrors. We select the following resistor values: R

_{c}= 1 kΩ and R

_{d}= 2 kΩ.

_{X}, V

_{Y}, and V

_{Z}and currents I

_{X}and I

_{Z}for any value of m, two-terminal NDR circuit with MCCM has the smallest value of current I

_{Y}for any value of m, two-terminal NDR circuit with MIWCM has the most considerable value of current I

_{Y}for any value of m, and two-terminal NDR circuits with MCCM, MWCM, and MIWCM have almost linear dependence of current on voltage in the NDR region.

_{Z}is the same for all two-terminal NDR circuits, and current I

_{Y}is different, the slope of the current-voltage characteristics in the NDR region is higher for the greater value of current I

_{Y}. Therefore, we can order the absolute negative resistance values of various two-terminal NDR circuits according to the following inequality:

_{1}using (3), (5), and (7) with the following data of transistors MMBFU310LT1 and BFT92W: I

_{DSS}= 50 mA, V

_{P}= –3.5 V, V

_{A}= 11 V, and V

_{EB}

_{3}= 0.6 V. We use the same values of resistors R

_{c}and R

_{d}as in the simulation.

_{Y}and I

_{Z}and the relative accuracy of the I

_{Y}current calculation ΔI

_{Y}%, where ΔI

_{Y}% is given by

_{Y}calculation when m = 0 belongs to Equations (5) and (7) for the two-terminal NDR circuit with an MWCM and MIWCM. The highest accuracy of the current I

_{Y}calculation when m = 1, 2 has Equation (5) for the two-terminal NDR circuit with an MWCM. The worst accuracy of the current I

_{Y}calculation when m = 0, 1, 2 has Equation (3) for the two-terminal NDR circuit with an MCCM.

_{Y}. A practically zero error exists in calculating the current I

_{Z}.

_{0}is a PHEMT. We select ATF34143 as transistor T

_{0}and MRFC521 as transistors in BJT CM and choose the following resistor values: R

_{c}= 300 Ω and R

_{d}= 4 kΩ.

_{1}at voltages V

_{X}, V

_{Y}, and V

_{Z}using Equations (3), (5) and (7) with the following data of transistors ATF34143 [54] and MRFC521: b = 0.24 A/V

^{2}, V

_{TH}= –0.95 V, α = 4 V

^{−1}, λ = 0.09 V

^{−1}, h

_{FE}= 50, V

_{A}= 15 V, V

_{EB3}= 0.7 V. The values of resistors R

_{c}and R

_{d}are similar to those used in simulation.

_{Y}and I

_{Z}and the relative accuracy of the I

_{Y}current calculation ΔI

_{Y}%. The conclusions concerning the accuracy of the current I

_{Y}calculation for Table 6 are the same as those for Table 3.

_{D}by Formula (17) is quite high. Indeed, for all two-terminal NDR circuits at V

_{Y}= 2.8 V, the current I

_{D}(simulated) = 2.79 mA, and the current I

_{D}(calculated) = 2.67 mA. Therefore, ΔI

_{D}% = –4.5 %, where ΔI

_{D}% is the relative accuracy of calculating the current I

_{D}by formula

#### 7.2. Simulation of Negative Differential Resistance

_{1,2}= 4 V for two-terminal NDR circuits shown in Figure 3, Figure 4 and Figure 5 using the same input data as Table 4. As shown in Table 7, the smallest absolute value of NDR at the operating point has a two-terminal NDR circuit with an improved Wilson CM. The NDR circuit with a Wilson CM has a little greater absolute value of NDR. The circuit with a cascode CM has the most considerable absolute value of NDR for any m. Thus, the improved Wilson and Wilson CM oscillators have the best start-up conditions due to inequality (23).

#### 7.3. Simulation of Oscillator Characteristics

_{0}, we use ATF34143 and MRFC521 as transistors in BJT CM. We select chip inductor 0604HQ-1N1XJR (1.15 nH), and C

_{1}= C

_{2}= 1 pF, R

_{c}= 300 Ω, R

_{d}= 4 kΩ, C

_{b}= 300 nF, and V

_{1,2}= 4 V for all oscillators. We selected the value of capacitance C

_{a}from the condition of minimizing the phase noise of each oscillator.

_{L}) is infinite.

_{a}= 3 pF.

_{b}for the oscillator with multiple-output Wilson CM. We can see from Figure 21 that oscillator phase noise significantly depends on the value of C

_{b}. Indeed, when capacitance C

_{b}varies from 3 to 300 nF, phase noise decreases from −125.5 to −159.9 dBc/Hz. We can explain such a decrease in phase noise by reducing noise spectral density at the drain of transistor T

_{0}where capacitor C

_{b}is connected.

_{L}is connected through the capacitive divider to an oscillator output, as shown in Figure 22. Assume that R

_{L}= 50 Ω and C

_{CD}

_{1}= C

_{CD}

_{2}= 0.5 pF for the oscillators with MIWCM (m = 0, 1, 2) and MWCM (m = 0). For the oscillators with MCCM (m = 0, 1, 2) and MWCM (m = 1, 2), we selected C

_{CD}

_{1}= C

_{CD}

_{2}= 0.25 pF.

_{L}= 50 Ω. Table 9 shows the results of the oscillators’ simulation. As shown in Table 9, the best FOM values correspond to the same m sequence (0, 2, 1) as when R

_{L}= ∞ for oscillators with MCCM, MWCM, and MIWCM.

_{L}= ∞ and R

_{L}= 50 Ω.

#### 7.4. Simulation of VCO Characteristics

_{c}and R

_{d}, inductor type of L, and power supply voltage as in Section 7.3 when R

_{L}= ∞. We select varactors SMV1104-33. The tuning voltage V

_{d}is varied from 2 to 12 V for each VCO. Capacitance C

_{b}= 50 nF for VCOs with MCCM and C

_{b}= 300 nF for VCOs with MWCM and MIWCM.

_{a}from the condition of minimizing the phase noise of each VCO.

_{d}= 2 V and V

_{d}= 12 V. The best value of phase noise of −137.9 dBc/Hz at an offset frequency of 100 kHz and V

_{d}= 2 V has VCO with MIWCM when m = 2 (see Figure 23). The best value of phase noise of −152.5 dBc/Hz at an offset frequency of 100 kHz and V

_{d}= 12 V also has VCO with MIWCM but when m = 1 (see Figure 24).

_{d}= 2 V, the phase noise improvement occurs in the sequence of m = 0, 1, 2, i.e., the more mirrored currents, the lower the phase noise (see Figure 23). However, at V

_{d}= 12 V, the phase noise improvement occurs in m = 0, 2, 1, i.e., the highest phase noise occurs at m = 0, and the lowest at m = 1 (see Figure 24). The phase noise curve at m = 2 occupies an intermediate position.

_{L}= ∞, where f

_{min}and f

_{max}are the minimum and maximum frequency of VCO operation. As shown in Table 11, the VCO with MCCM has the best performance when m = 0. The VCO with MWCM achieves the best performance when m = 2 and VCO with MIWCM—when m = 1. For each value of m in Table 11, VCO with MWCM and MIWCM have significantly lower (i.e., better) FOM than VCO with MCCM. The broadest tuning frequency range, Δf = 370 MHz, has VCO with MCCM when m = 0. The lowest power consumption, P

_{dis}= 18.8 mW, also has VCO with MCCM when m = 0.

_{b}for VCO with multiple-output improved Wilson CM at V

_{d}= 2 V and V

_{d}= 12 V, respectively. We can see from Figure 25 and Figure 26 that VCO phase noise significantly depends on the value of capacitor C

_{b}. Indeed, when capacitance C

_{b}varies from 3 to 300 nF, phase noise decreases from −95.3 to −137.9 dBc/Hz at V

_{d}= 2 V and from −110.9 to −146.9 dBc/Hz at V

_{d}= 12 V. We can explain such a decrease in phase noise by reducing noise spectral density at the drain of transistor T

_{0}.

_{CD}

_{1}= C

_{CD}

_{2}= 0.5 pF for the VCOs with MWCM (m = 0, 1, 2), and MIWCM (m = 1, 2), and C

_{CD}

_{1}= C

_{CD}

_{2}= 0.25 pF for the VCOs with MCCM (m = 0, 1, 2) and MIWCM (m = 0).

_{a}= 30 pF. The VCO with MWCM achieves the best performance when m = 1 and C

_{a}= 20 pF, and the VCO with MIWCM—when m = 2 and C

_{a}= 9 pF.

_{L}= ∞ (see Table 11), for each value of m in Table 12, VCOs with MWCM and MIWCM have significantly lower FOM than VCO with MCCM.

_{d}= 2 V and V

_{d}= 12 V when R

_{L}= 50 Ω. The best value of phase noise of −139.0 dBc/Hz at an offset frequency of 100 kHz and V

_{d}= 2 V has VCO when m = 2 (see Figure 27).

_{d}= 12 V corresponds to m = 0 (see Figure 28).

_{L}= ∞ and R

_{L}= 50 Ω.

_{L}= 50 Ω) designed in this study has the lowest phase noise (−154.6 dBc/Hz at 0.1 MHz offset) and the best FOM (−221.6 dBc/Hz) among all oscillators. The latter is an indisputable advantage of the developed oscillator since CMOS oscillators have a much lower power consumption and usually have a significant advantage over GaN and GaAs oscillators in terms of the FOM value.

_{L}= 50 Ω) also has very low phase noise (−139.0, −137.0 dBc/Hz at 0.1 MHz offset) and is one of the best FOM (−205.1, −203.9 dBc/Hz at 0.1 MHz offset) in the tuning range. Thus, we can successfully use the proposed two-terminal circuits with NDR for constructing highly efficient microwave oscillators and VCOs.

## 8. Experimental Results

_{1,2}= 6 V and I

_{1}= 2.7 mA. Figure 29 shows the measured oscillator output spectrum at the fundamental frequency of 18.7 MHz with an output power of −14.8 dBm. We used a spectrum analyzer USB-SA44B (Battle Ground, WA, USA) and an Auburn P-20A RF probe (Auburn, WA, USA) with a 10:1 voltage ratio.

_{1,2}= 9 V and RBW = 100 kHz. As shown in Figure 31, the oscillation frequency is 944.4 MHz, and the power level of the output signal is −40.2 dBm. In estimating the actual power level, we should consider that the attenuation provided by the P-20A RF probe is 20 dB, and an insertion loss of the buffer amplifier is 2.2 dB.

## 9. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Acknowledgments

## Conflicts of Interest

## Abbreviations

BJT | Bipolar junction transistor |

CM | Current mirror |

CMOS | Complementary metal-oxide-semiconductor |

FET | Field-effect transistor |

HBT | Heterojunction bipolar transistor |

HEMT | High-electron-mobility transistor |

JFET | Junction field-effect transistor |

MCCM | Multiple-output cascode current mirror |

MESFET | Metal-semiconductor field-effect transistor |

MIWCM | Multiple-output improved Wilson current mirror |

MOSFET | Metal-oxide-semiconductor field-effect transistor |

MWCM | Multiple-output Wilson current mirror |

NDR | Negative differential resistance |

NI | Negative impedance |

nMOS | n-channel metal-oxide semiconductor |

PCB | Printed circuit board |

PHEMT | Pseudomorphic high-electron-mobility transistor |

pMOS | p-channel metal-oxide semiconductor |

PVCR | Peak-to-valley current ratio |

RBW | Resolution bandwidth |

RF | Radio frequency |

SiGe | Silicon-Germanium |

SRAM | Static random-access memory |

TFET | Tunnel field-effect transistor |

VCO | Voltage-controlled oscillator |

Nomenclature | |

α | Coefficient of the hyperbolic tangent function |

b | Transconductance |

f_{of} | Offset frequency |

FOM | Figure of merit |

h_{FE} | Bipolar transistor dc current gain |

I_{1} | Total dc current of the NDR circuit |

I_{2} | Mirrored current |

I_{D} | Current in the master branch of CM |

I_{DSS} | Zero-gate-voltage drain current of JFET |

I_{X} | Total dc current of the NDR circuit at point X |

I_{Y} | Total dc current of the NDR circuit at point Y |

I_{Z} | Total dc current of the NDR circuit at point Z |

λ | Channel length modulation coefficient |

m | Number of additional current sources (mirrored currents) |

M | Number of BJTs in multiple-output current mirror |

P_{dis} | Oscillator dissipation power |

PN | Oscillator phase noise |

Q_{l} | Loaded quality factor of the tank circuit |

$\rho $ | Characteristic impedance of the tank circuit |

R_{diff} | Differential resistance |

${R}_{diff}^{C}$ | Differential resistance of the NDR circuit with multiple-output cascode current mirror |

${R}_{diff}^{IW}$ | Differential resistance of the NDR circuit with multiple-output improved Wilson current mirror |

${R}_{diff}^{W}$ | Differential resistance of the NDR circuit with multiple-output Wilson current mirror |

R_{c}, R_{d} | Resistive voltage divider |

R_{Q} | Loaded tank circuit resistance at resonance |

T_{0} | Field-effect transistor in NDR circuits |

$\overline{{T}_{1},{T}_{M}}$ | Bipolar junction transistors in multiple-output current mirror |

V_{1,2} | Voltage between terminals 1 and 2 in NDR circuits |

V_{A} | Early voltage of a BJT in the current mirror |

V_{CE}_{1}, V_{CE}_{2} | Collector-emitter voltages of transistors T_{1} and T_{2} in the multiple-output Wilson current mirror |

V_{D} | Drain voltage of transistor T_{0} |

V_{DS} | Drain-source voltage of transistor T_{0} |

V_{EB} | Emitter-base voltage |

V_{EB}_{3} | Emitter-base voltage of transistor T_{3} in the multiple-output Wilson current mirror |

V_{GS} | Gate-source voltage of transistor T_{0} |

V_{P} | Pinch-off voltage of JFET T_{0} |

V_{TH} | Threshold voltage of transistor T_{0} (MESFET, HEMT, or PHEMT) |

V_{X} | Voltage between terminals 1 and 2 at point X |

V_{Y} | Voltage between terminals 1 and 2 at point Y |

V_{Z} | Voltage between terminals 1 and 2 at point Z |

ΔI_{Y} % | Relative accuracy of calculating current I_{Y} |

ΔI_{D} % | Relative accuracy of calculating current I_{D} |

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**Figure 2.**Current-voltage characteristics of a two-terminal NDR circuit with multiple-output current mirror; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 12.**Current-voltage characteristics of the two-terminal NDR circuit with multiple-output cascode current mirror; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 13.**Current-voltage characteristics of the two-terminal NDR circuit with multiple-output Wilson current mirror; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 14.**Current-voltage characteristics of the two-terminal NDR circuit with multiple-output improved Wilson current mirror; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 15.**(

**a**) Calculated current-voltage characteristics of the NDR circuit with multiple-output cascode current mirror in the NDR region; m = 0—green curve, m = 1—blue curve, m = 2—red curve. (

**b**) Calculated current-voltage characteristics of the NDR circuit with multiple-output Wilson current mirror in the NDR region; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 16.**Calculated current-voltage characteristics of the NDR circuit with multiple-output improved Wilson current mirror in the NDR region; m = 0—green curve, m = 1—blue curve, m = 2—red curve.

**Figure 17.**Current-voltage characteristics of the NDR circuit with multiple-output cascode current mirror; m = 0—purple curve, m = 1—blue curve, m = 2—red curve.

**Figure 18.**Current-voltage characteristics of the NDR circuit with multiple-output Wilson current mirror; m = 0—purple curve, m = 1—blue curve, m = 2—red curve.

**Figure 19.**Current-voltage characteristics of the NDR circuit with multiple-output improved Wilson current mirror; m = 0—purple curve, m = 1—blue curve, m = 2—red curve.

**Figure 20.**Phase noise versus offset frequency for the oscillator with multiple-output Wilson current mirror when R

_{L}= ∞; m = 0—purple curve, m = 1—blue curve, m = 2—red curve.

**Figure 21.**Phase noise versus offset frequency for the oscillator with multiple-output Wilson current mirror when R

_{L}= ∞; C

_{b}= 300 nF—red curve, C

_{b}= 30 nF—blue curve, C

_{b}= 3 nF—purple curve.

**Figure 23.**Phase noise versus offset frequency for VCO with multiple-output improved Wilson current mirror when V

_{d}= 2 V, R

_{L}= ∞; m = 0—purple curve (C

_{a}= 10 pF), m = 1—blue curve (C

_{a}= 7 pF), m = 2—red curve (C

_{a}= 6 pF).

**Figure 24.**Phase noise versus offset frequency for VCO with multiple-output improved Wilson current mirror when V

_{d}= 12 V, R

_{L}= ∞; m = 0—purple curve (C

_{a}= 10 pF), m = 1—blue curve (C

_{a}= 7 pF), m = 2—red curve (C

_{a}= 6 pF).

**Figure 25.**Phase noise versus offset frequency for the VCO with multiple-output improved Wilson current mirror when V

_{d}= 2 V, R

_{L}= ∞, and C

_{a}= 6 pF; C

_{b}= 3 nF—purple curve, C

_{b}= 30 nF—blue curve, C

_{b}= 300 nF—red curve.

**Figure 26.**Phase noise versus offset frequency for the VCO with multiple-output improved Wilson current mirror when V

_{d}= 12 V, R

_{L}= ∞, and C

_{a}= 6 pF; C

_{b}= 3 nF—purple curve, C

_{b}= 30 nF—blue curve, C

_{b}= 300 nF—red curve.

**Figure 27.**Phase noise versus offset frequency for VCO with multiple-output improved Wilson current mirror when V

_{d}= 2 V, R

_{L}= 50 Ω; m = 0—purple curve (C

_{a}= 13 pF), m = 1—blue curve (C

_{a}= 12 pF), m = 2—red curve (C

_{a}= 9 pF).

**Figure 28.**Phase noise versus offset frequency for VCO with multiple-output improved Wilson current mirror when V

_{d}= 12 V, R

_{L}= 50 Ω; m = 0—purple curve (C

_{a}= 9 pF), m = 1—blue curve (C

_{a}= 12 pF), m = 2—red curve (C

_{a}= 13 pF).

**Figure 29.**The output spectrum of the prototype oscillator with multiple-output improved Wilson current mirror (m = 1).

**Figure 30.**Printed circuit board assembly of the oscillator with multiple-output improved Wilson current mirror (m = 0).

**Figure 31.**The output spectrum of the oscillator with multiple-output improved Wilson current mirror (m = 0).

**Table 1.**Simulated parameters of current-voltage characteristics for different two-terminal NDR circuits (T

_{0}—JFET).

Type of NDR Circuit → | NDR Circuit with Multiple-Output | ||
---|---|---|---|

Parameter of I–V Characteristics ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

V_{X} (V) | 1.46 | 1.46 | 1.46 |

I_{X} (mA) | 0.5 | 0.5 | 0.5 |

V_{Y} (V) | 4.6 | 4.6 | 4.6 |

I_{Y} (mA)m = 0 | 4.3 | 4.4 | 4.5 |

I_{Y} (mA)m = 1 | 5.8 | 6.1 | 6.2 |

I_{Y} (mA)m = 2 | 7.1 | 7.6 | 7.8 |

V_{Z} (V) | 10.2 | 10.2 | 10.2 |

I_{Z} (mA) | 3.5 | 3.5 | 3.5 |

**Table 2.**Calculated parameters of current-voltage characteristics for different two-terminal NDR circuits (T

_{0}—JFET).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

Parameter of I–V Characteristics ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

V_{Y} (V) | 4.6 | 4.6 | 4.6 |

I_{Y} (mA)m = 0 | 4.6 | 4.6 | 4.7 |

I_{Y} (mA)m = 1 | 6.4 | 6.4 | 6.7 |

I_{Y} (mA)m = 2 | 8.1 | 8.2 | 8.6 |

V_{Z} (V) | 10.2 | 10.2 | 10.2 |

I_{Z} (mA) | 3.5 | 3.5 | 3.5 |

**Table 3.**The relative accuracy of the I

_{Y}current calculation for different two-terminal NDR circuits (T

_{0}—JFET).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

The Relative Accuracy of the I_{Y} Current Calculation ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

ΔI_{Y} %m = 0 | 6.5% | 4.3% | 4.3% |

ΔI_{Y} %m = 1 | 9.4% | 4.7% | 7.5% |

ΔI_{Y} %m = 2 | 12.3% | 7.3% | 9.3% |

**Table 4.**Simulated parameters of current-voltage characteristics for different two-terminal NDR circuits (T

_{0}—PHEMT).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

Parameter of I–V Characteristic ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

V_{X} (V) | 1.2 | 1.2 | 1.2 |

I_{X} (mA) | 0.3 | 0.3 | 0.3 |

V_{Y} (V) | 2.8 | 2.8 | 2.8 |

I_{Y} (mA), m = 0 | 4.9 | 5.1 | 5.2 |

I_{Y} (mA), m = 1 | 6.7 | 7.2 | 7.3 |

I_{Y} (mA), m = 2 | 8.3 | 9.1 | 9.3 |

V_{Z} (V) | 13.6 | 13.6 | 13.6 |

I_{Z} (mA) | 3.2 | 3.2 | 3.2 |

**Table 5.**Simulated parameters of current-voltage characteristics for different two-terminal NDR circuits (T

_{0}—PHEMT).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

Parameter of I–V Characteristic ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

V_{Y} (V) | 2.8 | 2.8 | 2.8 |

I_{Y} (mA), m = 0 | 5.6 | 5.7 | 5.8 |

I_{Y} (mA), m = 1 | 8.1 | 8.2 | 8.5 |

I_{Y} (mA), m = 2 | 10.5 | 10.8 | 11.1 |

V_{Z} (V) | 13.6 | 13.6 | 13.6 |

I_{Z} (mA) | 3.2 | 3.2 | 3.2 |

**Table 6.**The relative accuracy of the I

_{Y}current calculation for different two-terminal NDR circuits (T

_{0}—PHEMT).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

The Relative Accuracy of the I_{Y} Current Calculation ↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

ΔI_{Y} %, m = 0 | 12.5% | 10.5% | 10.3% |

ΔI_{Y} %, m = 1 | 17.3% | 12.2% | 14.1% |

ΔI_{Y} %, m = 2 | 20.9% | 15.7% | 16.2% |

**Table 7.**Simulated negative differential resistance for different two-terminal NDR circuits (T

_{0}—PHEMT).

Type of NDR Circuit → | Two-Terminal NDR Circuit with Multiple-Output | ||
---|---|---|---|

Negative Differential Resistance R _{diff} (kΩ)↓ | Cascode Current Mirror | Wilson Current Mirror | Improved Wilson Current Mirror |

m = 0 | −6.25 | −5.56 | −5.41 |

m = 1 | −3.07 | −2.70 | −2.67 |

m = 2 | −2.63 | −1.85 | −1.80 |

Type of Oscillator | Capacitance, C_{a}(pF) | Oscillator Characteristics | |||
---|---|---|---|---|---|

Frequency of Operation, f (MHz) | Phase Noise at an Offset Frequency of 10^{5} Hz, PN(dBc/Hz) | Power of Dissipation, P_{dis}(mW) | The Figure of Merit, FOM (dBc/Hz) | ||

MCCM (m = 0) | 8 | 2019 | −125.4 | 18.8 | −198.8 |

MCCM (m = 1) | 8 | 1627 | −104.4 | 25.2 | −174.6 |

MCCM (m = 2) | 25 | 1412 | −104.7 | 31.0 | −172.8 |

MWCM (m = 0) | 1 | 1958 | −150.7 | 19.6 | −223.6 |

MWCM (m = 1) | 1 | 1556 | −151.1 | 27.0 | −220.6 |

MWCM (m = 2) | 3 | 1335 | −159.9 | 33.9 | −227.1 |

MIWCM (m = 0) | 3 | 1951 | −145.0 | 19.8 | −217.8 |

MIWCM (m = 1) | 1 | 1554 | −152.0 | 27.4 | −221.5 |

MIWCM (m = 2) | 2 | 1333 | −152.6 | 34.5 | −219.7 |

Type of Oscillator | Capacitance, C_{a}(pF) | Oscillator Characteristics | |||
---|---|---|---|---|---|

Frequency of Operation, f (MHz) | Phase Noise at an Offset Frequency of 10^{5} Hz, PN(dBc/Hz) | Power of Dissipation, P_{dis}(mW) | The Figure of Merit, FOM (dBc/Hz) | ||

MCCM (m = 0) | 28 | 1925 | −116.1 | 18.8 | −189.1 |

MCCM (m = 1) | 15 | 1582 | −103.9 | 25.2 | −173.9 |

MCCM (m = 2) | 25 | 1384 | −90.0 | 31.0 | −157.9 |

MWCM (m = 0) | 15 | 1800 | −143.1 | 19.6 | −215.3 |

MWCM (m = 1) | 3 | 1519 | −149.8 | 27.0 | −219.1 |

MWCM (m = 2) | 7 | 1310 | −154.6 | 33.9 | −221.6 |

MIWCM (m = 0) | 7 | 1800 | −144.9 | 19.8 | −217.0 |

MIWCM (m = 1) | 5 | 1483 | −150.8 | 27.4 | −219.8 |

MIWCM (m = 2) | 2 | 1294 | −148.3 | 34.5 | −215.2 |

Oscillator Load, R_{L} (Ω) | The Figure of Merit (dBc/Hz) | ||
---|---|---|---|

Type of Oscillator | |||

MCCM | MWCM | MIWCM | |

∞ | −198.8 | −227.1 | −221.5 |

50 | −189.1 | −221.6 | −219.8 |

Type of VCO | Capacitance, C_{a}(pF) | VCO Characteristics | ||||
---|---|---|---|---|---|---|

f_{min}, f_{max}V _{d} = 2 V, 12 V(MHz) | Δf (MHz) | PN (f_{of} = 10^{5} Hz)V _{d} = 2 V, 12 V(dBc/Hz) | P_{dis}(mW) | FOM V _{d} = 2 V, 12 V(dBc/Hz) | ||

MCCM (m = 0) | 5 | 1616, 1986 | 370 | −99.2, −139.1 | 18.8 | −170.6, −212.3 |

MCCM (m = 1) | 12 | 1408, 1631 | 223 | −97.6, −100.4 | 25.2 | −166.6, −170.6 |

MCCM (m = 2) | 12 | 1262, 1410 | 148 | −96.8, −90.4 | 31.0 | −163.9, −158.5 |

MWCM (m = 0) | 10 | 1571, 1912 | 341 | −132.5, −143.2 | 19.6 | −203.5, −215.9 |

MWCM (m = 1) | 7 | 1366, 1556 | 190 | −135.3, −151.2 | 27.0 | −203.7, −220.7 |

MWCM (m = 2) | 7 | 1222, 1339 | 117 | −137.8, −148.1 | 33.9 | −204.2, −215.3 |

MIWCM (m = 0) | 10 | 1569, 1911 | 342 | −132.4, −144.2 | 19.8 | −203.3, −216.8 |

MIWCM (m = 1) | 7 | 1364, 1554 | 190 | −136.7, −152.5 | 27.4 | −205.0, −222.0 |

MIWCM (m = 2) | 6 | 1222, 1337 | 115 | −137.9, −146.9 | 34.5 | −204.3, −214.0 |

Type of Oscillator | Capacitance, C_{a}(pF) | VCO Characteristics | ||||
---|---|---|---|---|---|---|

f_{min}, f_{max}V _{d} = 2 V, 12 V(MHz) | Δf (MHz) | PN (f_{of} = 10^{5} Hz)V _{d} = 2 V, 12 V(dBc/Hz) | Power of Dissipation, P_{dis}(mW) | FOM V _{d} = 2 V, 12 V(dBc/Hz) | ||

MCCM (m = 0) | 30 | 1555, 1915 | 360 | −99.0, −98.3 | 18.8 | −170.1, −171.2 |

MCCM (m = 1) | 15 | 1376, 1586 | 210 | −97.3, −88.2 | 25.2 | −166.1, −158.2 |

MCCM (m = 2) | 30 | 1235, 1380 | 145 | −97.8, −88.8 | 31.0 | −164.7, −156.7 |

MWCM (m = 0) | 12 | 1510, 1791 | 281 | −111.7, −134.6 | 19.6 | −182.4, −206.7 |

MWCM (m = 1) | 20 | 1325, 1480 | 245 | −134.7, −141.9 | 27.0 | −202.8, −211.0 |

MWCM (m = 2) | 18 | 1191, 1298 | 107 | −144.0, −128.4 | 33.9 | −210.2, −195.4 |

MIWCM (m = 0) | 13 | 1532, 1841 | 309 | −130.4, −138.4 | 19.8 | −201.1, −210.7 |

MIWCM (m = 1) | 12 | 1325, 1478 | 153 | −135.6, −136.1 | 27.4 | −203.7, −205.1 |

MIWCM (m = 2) | 9 | 1191, 1295 | 104 | −139.0, −137.0 | 34.5 | −205.1, −203.9 |

Oscillator Load, R_{L} (Ω) | The Figure of Merit (dBc/Hz) | ||
---|---|---|---|

Type of Oscillator | |||

MCCM | MWCM | MIWCM | |

∞ | −170.6, −212.3 | −204.2, −215.3 | −205.0, −222.0 |

50 | −170.1, −171.2 | −202.8, −211.0 | −205.1, −203.9 |

Oscillator (VCO) | Technology | Oscillation Frequency (GHz) | Offset Frequency (MHz) | Phase Noise (dBc/Hz) | Dissipation Power (mW) | Figure of Merit (dBc/Hz) |
---|---|---|---|---|---|---|

[55] | GaN HEMT | 7.9 | 1 | −135 | 1456 | −181.3 |

[56] | GaN HEMT | 6.45 ÷ 7.55 | 1 | −132 | 198 | −185.9 |

[57] | GaN HEMT | 5.2 | 1 | −125.7 | 16 | −188 |

[58] | GaAs PHEMT | 37.608 | 1 | −112.31 | 130 | −182.7 |

[59] | GaN HEMT | 1.93 | 1 | −149 | 400 | −189 |

[60] | GaN HEMT | 7.26 | 1 | −122.48 | 18.33 | −187 |

[61] | GaN HEMT | 8.8 | 1 | −124.55 | 21.6 | −190.1 |

[62] | SiGe | 8.99 | 0.1 | −120.05 | 18 | −206.58 |

[63] | GaN HEMT | 4.95 | 1 | −143 | 320 | −191.84 |

[64] | InGaP HBT | 5.05 ÷ 6.35 | 0.1 | −103, −95 | 350 | −171.6, −165.6 |

[65] | CMOS | 1.36 ÷ 1.86 | 0.1 | −121 | 2.7 | −202 |

[66] | CMOS | 8 | 1 | −134.3 | 6.6 | −204 |

[67] | CMOS | 7.4 ÷ 8.4 | 10 | −151.5 | 29 | −194.3, −195.6 |

[68] | CMOS | 2.28 ÷ 2.59 | 0.1 | −103.6, −125.5 | 1.9 | −188, −211 |

[69] | CMOS | 14 ÷ 18 | 1 | −113, −110 | 24 | −−182.1, −181.3 |

[70] | BiCMOS | 15 | 1 | −124 | 70 | −189 |

[71] | BiCMOS | 29.6 ÷ 36.5 | 1 | −97 | 20 | −180 |

This work | GaAs PHEMT, BJT | 1.31 | 0.1 | −154.6 | 33.9 | −221.6 |

This work | GaAs PHEMT, BJT | 1.367 ÷ 1.556 | 0.1 | −139.0, −137.0 | 34.5 | −205.1, −203.9 |

Circuit Elements | Part Numbers and Nominal Values |
---|---|

Transistor T_{0} | BF245B |

$\mathrm{Transistors}\text{}\overline{{T}_{1},{T}_{M}}$ | 2N3906 |

Inductor L | 1 μH |

Capacitor C_{a} | 200 pF |

Capacitor C_{b} | 10 nF |

Capacitors C_{1}, C_{2} | 60 pF |

Resistor R_{c} | 1 kΩ |

Resistor R_{d} | 4 kΩ |

Circuit Elements | Part Numbers and Nominal Values |
---|---|

Transistor T_{0} | BF245B |

$\mathrm{Transistors}\text{}\overline{{T}_{1},{T}_{M}}$ | BFT92W |

Inductor L | ELJQF8N2 (8.2 nH) |

Capacitor C_{a} | C0603C0G1E100D (10 pF) |

Capacitor C_{b} | C0603Y5V1C103Z (10 nF) |

Capacitors C_{1}, C_{2} | C0603C0G1E0R5C (0.5 pF) |

Resistor R_{c} | ERJ1GEJ102 (1 kΩ) |

Resistor R_{d} | ERJ1GEJ392 (3.9 kΩ) |

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## Share and Cite

**MDPI and ACS Style**

Ulansky, V.; Raza, A.; Milke, D.
Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications. *Appl. Sci.* **2021**, *11*, 9815.
https://doi.org/10.3390/app11219815

**AMA Style**

Ulansky V, Raza A, Milke D.
Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications. *Applied Sciences*. 2021; 11(21):9815.
https://doi.org/10.3390/app11219815

**Chicago/Turabian Style**

Ulansky, Vladimir, Ahmed Raza, and Denys Milke.
2021. "Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications" *Applied Sciences* 11, no. 21: 9815.
https://doi.org/10.3390/app11219815