An Artificial Neural Network Based on Oxide Synaptic Transistor for Accurate and Robust Image Recognition

Abstract

Synaptic transistors with low-temperature, solution-processed dielectric films have demonstrated programmable conductance, and therefore potential applications in hardware artificial neural networks for recognizing noisy images. Here, we engineered AlO_x/InO_x synaptic transistors via a solution process to instantiate neural networks. The transistors show long-term potentiation under appropriate gate voltage pulses. The artificial neural network, consisting of one input layer and one output layer, was constructed using 9 × 3 synaptic transistors. By programming the calculated weight, the hardware network can recognize 3 × 3 pixel images of characters z, v and n with a high accuracy of 85%, even with 40% noise. This work demonstrates that metal-oxide transistors, which exhibit significant long-term potentiation of conductance, can be used for the accurate recognition of noisy images.

1. Introduction

Artificial neural networks (ANNs) have achieved remarkable success in machine vision tasks such as image recognition, driving the demand for specialized hardware [1,2,3,4]. Emerging devices combining storage and computational functionalities have become the focus of research, including memristors [5,6,7], synaptic transistors [8,9,10,11], and ferroelectric transistors [12,13,14,15]. By emulating their behavior, it is possible to instantiate neural networks capable of executing complex tasks like image recognition directly at the hardware level. However, the practical implementation of neuromorphic computing using these in-memory computation devices presents significant challenges, particularly maintaining robust operation under non-ideal environmental conditions.

Oxide-based synaptic transistors are promising candidates for the implementation of ANNs [10]. They leverage the formation of the electric double layer in the oxide electrolyte that enables substantial modulation of the channel conductance, thereby mimicking the biological synaptic plasticity [16,17,18]. This property means they are suitable for use as weights in connections of the network, especially when dealing with high-noise image recognition. Furthermore, amorphous oxide films are attractive because they are compatible with large-area semiconductor device processes that can be integrated into device networks.

In this study, we employed an InO_x synaptic transistor with an AlO_x solid electrolyte as the dielectric layer and 9 × 3 transistors were used to construct a single-layer neural network model. The synaptic transistor exhibited pronounced long-term potentiation, which enables the construction of networks and recognizes images under high-noise conditions.

2. Materials and Methods

The method of film deposition has been reported in a previous study [19]. The AlO_x precursor was synthesized by dissolving aluminum nitrate hydrate, nitric acid and ammonium hydroxide in hydrogen peroxide, and it was spin-coated on a heavily doped silicon wafer. The sample was annealed on a hot plate at 300 °C for 30 min. After repeating this process five times, the thickness of the AlO_x film reached about 30 nm. Then, the InO_x precursor was synthesized by dissolving indium nitrate hydrate in deionized water and was spin-coated on the AlO_x film. The sample was annealed on a hot plate at 230 °C for 2 h. The Al top electrodes were deposited on the InO_x film to fabricate an AlO_x/InO_x capacitor. For the fabrication of the transistor, the InO_x film was patterned by photolithography and etched with hydrochloric acid. The InO_x films were patterned to reduce the gate leakage current. Subsequently, the sample was annealed on a hot plate at 100 °C for 10 min to repair the damage from the etching process. Then, Al was used as source/drain electrodes to fabricate bottom-gate, top-contact transistors. The films and devices were characterized by a semiconductor parameter analyzer and an electrochemical impedance analyzer. The composition of the SiO₂/AlO_x thin film was characterized by secondary-ion mass spectroscopy (SIMS), which measured the depth profiles with a 2 kV Cs+ sputter beam. Cross-sectional transmission electron microscope (TEM) images were obtained with the JEM 2100F system operating at 200 kV and the samples were prepared on silicon using focused-ion-beam techniques.

3. Results

Figure 1a shows the scheme of the AlO_x/InO_x capacitor. The capacitor is equivalent to the circuit that contains three parallel RC in series, representing the dielectric layer, electric double layer (EDL) and semiconductor layer. The EDL is formed by the accumulation of protons at the interface between AlO_x and InO_x under positive bias at the bottom electrode. Thus, the impedance and the capacitance are dependent on the frequency and the bottom electrode bias, as shown in Figure 1b,c. The measured capacitances were determined by the complex impedance and represent the response of the film to the AC voltage with various frequencies and DC biases. The capacitive components in the equivalent circuit represent the corresponding charge storage and release processes within the thin film. For example, the EDL capacitance C_EDL represents the storage and release of ions at the interface between AlO_x and InO_x. Due to the formation of the EDL, the total capacitance of the capacitor increases as the bias increases. Meanwhile, induced by the EDL, the carriers in InO_x accumulate at the interface and increase the conductance of InO_x. Thus, the total impedance of the capacitor decreases as the bias increases. At negative bias, due to the absence of EDL formation, the impedance and capacitance are close at bias values of 0 V and −3 V.

Therefore, the conductance of the transistor can be modulated in a wide range by V_g pulse stimulation, as shown in Figure 1e. The gate leakage current at V_g = 2 V is about 2.9 × 10⁻⁹ A, which is lower than I_d = 6.3 × 10⁻⁵ A. The results can confirm that the electrical insulation characteristics of the AlO_x layer are good enough for the gate dielectric layer. This is because the capacitance increases when the frequency decreases at a bias value of 3 V, as shown in Figure 1c. It indicates the interfacial ion concentration would increase with a reducing scan rate. Corresponding to the low frequency (0.1–10 Hz) with large capacitance, an appropriate scanning rate (in Figure 1e, the scan rate is 0.41 V/s) can effectively ensure the formation of EDL and the plasticity of the device. Under a positive gate voltage, the ions in AlO_x move towards the interface. Due to the ion accumulation, the electric double layer (EDL) is formed near the interface. In addition, the ions may be adsorbed on the interface electrochemically. The large capacitance of the EDL and the charge from adsorption stimulate the channel carrier and increase the current. Depending on the decay time of the accumulated ions, the increased current can be maintained for a long time (serving as long-term potentiation) or a short time (serving as short-term potentiation). By applying the V_g pulses, the current increases with the continuous pulse stimulation, demonstrating short-term potentiation, as shown in Figure 1f. After the pulses, the current decays but remains above the initial value, indicating long-term potentiation. Various pulse widths and intervals would affect the potentiation behaviors. As shown in Figure 1g, when increasing the pulse width from 20 ms to 70 ms, the drain current stimulated by 30 gate pulses increases from 0.72 μA to 1.10 μA. As shown in Figure 1h, when increasing the pulse interval from 20 ms to 70 ms, the drain current stimulated by 30 gate pulses decreases from 0.52 μA to 0.37 μA. By increasing the pulse width and reducing the pulse interval, the accumulated ions at the interface increased, resulting in a higher drain current. The paired pulse facilitation (PPF) behavior can be observed in Figure 1i. The PPF index can be fitted by the double-phase exponential function as $\mathrm{P}\mathrm{P}\mathrm{F} \mathrm{i}\mathrm{n}\mathrm{d}\mathrm{e}\mathrm{x}=1+A_1\exp \left(-∆t/{\tau }_1\right)+A_2\exp \left(-∆t/{\tau }_2\right)$. ${\tau }_1$ and ${\tau }_2$ are estimated to be 12.3 ms and 284.3 ms. The relaxation time indicates that the PPF is mainly related to ion response at 1–10 Hz.

To characterize the hydrogen in the alumina, transmission electron microscopy (TEM) of Si/AlO_x/InO_x and secondary ion mass spectrometry (SIMS) of SiO₂/AlO_x were performed. As shown in Figure 2a, the alumina was amorphous with inapparent pinholes. The pinholes are probably formed due to the decomposition of nitric acid and ammonium hydroxide in the precursor. The amorphous structure may provide a transport channel for the hydrogen in the film. The hydrogen concentration was related to the annealing temperature. Figure 2b,c show the hydrogen and aluminum intensity with the film annealed at 200 °C and 300 °C. The hydrogen concentration decreases when the annealing temperature increases from 200 °C to 300 °C. It indicates that the source of hydrogen ions is probably the residual decomposition of the precursor. The absorbed moisture is also a possible source because at the start of sputtering, the surface shows an obvious hydrogen intensity. This means that the moisture in the atmosphere was adsorbed by the film. To characterize the influence of temperature on the retention time, we analyzed the drain current stimulated by a gate pulse at various temperatures as shown in Figure 2d. The decay of the current was fitted with the exponential function, i.e., $I_{\mathrm{d}}=I_{\mathrm{d}1}\exp \left(-t/\tau \right)+I_{\mathrm{d}0}$. The extracted time constant τ as a function of the temperature is shown in Figure 2e. When increasing the temperature from −50 °C to 50 °C, τ decreases from 2.41 s to 0.69 s. As the temperature increases, the ions migrate more easily. Thus, the carrier induced by the electric double layer decays faster after the pulse at a high temperature, resulting in a shorter retention time for the conductance.

The ability of long-term potentiation to provide the weight update function is essential in artificial neural networks (ANNs). We built an ANN that can recognize three types of images with 3 × 3 pixels like characters z, v and n. The training and test datasets contain 9999 and 999 sets of pixel data, respectively. The framework of the network contains one input layer (nine inputs) and one output layer (three outputs), as shown in Figure 3a. The input layer and output layer are fully connected; this means that the output value $o_{\mathrm{n}}$ is the sum of all inputs, i.e., $o_{\mathrm{n}}={\sum }_{\mathrm{m}=1}^9\left(p_{\mathrm{m}}\times G_{\mathrm{m},\mathrm{n}}\right)$, where $p_{\mathrm{m}}$ is the normalized grayscale values used as input and $G_{\mathrm{m},\mathrm{n}}$ is the connection weight. Considering that the conductance of a transistor is positive, $G_{\mathrm{m},\mathrm{n}}$ is restricted to being greater than zero. The activation function is $y_{\mathrm{n}}=1/\left[1+\mathrm{e}\mathrm{x}\mathrm{p}\left(-o_{\mathrm{n}}\right)\right]$ (Sigmoid function). The pixel grayscale was introduced with noise, which is expressed as $p_{\mathrm{m}}=1-\sigma p_{\mathrm{n}} \mathrm{a}\mathrm{n}\mathrm{d} 0+\sigma p_{\mathrm{n}}$ for the black and white pixel, respectively, where $\sigma$ is the degree of noise and $p_{\mathrm{n}}$ is the random noise in the range of zero to one. Through training the ANN in software using the backpropagation algorithm [20], the weights in the ANN are updated from the random values (Figure 3b) to converge (Figure 3c). The accuracy is 100% for the images when $\sigma =0.4$. The weight mapping indicates that three transistors are needed to update the weight.

For implementation in devices, the normalized grayscale values $p_{\mathrm{m}}$ were converted to the drain voltage, when $0{<p}_{\mathrm{m}}<0.1$, $V_{\mathrm{d}}=0.1 \mathrm{V}$, and when $0.9{<p}_{\mathrm{m}}<1$, $V_{\mathrm{d}}=1 \mathrm{V}$. The conductance of the transistors was used as the connection weight. The sum of the drain currents can represent the output value, i.e., $o_{\mathrm{n}}={\sum }_{\mathrm{m}=1}^9\left(V_{\mathrm{d}}\times G_{\mathrm{m},\mathrm{n}}\right)={\sum }_{\mathrm{m}=1}^9{I}_{\mathrm{d}\mathrm{m},\mathrm{n}}$, as shown in Figure 4a. By comparing the values of o₁, o₂, and o₃, the images can be recognized. According to the simulation results, the corresponding devices can be trained using gate voltage pulses. The initial conductance mapping was carried out in the range of about 10 nS to 80 nS (Figure 4b) and updated to a similar conductance distribution. The corresponding conductance was in the range of about 1 μS to 5 μS (Figure 4c). Although the device size is relatively large, it can be further scaled down after optimizing the following process: (1) the spin-coating process of the InO_x film for improving the film’s quality and uniformity; (2) the photolithography process for high exposure resolution; (3) the etching process to eliminate the nonideal etching profile, like undercut and overetching; (4) the metal lift-off process to achieve a high yield rate.

A detailed training process for hardware device arrays was implemented in a similar way to the simulation in the software. The drain current with a period time of 3 s served as one epoch. The devices were set to an initial state of about 10 nS. When the image pixel data were input, namely the corresponding drain bias, the I_d-t curves were measured. For the transistors that did not require updated conductance, no gate pulse was applied. For the transistors that required updated conductance, gate pulses (width: 90 ms, amplitude: 3 V) were applied. Examples of the I_d-t curves at various drain voltages are shown in Figure 5a. Figure 5b,c show the process of recognizing image z. The grayscale values were inputted as V_d into each column, and the I_d of each row were summed to obtain o_n. After 30 epochs, the conductance of the corresponding devices was enhanced to satisfy the need for image recognition, as shown in Figure 5d.

Figure 6a shows the recognition accuracy when the images have various noises. When increasing the conductance of corresponding devices, the accuracy increases with each epoch. The accuracy can reach 100% by epoch 4 for these three images without noise (Figure 6a, black curve). With an increasing noise degree $\sigma$, the accuracy decreases. When $\sigma =0.4$, the accuracy can reach 85% by epoch 19 (Figure 6a, purple curve). The decrease in the accuracy with $\sigma$ is probably because of the variation in conductance. The effect of the ΔG on accuracy has been estimated as shown in Figure 6b. The definition of ΔG in Figure 6b is the ratio of the conductance with inputting gate voltage pulses and the conductance without inputting gate voltage pulses. The accuracy tends to increase with ΔG when it is below 100, and then it remains almost constant. Figure 6c–e depict the evolution of the output, namely the summed current, over the course of training. When the input image is z, the corresponding summed current o₁ increases with training and surpasses the o₂ and o₃, indicating successful recognition of image z. With the same weight mapping, the corresponding summed current can increase to the maximum among the three outputs when either image v or n is inputted.

In addition to the implementation of image recognition, conductance can be used to map characters. The conductance at appropriate locations was modulated by gate pulses (amplitude: 10 V, width: 50 ms) and read at V_d = 0.1 V after 10 s. The 3 × 3 devices can represent images such as z, v, and n (Figure 7). The contrast ratio, namely the current ratio, can attain a value of about 10⁴.

4. Conclusions

The synaptic transistors with AlO_x as the electrolyte layer and InO_x as the semiconductor layer were used to implement an ANN for image recognition. Through controlling the ion accumulation at the interface by gate voltage, the conductance of the AlO_x/InO_x transistors shows long-term potentiation. We implemented an ANN comprising 9 × 3 synaptic transistors. By constructing appropriate weight maps, the network shows a high accuracy of 85% in recognizing three types of 3 × 3 pixel images with a high noise of 40%. This work presents a feasible approach for oxide synaptic transistors to construct a network and recognize noisy images.