Emerging Memory Materials and Devices

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "A:Physics".

Deadline for manuscript submissions: 30 September 2024 | Viewed by 636

Special Issue Editors

School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China
Interests: flexible/stretchable electronics; nanoelectronics; neuromorphic computing

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Guest Editor
Department of Materials Science and Engineering, National University of Singapore, Singapore 117575, Singapore
Interests: RRAM; FeRAM; synaptic emulation; neuromorphic computing

Special Issue Information

Dear Colleagues,

With the advent of the “post-Moore era”, rapid developments in the fields of the Internet of Things, big data, and artificial intelligence have challenged the traditional “von Neumann” computing architecture. Brain-inspired neuromorphic computing emulates the structure of the human brain, which is capable of parallel processing and distributed computing of complex information data while maintaining high efficiency and ultra-low power consumption. Emerging memory devices, including resistive random-access memory (RRAM), ferroelectric random access memory (FeRAM), and magnetoresistive random access memory (MRAM), are considered to be ideal hardware implementations of neuromorphic computing due to improved performance, lower power consumption, and higher data density. Over the past few decades, great efforts have been made in the development of emerging memory materials, devices, and circuits for synaptic emulation, logic operations, and neuromorphic computing. However, there are still extensive challenges to address before demonstrating the hardware implementation of neuromorphic computing. These challenges may include the operational reliability of memory devices, the biorealistic realization of synaptic functions, the algorithm and circuit of the artificial neural network, and so on. To overcome those obstacles, the study of material selection, physical mechanism, and circuit construction are still necessary. This Special Issue will cover topics that involve emerging memory materials, devices, and circuits in the context of synaptic emulation and neuromorphic computing.

Dr. Qilin Hua
Dr. Tao Zeng
Guest Editors

Manuscript Submission Information

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Keywords

  • emerging memory materials and devices: RRAM, FeRAM, MRAM
  • artificial synapse/neuron
  • artificial sensor system
  • artificial neural networks
  • in-memory computing
  • neuromorphic computing

Published Papers (1 paper)

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Research

16 pages, 6061 KiB  
Article
DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks
by Ruiyong Zhao, Zhenghui Gong, Yulan Liu and Jing Chen
Micromachines 2024, 15(5), 617; https://doi.org/10.3390/mi15050617 - 30 Apr 2024
Viewed by 446
Abstract
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumulate (MAC) operations within the SRAM array. This design [...] Read more.
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply–Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design. Full article
(This article belongs to the Special Issue Emerging Memory Materials and Devices)
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