High-Performance Embedded Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 August 2024 | Viewed by 1615

Special Issue Editors


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Guest Editor
Department of Electronic Engineering, University of Rome Tor Vergata, 00133 Rome, Italy
Interests: FPGA; ASIC; machine learning; digital signal processing; embedded systems
Special Issues, Collections and Topics in MDPI journals

E-Mail Website
Guest Editor
Department of Electronic Engineering, University of Rome “Tor Vergata”, 00133 Rome, Italy
Interests: digital signal processing; machine learning; digital architectures; digital electronics for space

Special Issue Information

Dear Colleagues,

Non-functional constraints such as execution time, memory capacity, and energy consumption are a significant challenge for designers in the field of embedded systems. New applications are being proposed that integrate an increasing variety of functionality into everyday objects, imposing several additional requirements on embedded system designers, as follows:

  • Increased computing workloads, elaborating and fusing multiple sensor data, even by advanced machine learning techniques;
  • Reduced power consumption, allowing for smaller batteries and renewable power sources;
  • Faster interaction with the environment, necessitating a high performance in data processing that is often reached by hardware implementations.

As an example, the physical dimensions and power consumption of embedded systems for the Internet of Things are frequently of interest. However, the need for small systems does not prevent higher demands for functionality and speed. Simultaneously, designers must respond to a growing need for more powerful edge systems capable of managing vast fleets of connected devices while running resource-intensive algorithms such as sensor fusion, feedback control, and machine learning. Developers must grasp the nature of embedded systems architectures and strategies for extracting their full performance potential in this environment, as well as embedded design in general.

This Special Issue invites researchers to contribute original research, case studies, and reviews that address topics related to designs and applications of high-performance digital embedded systems.

The topics relevant for this Special Issue include (but are not limited to):

  • Low-power IoT applications;
  • Embedded FPGA and SoC implementations;
  • Embedded ASIC implementations;
  • Machine learning on the Edge;
  • Efficient data-processing algorithms

Dr. Sergio Spanò
Prof. Dr. Gian Carlo Cardarilli
Guest Editors

Manuscript Submission Information

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Keywords

  • embedded systems
  • digital electronics
  • low-power
  • IoT
  • edge computing
  • FPGA
  • ASIC
  • systems-on-chips
  • machine learning

Published Papers (1 paper)

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Research

15 pages, 1322 KiB  
Article
Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes
by Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Angioli, Saeid Jamili and Mauro Olivieri
Electronics 2023, 12(17), 3574; https://doi.org/10.3390/electronics12173574 - 24 Aug 2023
Cited by 2 | Viewed by 1006
Abstract
High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software techniques, it is possible to increase the overall reliability and safety of these systems by [...] Read more.
High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software techniques, it is possible to increase the overall reliability and safety of these systems by designing embedded architectures that can continue to function correctly in the event of a failure or malfunction. In this work, we fully investigate the integration of a configurable hardware vector acceleration unit in the fault-tolerant RISC-V Klessydra-fT03 soft core, introducing two different redundant vector co-processors coupled with the Interleaved-Multi-Threading paradigm on which the microprocessor is based. We then illustrate the pros and cons of both approaches, comparing their impacts on performance and hardware utilization with their vulnerability, presenting a quantitative large-fault-injection simulation analysis on typical vector computing benchmarks, and comparing and classifying the obtained results. The results demonstrate, under specific conditions, that it is possible to add a hardware co-processor to a fault-tolerant microprocessor, improving performance without degrading safety and reliability. Full article
(This article belongs to the Special Issue High-Performance Embedded Systems)
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