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Electronics
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Advances in Analog and Mixed-Signal Integrated Circuits
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Advances in Analog and Mixed-Signal Integrated Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 30 April 2024 | Viewed by 5033

Special Issue Editor

Dr. Masum Hossain

E-Mail Website
Guest Editor
Department of Electrical & Computer Engineering, Faculty of Engineering, University of Alberta, Edmonton, AB T6G 2R3, Canada
Interests: high-speed I/O; memory interface; analog and mixed signal computation; frequency synthesis and data converters
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Analog and mixed-signal circuits are in high demand in the current system-on-chip (SoC) systems. They are widely used in power management, radio frequency (RF) signal sensing and processing, A/D or D/A conversion, clock generation, etc.

Therefore, the main objective of this Special Issue is to present new works, recent developments, reviews, and results in the field of novel concepts on phase locking, and carrier recovery, as well as building blocks such as VCO, wide bandwidth amplifiers, comparators, analog, mixed-signal and RF circuits, and systems. Relevant topics include, but are not limited to, the following:

  • Clocking circuits;
  • Power amplifiers;
  • Transceiver designs;
  • High-speed I/O circuits;
  • Data converters: ADCs and DACs;
  • Low-power and low-voltage circuits;
  • Power management circuits;
  • Digital-based analog processing;
  • CMOS and beyond circuit design;
  • Machine learning techniques/AI in analog/RF integrated circuit design;
  • Mixed signal circuits/systems;
  • Integrated sensor ICs;
  • RF circuits and building blocks.

Dr. Masum Hossain
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • SerDes
  • ADC/TDC equalization
  • PLL, DLL and CDR
  • analog and mixed-signal circuits
  • RF circuits

Published Papers (5 papers)

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Research

14 pages, 1380 KiB  
Article
Design of a 12-Bit SAR ADC with Calibration Technology
by Deming Wang, Jing Hu, Xin Huang and Qinghua Zhong
Electronics 2024, 13(3), 548; https://doi.org/10.3390/electronics13030548 - 30 Jan 2024
Viewed by 888
Abstract
Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In [...] Read more.
Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 μm × 517 μm. Full article
(This article belongs to the Special Issue Advances in Analog and Mixed-Signal Integrated Circuits)
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14 pages, 7969 KiB  
Article
Multi-Channel Sensing System Utilizing Mott Memristors for Single-Wire Data Fusion and Back-End Greedy Strategy Data Recovery
by Shiquan Fan, Peihao Liu, Yongqiang Shi, Shujing Zhao, Chuanyu Han, Junyi Xu and Guohe Zhang
Electronics 2024, 13(2), 345; https://doi.org/10.3390/electronics13020345 - 13 Jan 2024
Viewed by 643
Abstract
This paper presents a novel Mott memristor-based multi-channel sensing system designed for the simultaneous processing of multiple sensing channels, employing single-wire data fusion and a greedy search strategy for back-end data recovery. Multiple channels of external stimulus information are simultaneously encoded into analog [...] Read more.
This paper presents a novel Mott memristor-based multi-channel sensing system designed for the simultaneous processing of multiple sensing channels, employing single-wire data fusion and a greedy search strategy for back-end data recovery. Multiple channels of external stimulus information are simultaneously encoded into analog signals with varying frequencies, utilizing a Mott memristor array. Auxiliary circuits then convert the analog sensing signals into square wave signals which are further transformed into narrow (100 ns) pulse signals through pulse generation circuitry. Subsequently, these narrow pulse signals are fused into a single-wire signal by using an OR gate. At the back-end of the system, a greedy searching strategy is applied to accurately identify all frequencies within the fused pulse signal, enabling seamless analog-to-frequency conversion across multiple channels. The system is suitable for a wide range of sensors and can be directly connected to FPGAs for data processing, eliminating the need for traditional analogue front-end and ADC circuits and greatly reducing circuit complexity and power consumption. By leveraging the innovative capabilities of Mott memristors, the proposed system achieves precise analog-to-frequency conversion with significantly reduced power consumption. Full article
(This article belongs to the Special Issue Advances in Analog and Mixed-Signal Integrated Circuits)
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13 pages, 3901 KiB  
Communication
In-ADC, Rank-Order Filter for Digital Pixel Sensors
by Miron Kłosowski, Yichuang Sun, Waldemar Jendernalik, Grzegorz Blakiewicz, Jacek Jakusz and Stanisław Szczepański
Electronics 2024, 13(1), 46; https://doi.org/10.3390/electronics13010046 (registering DOI) - 21 Dec 2023
Viewed by 600
Abstract
This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states [...] Read more.
This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW. Full article
(This article belongs to the Special Issue Advances in Analog and Mixed-Signal Integrated Circuits)
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13 pages, 3515 KiB  
Article
A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing
by Cheng Wang, Zhanpeng Yang, Xinpeng Xing, Quanzhen Duan, Xinfa Zheng and Georges Gielen
Electronics 2023, 12(19), 4062; https://doi.org/10.3390/electronics12194062 - 27 Sep 2023
Viewed by 928
Abstract
This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC [...] Read more.
This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. Full article
(This article belongs to the Special Issue Advances in Analog and Mixed-Signal Integrated Circuits)
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12 pages, 2527 KiB  
Article
Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata
by Aibin Yan, Xuehua Li, Runqi Liu, Zhengfeng Huang, Patrick Girard and Xiaoqing Wen
Electronics 2023, 12(14), 3189; https://doi.org/10.3390/electronics12143189 - 23 Jul 2023
Viewed by 1435
Abstract
Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently [...] Read more.
Quantum-dot cellular automata (QCA) has been considered as a novel nano-electronic technology. With the advantages of low power consumption, high speed, and high integration, QCA has been treated as the potential replacement technology of the CMOS (complementary metal oxide semiconductor) which is currently used in the industry. This paper presents a QCA-based array multiplier with an optimized delay. This type of circuit is the basic building block of many arithmetic logic units and electronic communication systems. Compared to the existing array multipliers, the proposed multipliers have the smallest cell count and area. The proposed designs used a compact clock scheme to reduce the carry delay of the signals. The 2 × 2 array multiplier clock delay was reduced by almost 65% compared to the existing designs. Moreover, since the multiplier exhibits a good scalability, for further proof, we proposed a 3 × 3 array multiplier. Simulation results asserted the feasibility of the proposed multipliers. Extensive comparison results demonstrated that when the design scaling was increased, our proposed designs still displayed an efficient overhead in terms of the delay, cell count, and area. The QCADesigner tool was employed to validate the proposed array multipliers. The QCADesigner-E was used to measure the power dissipation of the alternative compared solutions. Full article
(This article belongs to the Special Issue Advances in Analog and Mixed-Signal Integrated Circuits)
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