Resistive Memory Characterization, Simulation, and Compact Modeling

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 10632

Special Issue Editors


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Guest Editor
Department of Electronics and Computer Technology, Science Faculty, Granada University, Avda. Fuente Nueva s/n 18071, Granada, Spain
Interests: resistive RAMs and memristors physical simulation and compact modeling; simulation and modeling of nanometric conventional and multigate devices; CMOS photodiodes and giant magnetoresistance current sensors

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Guest Editor
Department of Electronics and Computer Technology, Science Faculty, University of Granada, Av. Fuentenueva s/n, 18071 Granada, Spain
Interests: RRAMs; memristors; Semiconductor Device Physics; nanoelectronics; Semiconductor Device Modeling

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Guest Editor
Institut de Microelectrònica de Barcelona IMB-CNM (CSIC), C/del Til·lers. Campus Universitat Autònoma de Barcelona (UAB), 08193 Cerdanyola del Vallès (Bellaterra), Barcelona, Spain
Interests: RRAMs; metal oxide semiconductors; thin film deposition; semiconductor device physics; material characterization;microelectronics; memristors; reliability

Special Issue Information

Dear Colleagues,

Resistive memories (also known as resistive random-access memories, RRAM) are outstanding electron devices that are being scrutinized both by academia and industry for their great potential in different applications in the electronics realm. They are a subgroup of a large family of devices known as memristors. In general, they are made of a simple structure formed by two electrodes (metal or semiconductors) with a dielectric in between (different materials have been employed for this, such as transition metal oxides, 2D material-based dielectric such as h-BN, multilayer stacks, etc.). Their conductance can be easily changed in a non-volatile manner, and their operation is known as resistive switching. The simplicity and stackability of these structures, their good endurance, reliability, and compatibility with the standard electronic technology make these devices attractive and promising in the semiconductor industry landscape. They have been used for the implementation of storage-class memories, but in this application facet, there is still a long way to go. Another application that shows a great future is linked to neuromorphic circuits. In this case, these resistive switching devices can be used to mimic biological synapses. Neuromorphic computing can step forward with circuits based on resistive switching devices due to their low power operation and their versatility to play the role of artificial synapses. In this manner, von Neumann bottlenecks could be overcome in computing solutions related to artificial intelligence. Finally, applications devoted to cryptography and the implementation of physical unclonable functions are of great interest due to the intrinsic stochastic nature of RRAM operation.

Resistive memories are key devices in this Special Issue where the most representative features of this technology will be tackled from different perspectives. Therefore, the scope will range from materials and device processing technologies to circuit and applications. We will pay special attention to simulations, including all the different approaches that can be employed to describe device physics and internal variables. In addition, compact modeling will be addressed, along with advanced electrical characterization methodologies and reliability studies. A detailed description of the topics is given below:

Topic list

  • Fabrication of resistive switching materials, devices, and advanced material characterization
  • Electrical characterization techniques and reliability for resistive memories
  • Multilevel operation algorithms
  • Resistive memories physical simulation (kinetic Monte Carlo, Ab initio approach, macroscopic description, etc.)
  • Resistive memory compact modeling (kinetic, thermal, noise modeling; Verilog-A implementation, modules for SPICE based circuit simulation, etc.)
  • Memristor modeling approach (current versus voltage, charge versus flux, first and second order memristors, etc.)
  • Emerging device applications: neuromorphic devices and circuits, hardware security, digital logic circuits, etc.

Prof. Dr. Juan B. Roldán Aranda
Prof. Dr. Francisco Jiménez-Molinos
Dr. Mireia Bargalló Gonzalez
Guest Editors

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Published Papers (4 papers)

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Research

12 pages, 388 KiB  
Article
Empirical Characterization of ReRAM Devices Using Memory Maps and a Dynamic Route Map
by Rodrigo Picos, Stavros G. Stavrinides, Mohamad Moner Al Chawa, Carola de Benito, Salvador Dueñas, Helena Castan, Euripides Hatzikraniotis and Leon O. Chua
Electronics 2022, 11(11), 1672; https://doi.org/10.3390/electronics11111672 - 24 May 2022
Cited by 1 | Viewed by 1824
Abstract
Memristors were proposed in the early 1970s by Leon Chua as a new electrical element linking charge to flux. Since that first introduction, these devices have positioned themselves to be considered as possible fundamental ones for the generations of electronic devices to come. [...] Read more.
Memristors were proposed in the early 1970s by Leon Chua as a new electrical element linking charge to flux. Since that first introduction, these devices have positioned themselves to be considered as possible fundamental ones for the generations of electronic devices to come. In this paper, we propose a new way to investigate the effects of the electrical variables on the memristance of a device, and we successfully apply this technique to model the behavior of a TiN/Ti/HfO2/W ReRAM structure. To do so, we initially apply the Dynamic Route Map technique in the general case to obtain an approximation to the differential equation that determines the behaviour of the device. This is performed by choosing a variable of interest and observing the evolution of its own temporal derivative versus both its value and the applied voltage. Then, according to this technique, it is possible to obtain an approach to the governing equations with no need to make any assumption about the underlying physical mechanisms, by fitting a function to this. We have used a polynomial function, which allows accurate reproduction of the observed electrical behavior of the measured devices, by integrating the resulting differential equation system. Full article
(This article belongs to the Special Issue Resistive Memory Characterization, Simulation, and Compact Modeling)
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9 pages, 2593 KiB  
Article
Effect of Dielectric Thickness on Resistive Switching Polarity in TiN/Ti/HfO2/Pt Stacks
by Guillermo Vinuesa, Héctor García, Mireia B. González, Kristjan Kalam, Miguel Zabala, Aivar Tarre, Kaupo Kukli, Aile Tamm, Francesca Campabadal, Juan Jiménez, Helena Castán and Salvador Dueñas
Electronics 2022, 11(3), 479; https://doi.org/10.3390/electronics11030479 - 06 Feb 2022
Cited by 6 | Viewed by 2049
Abstract
In recent years, several materials and metal-insulator-metal devices are being intensively studied as prospective non-volatile memories due to their resistive switching effect. In this work, thickness-dependent resistive switching polarity was observed in TiN/Ti/HfO2/Pt structures as the sign of the voltages at [...] Read more.
In recent years, several materials and metal-insulator-metal devices are being intensively studied as prospective non-volatile memories due to their resistive switching effect. In this work, thickness-dependent resistive switching polarity was observed in TiN/Ti/HfO2/Pt structures as the sign of the voltages at which SET and RESET occur depended on the film thickness. A thorough revision of the previous literature on bipolar resistive switching polarity changes is made in order to condense previous knowledge of the subject in a brief and comprehensible way and explain the experimental measurements. The different resistive switching polarities occur in a similar voltage range, which is a new finding when compared to precedent research on the subject. A hypothesis is proposed to explain the change in resistive switching polarity, based on the assumption that polarity change is due to filament disruption occurring at different interfaces. Full article
(This article belongs to the Special Issue Resistive Memory Characterization, Simulation, and Compact Modeling)
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18 pages, 8142 KiB  
Article
Serial RRAM Cell for Secure Bit Concealing
by Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Mireia Bargalló González, Francesca Campabadal and Liang Fang
Electronics 2021, 10(15), 1842; https://doi.org/10.3390/electronics10151842 - 31 Jul 2021
Cited by 3 | Viewed by 2089
Abstract
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could [...] Read more.
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal. Full article
(This article belongs to the Special Issue Resistive Memory Characterization, Simulation, and Compact Modeling)
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15 pages, 4552 KiB  
Article
Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
by Eduardo Pérez, Antonio Javier Pérez-Ávila, Rocío Romero-Zaliz, Mamathamba Kalishettyhalli Mahadevaiah, Emilio Pérez-Bosch Quesada, Juan Bautista Roldán, Francisco Jiménez-Molinos and Christian Wenger
Electronics 2021, 10(9), 1084; https://doi.org/10.3390/electronics10091084 - 03 May 2021
Cited by 13 | Viewed by 3388
Abstract
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by [...] Read more.
Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters. Full article
(This article belongs to the Special Issue Resistive Memory Characterization, Simulation, and Compact Modeling)
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