Mixed Signal Integrated Circuit Design

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 September 2024 | Viewed by 1768

Special Issue Editors


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Guest Editor
Department of Electrical and Computer Engineering, University of the Peloponnese, 263 34 Patras, Greece
Interests: analog integrated circuits; analog filters; high speed serial transceivers; RF circuits for wireless transceivers; low voltage and low power electronics

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Guest Editor
IoT Connectivity & Audio Business Unit, Renesas Electronics, 176 74 Athens, Greece
Interests: analog integrated circuits; continuous-time filters; low-voltage/low-power circuits; RF circuits for wireless transceivers

Special Issue Information

Dear Colleagues,

As high-frequency operation, together with quality, and accuracy are of great importance in many integrated circuits, the need for combining analog and digital circuits on the same die became a necessity for integrated circuits. So, mixed signal circuits on the same die have gained much development during recent decades. Taking advantage of the high operating frequency of analog circuits with the high accuracy, high complexity, and low power consumption of digital circuits, mixed signal integrated circuits are exploited.  The analog-to-digital converter (ADC) is a typical application based on the combination of analog and digital circuits, though more topologies of mixed-signal circuits are used in communications, RF circuits with digital control, automotive, IoT circuits, sensor circuits, and others. Additionally, with the increasing demand for IoT devices, the development of more advanced mixed-signal circuits will continue to be an important area of research and further expand the scale of sensing, communication, and computation. The tight area and power budget in these applications will lead to a more careful and sophisticated design of mixed-signal circuits. One of the challenges in deep-scaled nodes is that as logic gates are getting better, supply headroom and transistor intrinsic gain is reduced which severely impacts analog circuit performance.  

This Special Issue provides an opportunity for researchers and engineers to present original high-quality articles in subjects covering all aspects of mixed signal integrated circuits. The topics of interest include, but are not limited to, the following:

  • Mixed signal circuits;
  • All digital PLLs;
  • Analog-to-Digital Converters (ADC);
  • Digital-to-Analog Converters (DAC);
  • All digital transceivers;
  • Automotive mixed-mode circuits;
  • Internet of Thing (IoT) circuits;
  • High-Speed I/O circuits;
  • Sensor circuits on ICs;
  • Power management.

Dr. George Souliotis
Dr. Costas Laoudias
Guest Editors

Manuscript Submission Information

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Keywords

  • mixed signal circuits
  • all digital PLLs
  • analog-to-digital converters (ADC)
  • digital-to-analog converters (DAC)
  • all digital transceivers
  • automotive mixed-mode circuits
  • Internet of Thing (IoT) circuits
  • high-speed I/O circuits
  • sensor circuits on ICs
  • power management

Published Papers (2 papers)

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Research

14 pages, 10131 KiB  
Article
A High ENOB 14-Bit ADC without Calibration
by Costas Laoudias, George Souliotis and Fotis Plessas
Electronics 2024, 13(3), 570; https://doi.org/10.3390/electronics13030570 - 31 Jan 2024
Viewed by 722
Abstract
This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, [...] Read more.
This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process. Full article
(This article belongs to the Special Issue Mixed Signal Integrated Circuit Design)
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19 pages, 12261 KiB  
Article
A 48-Channel High-Resolution Ultrasound Beamforming System for Ultrasound Endoscopy Applications
by Soohyun Yun, Seungah Lee and Joonsung Bae
Electronics 2024, 13(3), 568; https://doi.org/10.3390/electronics13030568 - 30 Jan 2024
Viewed by 646
Abstract
We introduce a highly efficient 48-channel ultrasound beamforming system ideal for ultrasound endoscopy applications. The system includes a transmitter and a receiver that allows for low-area, high-resolution imaging acquisition. The transmitter uses a charge redistribution HV (high-voltage) scheme to generate three-level pulses that [...] Read more.
We introduce a highly efficient 48-channel ultrasound beamforming system ideal for ultrasound endoscopy applications. The system includes a transmitter and a receiver that allows for low-area, high-resolution imaging acquisition. The transmitter uses a charge redistribution HV (high-voltage) scheme to generate three-level pulses that actuate the transducer, implemented with the standard CMOS process for optimal cost and power savings. Meanwhile, the receiver features a sub-array structure and a delay generator that reduces the area usage. To achieve high-resolution ultrasound imaging acquisition with low computational power, we developed a Shift Coherence Factor (SCF) algorithm that is hardware-friendly. This approach delivers a lateral resolution of over 20% better than that of the conventional delay and sum (DAS) algorithm, with a contrast ratio of over 30 dB. The system was implemented in a 180 nm standard CMOS process with an area of 24.98 mm2, power consumption of 8.23 mW per channel, achieving a delay resolution of 8.33 ns, and a low-area implementation of 0.52 mm2 per channel. The system offers high-quality imaging acquisition with minimal additional area and power consumption, which has great potential for 3D imaging or catheterized ultrasound systems. Full article
(This article belongs to the Special Issue Mixed Signal Integrated Circuit Design)
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