Submit to Electronics Review for Electronics Propose a Special Issue

Journal Menu

Journal Browser

Efficient Algorithms and Architectures for DSP Applications

Print Special Issue Flyer
Special Issue Editors
Special Issue Information
Keywords
Published Papers

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2022) | Viewed by 20584

Share This Special Issue

Special Issue Editors

Prof. Dr. Doru Florin Chiper

E-Mail Website
Guest Editor

Technical Sciences Academy of Romania—ASTR, Academy of Romanian Scientists—AOSR, Faculty of Electronics, Telecommunication and Information Technology, “Gheorghe Asachi“ Technical University of Iasi, 700506 Iasi, Romania
Interests: digital signal processing (DSP); adaptive signal processing; blind equalization/identification; fast computational algorithms; parallel and VLSI algorithms and architectures for communications and DSP; high-level DSP design
Special Issues, Collections and Topics in MDPI journals

Prof. Dr. Constantin Paleologu

E-Mail Website
Guest Editor

Department of Telecommunications, University Politehnica of Bucharest, 1-3, Iuliu Maniu Blvd., 061071 Bucharest, Romania
Interests: adaptive filters; acoustic echo cancellation; sparse systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Optimization of the implementation of DSP algorithms and architectures is an essential part of research and design for many modern applications, e.g., multimedia, big data, IoT, etc. For example, real-time multimedia applications have increasingly more performance requirements due to data processing and transmission of huge data volumes at high speeds, with resource constraints specific to portable devices. Optimizing such computationally intensive applications is a challenging issue that requires a clever design or restructuring of the algorithm or architecture. This Special Issue focuses on papers that demonstrate how these design challenges can be overcome using innovative solutions.

Topics of interest for this Special Issue include but are not limited to:

VLSI signal processing;
Signal processing methods for an efficient implementation;
Optimization of the VLSI implementation of multimedia blocks;
Low-power circuits and systems for DSP applications;
Efficient adaptive/learning algorithms (low complexity/fast versions, optimized parameters, etc.);
Tensor-based signal processing (efficient decomposition methods, low-rank approximations, etc.);
Sparsity-aware algorithms.

Prof. Dr. Chiper Doru Florin
Prof. Dr. Constantin Paleologu
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

VLSI signal processing
Signal processing methods for an efficient implementation
Optimization of the VLSI implementation of multimedia blocks
Low-power circuits and systems for DSP applications
Efficient adaptive/learning algorithms (low complexity/fast versions, optimized parameters, etc.)
Tensor-based signal processing (efficient decomposition methods, low-rank approximations, etc.)
Sparsity-aware algorithms

Published Papers (12 papers)

Download All Papers

Order results

Result details

Show export options Show export options

Select all

Export citation of selected articles as:

Editorial

Jump to: Research, Review

4 pages, 174 KiB

Open AccessEditorial

Efficient Algorithms and Architectures for DSP Applications

by Doru-Florin Chiper and Constantin Paleologu

Electronics 2023, 12(4), 1012; https://doi.org/10.3390/electronics12041012 - 17 Feb 2023

Viewed by 1069

Abstract

In the new era of digital revolution, the digital sensors and embedded designs become cheaper and more present [...] Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

Research

Jump to: Editorial, Review

19 pages, 4583 KiB

Open AccessArticle

Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems

by Olga Bureneva and Sergey Mironov

Electronics 2023, 12(3), 605; https://doi.org/10.3390/electronics12030605 - 26 Jan 2023

Cited by 2 | Viewed by 2201

Abstract

Traditionally, the usual multipliers are used to multiply signals by a constant, but multiplication by a constant can be considered as a special operation requiring the development of specialized multipliers. Different methods are being developed to accelerate multiplications. A large list of methods implement multiplication on a group of bits. The most known one is Booth’s algorithm, which implements two-digit multiplication. We propose a modification of the algorithm for the multiplication by three digits at the same time. This solution reduces the number of partial products and accelerates the operation of the multiplier. The paper presents the results of a comparative analysis of the characteristics of Booth’s algorithm and the proposed algorithm. Additionally, a comparison with built-in FPGA multipliers is illustrated. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

30 pages, 4961 KiB

Open AccessArticle

ASIPAMPIUM: An Efficient ASIP Generator for Low Power Applications

by Alian Engroff, Marcelo Romanssini, Lucas Compassi-Severo, Paulo C. C. de Aguirre and Alessandro Girardi

Electronics 2023, 12(2), 401; https://doi.org/10.3390/electronics12020401 - 12 Jan 2023

Cited by 3 | Viewed by 1319

Abstract

The adoption of customized ASIPs (Application Specific Instruction Set Processors) in embedded circuits is an important alternative for optimizing power consumption, silicon area, or processing performance according to the design requirements. The processor is implemented specifically for the target application, which allows the hardware customization in terms of instruction set architecture, data word length, memory size, and parallelism. This work describes an EDA tool for the semi-automatic development of ASIPs named ASIPAMPIUM. The strategy is to provide a set of integrated tools to interpret and generate a customized hardware for a given target application, including compilation, simulation, and hardware synthesis. From the C code description of the application, the tool returns a synthesizable hardware description of the processor. The proposed methodology is based on the adaptation of a new customizable microprocessor called PAMPIUM, which can be optimized in terms of silicon area, power consumption, or processing performance according to the target application. The ASIPAMPIUM tool provides a series of simulated data to the designer in order to identify optimization strategies in both software and hardware domains. We show the results for the implementation of an FFT algorithm using the proposed methodology, which achieved best results in terms of silicon area and energy consumption compared to other works described in the literature for both FPGA and silicon implementation. Moreover, measurement results of the implementation in silicon of a dedicated ASIP for interfacing with six sensors in real-time, including three I2C, an SPI, and an RS-232 interfaces, demonstrate the complete design flow, from the C code program to physical implementation and characterization. Aside from providing a short design time, the ASIPAMPIUM tool also affords a simple and intuitive design flow, allowing the designer to deal with different design trade-offs and objectives. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

17 pages, 2269 KiB

Open AccessArticle

An Improved VLSI Algorithm for an Efficient VLSI Implementation of a Type IV DCT That Allows an Efficient Incorporation of Hardware Security with a Low Overhead

by Doru Florin Chiper

Electronics 2023, 12(1), 243; https://doi.org/10.3390/electronics12010243 - 03 Jan 2023

Cited by 2 | Viewed by 1134

Abstract

This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexity and the overheads introduced by the security techniques should be as low as possible. This paper proposes an improved approach based on a new VLSI algorithm for including the obfuscation technique in the VLSI implementation of one important DSP algorithm used in multimedia applications. The proposed approach is based on a new VLSI algorithm that decomposes type IV DCT into six quasi-cycle convolutions and allows an efficient incorporation of the obfuscation technique. The proposed method uses a regular and modular structure called quasi-cyclic convolution and the obtained architecture is based on the architectural paradigm of systolic arrays. In this way we can obtain the advantages introduced by systolic arrays, especially high speed, with an efficient utilization of the hardware structure. Moreover, using the proposed VLSI algorithm, we can obtain the important benefit of attaining hardware security. Thus, a more efficient VLSI architecture for type IV DCT can be obtained, with a significant reduction of the hardware complexity, and an efficient incorporation of an improved hardware security mechanism with low overheads. These features are very important for resource-constrained common goods. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

14 pages, 2839 KiB

Open AccessArticle

Dual Reversible Data Hiding Based on AMBTC Using Hamming Code and LSB Replacement

by Cheonshik Kim

Electronics 2022, 11(19), 3210; https://doi.org/10.3390/electronics11193210 - 06 Oct 2022

Cited by 4 | Viewed by 1174

Abstract

The existing data hiding schemes conceal the data in the cover image and then communicate secretly on the channel. The weakness of these methods is that the security aspect is somewhat lacking, and there is a limit to hiding enough data. In this paper, we propose a reversible data hiding method based on dual AMBTC images. It improves security, which is a weakness of data hiding. AMBTC has strengths in low-bandwidth channel environments with simple calculations and efficient data performance. HC(7,4) and LSB replacement methods are applied to each block of AMBTC to hide secret data. After the embedding process, the two AMBTC-marked images are obtained, and these images are sent to different recipients. The recipients can extract hidden messages and restore the cover AMBTC image by using the proposed method and two marked images. Our proposed data hiding method guarantees sufficient data hiding, proper cover image quality, and restoration of the original cover image. Experimental results show that our method is efficient in terms of image quality and embedding ratio. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

18 pages, 373 KiB

Open AccessArticle

Small-Size Algorithms for the Type-I Discrete Cosine Transform with Reduced Complexity

by Miłosz Kolenderski and Aleksandr Cariow

Electronics 2022, 11(15), 2411; https://doi.org/10.3390/electronics11152411 - 02 Aug 2022

Cited by 1 | Viewed by 1338

Abstract

Discrete cosine transforms (DCTs) are widely used in intelligent electronic systems for data storage, processing, and transmission. The popularity of using these transformations, on the one hand, is explained by their unique properties and, on the other hand, by the availability of fast algorithms that minimize the computational and hardware complexity of their implementation. The type-I DCT has so far been perhaps the least popular, and there have been practically no publications on fast algorithms for its implementation. However, at present the situation has changed; therefore, the development of effective methods for implementing this type of DCT becomes an urgent task. This article proposes several algorithmic solutions for implementing type-I DCTs. A set of type-I DCT algorithms for small lengths

N = 2, 3, 4, 5, 6, 7, 8

is presented. The effectiveness of the proposed solutions is due to the possibility of fortunate factorization of the small-size DCT-I matrices, which reduces the complexity of implementing transformations of this type. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

22 pages, 726 KiB

Open AccessArticle

On the Derivation of Winograd-Type DFT Algorithms for Input Sequences Whose Length Is a Power of Two

by Mateusz Raciborski and Aleksandr Cariow

Electronics 2022, 11(9), 1342; https://doi.org/10.3390/electronics11091342 - 23 Apr 2022

Cited by 1 | Viewed by 1902

Abstract

Winograd’s algorithms are an effective tool for calculating the discrete Fourier transform (DFT). These algorithms described in well-known articles are traditionally represented either with the help of sets of recurrent relations or with the help of products of sparse matrices obtained on the basis of various methods of the DFT matrix factorization. Unfortunately, in the mentioned papers, it is not shown how the described relations were obtained or how the presented factorizations were found. In this paper, we use a simple, understandable and fairly unified approach to the derivation of the Winograd-type DFT algorithms for the cases N = 8, N = 16 and N = 32. It is easy to verify that algorithms for other lengths of sequences that are powers of two can be synthesized in a similar way. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

15 pages, 1159 KiB

Open AccessArticle

Cascaded RLS Adaptive Filters Based on a Kronecker Product Decomposition

by Alexandru-George Rusu, Silviu Ciochină, Constantin Paleologu and Jacob Benesty

Electronics 2022, 11(3), 409; https://doi.org/10.3390/electronics11030409 - 29 Jan 2022

Cited by 3 | Viewed by 1894

Abstract

The multilinear system framework allows for the exploitation of the system identification problem from different perspectives in the context of various applications, such as nonlinear acoustic echo cancellation, multi-party audio conferencing, and video conferencing, in which the system could be modeled through parallel or cascaded filters. In this paper, we introduce different memoryless and memory structures that are described from a bilinear perspective. Following the memory structures, we develop the multilinear recursive least-squares algorithm by considering the Kronecker product decomposition concept. We have performed a set of simulations in the context of echo cancellation, aiming both long length impulse responses and the reverberation effect. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

16 pages, 841 KiB

Open AccessArticle

Tensor-Based Recursive Least-Squares Adaptive Algorithms with Low-Complexity and High Robustness Features

by Ionuț-Dorinel Fîciu, Cristian-Lucian Stanciu, Camelia Elisei-Iliescu and Cristian Anghel

Electronics 2022, 11(2), 237; https://doi.org/10.3390/electronics11020237 - 12 Jan 2022

Cited by 3 | Viewed by 1278

Abstract

The recently proposed tensor-based recursive least-squares dichotomous coordinate descent algorithm, namely RLS-DCD-T, was designed for the identification of multilinear forms. In this context, a high-dimensional system identification problem can be efficiently addressed (gaining in terms of both performance and complexity), based on tensor decomposition and modeling. In this paper, following the framework of the RLS-DCD-T, we propose a regularized version of this algorithm, where the regularization terms are incorporated within the cost functions. Furthermore, the optimal regularization parameters are derived, aiming to attenuate the effects of the system noise. Simulation results support the performance features of the proposed algorithm, especially in terms of its robustness in noisy environments. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

23 pages, 4845 KiB

Open AccessArticle

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

by Doru Florin Chiper and Laura-Teodora Cotorobai

Electronics 2021, 10(14), 1656; https://doi.org/10.3390/electronics10141656 - 12 Jul 2021

Cited by 8 | Viewed by 1572

Abstract

This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

Review

Jump to: Editorial, Research

22 pages, 1192 KiB

Open AccessReview

An Overview of Systolic Arrays for Forward and Inverse Discrete Sine Transforms and Their Exploitation in View of an Improved Approach

by Doru Florin Chiper, Arcadie Cracan and Vasilica-Daniela Andries

Electronics 2022, 11(15), 2416; https://doi.org/10.3390/electronics11152416 - 02 Aug 2022

Cited by 2 | Viewed by 1302

Abstract

This paper aims to present a unified overview of the main Very Large-Scale Integration (VLSI) implementation solutions of forward and inverse discrete sine transforms using systolic arrays. The main features of the most important solutions to implement the forward and inverse discrete sine transform (DST) using systolic arrays are presented. One of the central ideas presented in the paper is to emphasize the advantages of using regular and modular systolic array computational structures such as cyclic convolution, circular correlation, and pseudo-band correlation in the VLSI implementation of these transforms. The use of such computational structures leads to architectures well adapted to the features of VLSI technologies, with an efficient use of the hardware structures and a reduced I/O cost that helps avoiding the so-called I/O bottleneck. With the techniques presented in this review, we have developed a new VLSI implementation of the DST using systolic arrays that allow efficient hardware implementation with reduced complexity while maintaining high-speed performances. Using a new restructuring input sequence, we have been able to efficiently reformulate the computation of the forward DST transform into a special computational structure using eight short quasi-cycle convolutions that can be computed with low complexity and where some of the coefficients are identical. This leads to a hardware structure with high throughput. The new restructuring sequence is the use of the input samples in a natural order as opposed to previous solutions, leading to a significant reduction of the hardware complexity in the pre-processing stage due to avoiding a permutation stage to reverse the order. Moreover, the proposed VLSI architecture allows an efficient incorporation of the obfuscation technique with very low overheads. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Figure 1

33 pages, 614 KiB

Open AccessReview

Identification of Linear and Bilinear Systems: A Unified Study

by Jacob Benesty, Constantin Paleologu, Laura-Maria Dogariu and Silviu Ciochină

Electronics 2021, 10(15), 1790; https://doi.org/10.3390/electronics10151790 - 26 Jul 2021

Cited by 19 | Viewed by 2531

Abstract

System identification problems are always challenging to address in applications that involve long impulse responses, especially in the framework of multichannel systems. In this context, the main goal of this review paper is to promote some recent developments that exploit decomposition-based approaches to multiple-input/single-output (MISO) system identification problems, which can be efficiently solved as combinations of low-dimension solutions. The basic idea is to reformulate such a high-dimension problem in the framework of bilinear forms, and to then take advantage of the Kronecker product decomposition and low-rank approximation of the spatiotemporal impulse response of the system. The validity of this approach is addressed in terms of the celebrated Wiener filter, by developing an iterative version with improved performance features (related to the accuracy and robustness of the solution). Simulation results support the main theoretical findings and indicate the appealing performance of these developments. Full article

(This article belongs to the Special Issue Efficient Algorithms and Architectures for DSP Applications)

► Show Figures

Journal Menu

Journal Browser

Efficient Algorithms and Architectures for DSP Applications

Share This Special Issue

Special Issue Editors

Special Issue Information

Keywords

Published Papers (12 papers)

Editorial

Research

Review

Further Information

Guidelines

MDPI Initiatives

Follow MDPI