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18 pages, 6734 KiB

Open AccessArticle

High-Speed CNN Accelerator SoC Design Based on a Flexible Diagonal Cyclic Array

by Dong-Yeong Lee, Hayotjon Aliev, Muhammad Junaid, Sang-Bo Park, Hyung-Won Kim, Keon-Myung Lee and Sang-Hoon Sim

Electronics 2024, 13(8), 1564; https://doi.org/10.3390/electronics13081564 - 19 Apr 2024

Viewed by 249

Abstract

The latest convolutional neural network (CNN) models for object detection include complex layered connections to process inference data. Each layer utilizes different types of kernel modes, so the hardware needs to support all kernel modes at an optimized speed. In this paper, we [...] Read more.

The latest convolutional neural network (CNN) models for object detection include complex layered connections to process inference data. Each layer utilizes different types of kernel modes, so the hardware needs to support all kernel modes at an optimized speed. In this paper, we propose a high-speed and optimized CNN accelerator with flexible diagonal cyclic arrays (FDCA) that supports the acceleration of CNN networks with various kernel sizes and significantly reduces the time required for inference processing. The accelerator uses four FDCAs to simultaneously calculate 16 input channels and 8 output channels. Each FDCA features a 4 × 8 systolic array that contains a 3 × 3 processing element (PE) array and is designed to handle the most commonly used kernel sizes. To evaluate the proposed CNN accelerator, we mapped the widely used YOLOv5 CNN model and evaluated the performance of its implementation on the Zynq UltraScale+ MPSoC ZCU102 FPGA. The design consumes 249,357 logic cells, 2304 DSP blocks, and only 567 KB BRAM. In our evaluation, the YOLOv5n model achieves an accuracy of 43.1% (mAP@0.5). A prototype accelerator has been implemented using Samsung’s 14 nm CMOS technology. It achieves 1.075 TOPS, a peak performance with a 400 MHz clock frequency. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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18 pages, 9098 KiB

Open AccessArticle

A Full-Duplex 60 GHz Transceiver with Digital Self-Interference Cancellation

by Yisheng Wang, Bharatha Kumar Thangarasu, Nagarajan Mahalingam, Kaixue Ma, Fanyi Meng, Yibo Huang and Kiat Seng Yeo

Electronics 2024, 13(3), 483; https://doi.org/10.3390/electronics13030483 - 24 Jan 2024

Viewed by 648

Abstract

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response [...] Read more.

This paper presents the design and measurement of an IEEE 802.11ad standard compatible RF transceiver for 60 GHz wireless communication systems. In addition to the traditional half-duplex (HD) mode, this work supports full-duplex (FD) operations to deliver better channel utilization and faster response times for the system. The isolation between the transmitter and receiver from the architecture design to system integration for FD operations has been fully considered. A digital self-interference cancellation (DSIC) is implemented in MATLAB to verify the FD performance. The super-heterodyne architecture with an intermediate frequency (IF) of 12 GHz is designed to suppress the image frequencies without using extra filters. A flexible phase-locked loop (PLL) synthesizer provides a local oscillator (LO) frequency with a 2 kHz resolution. Other than the time division duplex (TDD) mode used in the conventional 60 GHz system, a wide-bandwidth baseband digital variable-gain amplifier (DVGA) with a 3 dB bandwidth of more than 4 GHz also supports frequency division duplex (FDD) operations. The transceiver chip is fabricated using the Tower Jazz 0.18 µm SiGe BiCMOS process. With an on-board antenna, the transceiver covers all four channels in the 802.11ad standard, with MCS-12 (7.04 Gbps under 1.76 GSym/s and 16-QAM) under 1.5 m. In the proposed system design, the RF frontend-based self-interference (SI) suppression from the local transmitter to receiver LNA is around 54 dB. To achieve a practical FD application, the SI is further suppressed with the help of a digital SI compensation. The measured power consumption for the transmitter and receiver configurations are 194 mW and 231 mW, respectively, in HD mode and 398 mW for the FDD or FD operation mode. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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28 pages, 403 KiB

Open AccessArticle

New Programmable LFSR Counters with Automatic Encoding and State Extension

by Martin Grymel

Electronics 2024, 13(2), 405; https://doi.org/10.3390/electronics13020405 - 18 Jan 2024

Viewed by 696

Abstract

An efficient method for detecting the end of a count of a linear feedback shift register (LFSR) is presented. We show how this detector can be used to extend a maximum-length LFSR sequence by a number of states up to one less than [...] Read more.

An efficient method for detecting the end of a count of a linear feedback shift register (LFSR) is presented. We show how this detector can be used to extend a maximum-length LFSR sequence by a number of states up to one less than the degree of the polynomial. In addition, a new algorithm is proposed to encode binary sequence values into their corresponding LFSR sequence states. Based on this algorithm and an alternative second method, two novel programmable, full-range, high-speed LFSR counter designs are proposed. The time complexity of the conversion algorithms ranges from quadratic to exponential time in the degree of the underlying polynomial. The proposed counter solutions are fully synchronous and can be implemented with standard cells, enabling easy portability across technologies. As the levels of logic are independent of the counter size, high scalability is facilitated. For evaluation, all the designs, including the recreated state-of-the-art solution, have been implemented on an FPGA, and also simulated targeting TSMC’s N3 CMOS process node for a wide range of counter sizes. The results confirm the superiority of the proposed solutions over the state of the art in terms of frequency, area and power efficiency as the counter is scaled up. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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18 pages, 10344 KiB

Open AccessArticle

A 4-Channel Optogenetic Stimulation, 16-Channel Recording Neuromodulation System with Real-Time Micro-LED Detection Function

by Yu Xia, Ruihan Zheng, Liyang Wang, Anguo Zhang, Dongming Li, Yufei Wu, Yueming Gao, Yanyan Xu, Baijun Zhang, Hungchun Li, Peng Un Mak, Mang I. Vai and Sio Hang Pun

Electronics 2023, 12(23), 4783; https://doi.org/10.3390/electronics12234783 - 26 Nov 2023

Viewed by 743

Abstract

Neuromodulation techniques are essential for exploring brain science and supporting treatments for neurological disorders. Compared to electrical neuromodulation, optogenetic neuromodulation offers advantages in cell type specificity and spatial precision. However, existing optogenetic neuromodulation systems have limited functionality (unable to simultaneously possess functions including [...] Read more.

Neuromodulation techniques are essential for exploring brain science and supporting treatments for neurological disorders. Compared to electrical neuromodulation, optogenetic neuromodulation offers advantages in cell type specificity and spatial precision. However, existing optogenetic neuromodulation systems have limited functionality (unable to simultaneously possess functions including optogenetic stimulation, recording, and micro-LED (micro-Light-Emitting Diode) status monitoring) and will restrict normal biological activities due to their large size. To this end, this paper presents an optogenetic neuromodulation system, including a specified neuromodulation IC (Integrated Circuit) and a customized optrode. The ASIC (Application Specific Integrated Circuit) includes a 16-channel neural signal recording module, a 4-channel optogenetic neurostimulator module, and a 4-channel micro-LED detection module. The micro-LED detection module monitors the micro-LED’s long-term status in real time and provides the direct output of its working status for convenient user access. The neuromodulation ASIC was fabricated in the TSMC 65 nm process, and an in situ normal saline experiment was conducted to test the neuromodulation system’s function. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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18 pages, 2591 KiB

Open AccessArticle

Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices

by Posani Vijaya Lakshmi, Sarada Musala, Avireni Srinivasulu and Cristian Ravariu

Electronics 2023, 12(22), 4691; https://doi.org/10.3390/electronics12224691 - 18 Nov 2023

Cited by 2 | Viewed by 1079

Abstract

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and [...] Read more.

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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29 pages, 20029 KiB

Open AccessArticle

Offset Voltage Reduction in Two-Stage Folded-Cascode Operational Amplifier Using High-Precision Source Degeneration

by Cristian Stancu, Andrei Neacsu, Teodora Ionescu, Cornel Stanescu, Ovidiu Profirescu, Dragos Dobrescu and Lidia Dobrescu

Electronics 2023, 12(21), 4534; https://doi.org/10.3390/electronics12214534 - 03 Nov 2023

Viewed by 1966

Abstract

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and [...] Read more.

The demand for CMOS precision operational amplifiers for critical applications has continuously increased over time due to higher accuracy and sensitivity requirements. Trimming or chopper architectures are advanced solutions that reduce the offset voltage and improve the circuit’s parameters, but the complexity and the increased chip die size are serious downsides. An efficient solution is a source degeneration configuration to control the transistor’s current-mirror transconductance, which impacts the offset voltage, with cost savings and a die area reduction also obtained. This paper focuses on designing and implementing such an approach in a two-stage folded-cascode operational amplifier. State-of-the-art thin-film resistors that use silicon–chromium as the metallic alloy were implemented to reduce mismatch variations between these passive components. Distinct methods that control the offset voltage parameter are also discussed and established. A comparison between the offset voltage standard deviation obtained using different types of resistors and that achieved with the innovative high-precision resistors was also carried out. The source degeneration’s impact on the common-mode rejection ratio, power supply rejection ratio, bandwidth and phase margin was also analyzed, and a comparison between the proposed design and the classical one was performed. The process variation’s influence on the circuit functionality was studied. A pre-layout ±1.273 mV maximum offset voltage at T = 27 °C was achieved using vector/array notations for the amplifier with the best overall performance. Post-layout simulations that included parasitic effects were performed, with a ±1.254 mV maximum offset voltage reached at room temperature. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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12 pages, 4505 KiB

Open AccessArticle

Low-Power Single Bitline Load Sense Amplifier for DRAM

by Chenghu Dai, Yixiao Lu, Wenjuan Lu, Zhiting Lin, Xiulong Wu and Chunyu Peng

Electronics 2023, 12(19), 4024; https://doi.org/10.3390/electronics12194024 - 25 Sep 2023

Viewed by 1427

Abstract

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since [...] Read more.

With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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19 pages, 5470 KiB

Open AccessArticle

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

by Ningyuan Yin, Wanyuan Pan, Yihe Yu, Chengcheng Tang and Zhiyi Yu

Electronics 2023, 12(15), 3209; https://doi.org/10.3390/electronics12153209 - 25 Jul 2023

Cited by 1 | Viewed by 2570

Abstract

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and [...] Read more.

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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15 pages, 1409 KiB

Open AccessArticle

A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation

by Hyein Kang, Sewon Lee and Minjae Lee

Electronics 2023, 12(8), 1863; https://doi.org/10.3390/electronics12081863 - 14 Apr 2023

Viewed by 1345

Abstract

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with [...] Read more.

A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200

Ω

, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm

^{2}

out of 1143

μ

m × 81

μ

m overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91

μ

W when under 1 V supply. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits Design)

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