Special Issue "CMOS Integrated Circuits Design"

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 April 2024 | Viewed by 2020

Special Issue Editors

Department of Engineering for Innovation, University of Salento, 73100 Lecce, Italy
Interests: design of integrated CMOS read-out interfaces for sensors; design of biomedical devices; e-noses development; agri-food sensing technologies
Department of Engineering for Innovation, University of Salento, 73100 Lecce, Italy
Interests: design of CMOS analog integrated circuits; base-band circuits for telecommunications; circuit interfaces for sensors

Special Issue Information

Dear Colleagues,

Complementary metal oxide semiconductor (CMOS) integrated circuits have been an enabling technology for the modern information age. The increase in both transistor density and performances, driven by Moore’s law, has been the leading factor in the technological advances of today’s complex mixed-signal systems. CMOS technology exhibits advantages for both digital and analog circuits in terms of reduced dimensions of transistors, higher working frequencies, and lower fabrication costs. However, the increasing circuit complexity of scaled CMOS technologies comes with many design challenges. On the digital side, although both static and dynamic power decrease for a single logic gate, the higher speed of circuits leads to signal integrity issues. Technology scaling is detrimental to the power consumption of analog circuits. Indeed, in order to achieve a target dynamic range with a decreased supply voltage, higher bias currents must be used to counteract the thermal noise contribution.

This Special Issue aims to collect original research articles of recent advances in CMOS integrated circuits design in scaled technologies. In particular, novel circuit design techniques, design strategies, and approaches aiming to improve the efficiency of both analog and digital integrated circuits in terms of performance, area, and power consumption are welcome.

The topics of interest for this Special Issue include but are not limited to:

  • Analog and digital integrated circuits design;
  • Read-out interfaces for sensors;
  • RF circuits for modern Internet-of-Things devices;
  • Analog-to-digital and digital-to-analog converters;
  • Circuits for telecommunications;
  • Circuits for signal processing;
  • Circuit strategies for energy efficiency;
  • Techniques for improving signal integrity in digital circuits.

Dr. Antonio Vincenzo Radogna
Dr. Stefano D'Amico
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2200 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog ICs
  • digital ICs
  • ADC
  • DAC
  • sensor interfaces
  • low-power ICs
  • signal processing

Published Papers (3 papers)

Order results
Result details
Select all
Export citation of selected articles as:

Research

Article
Low-Power Single Bitline Load Sense Amplifier for DRAM
Electronics 2023, 12(19), 4024; https://doi.org/10.3390/electronics12194024 - 25 Sep 2023
Viewed by 240
Abstract
With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since [...] Read more.
With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits. Full article
(This article belongs to the Special Issue CMOS Integrated Circuits Design)
Show Figures

Figure 1

Article
Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier
Electronics 2023, 12(15), 3209; https://doi.org/10.3390/electronics12153209 - 25 Jul 2023
Viewed by 486
Abstract
With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and [...] Read more.
With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product. Full article
(This article belongs to the Special Issue CMOS Integrated Circuits Design)
Show Figures

Figure 1

Article
A Three-Step Tapered Bit Period SAR ADC Using Area-Efficient Clock Generation
Electronics 2023, 12(8), 1863; https://doi.org/10.3390/electronics12081863 - 14 Apr 2023
Viewed by 816
Abstract
A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with [...] Read more.
A three-step tapered bit period asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is proposed to reduce the total DAC settling time by 47.7% compared to the non-tapered conversion time with less design overhead. Unlike conventional approaches, the SAR settling time analysis with both reference buffer output impedance and hardware overhead is first analyzed in each conversion step, which demonstrates that the three-step tapered bit period approach is the most time- and hardware efficient in our design. Additionally, area-efficient three-step clock generation is proposed by sharing resistors for delay generation, resulting in a small area increase of only 20.4% compared to the non-tapered clock generation. As a result, the proposed technique is used to reduce the reference buffer’s power and increase the sampling frequency. The maximum allowed output impedance of the reference buffer for SFDR > 92 dB becomes larger than that of the non-tapered design by 200 Ω, translated to a sampling frequency increase from 6 MHz to 8 MHz in our design. The proposed three-step tapered bit period using an area-efficient clock generator was designed in a 55 nm CMOS process. The clock generator occupies 0.00081 mm2 out of 1143 μm × 81 μm overall size. The power consumption of the 8 MS/s 12-bit SAR ADC with proposed clock generation is 128.91 μW when under 1 V supply. Full article
(This article belongs to the Special Issue CMOS Integrated Circuits Design)
Show Figures

Figure 1

Back to TopTop