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Electronics
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Architecture and CAD for Field-Programmable Gate Arrays (FPGAs)
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Architecture and CAD for Field-Programmable Gate Arrays (FPGAs)

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 2771

Special Issue Editor

Prof. Dr. Dinesh Bhatia

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Texas at Dallas, Richardson, TX 75083, USA
Interests: FPGA CAD; reconfigurable computing; domain-specific computing; deep learning architectures

Special Issue Information

Dear Colleagues,

Field-programmable gate array technology has advanced significantly, and FPGAs represent a substantial portion of overall semiconductor growth. Advances in the device architecture and supporting CAD tools have made FPGAs a very viable technology for implementing very large-scale high-performance systems. Recent progress in compilation technology has allowed easy translation of complex high-level software abstractions into efficient hardware implementations. FPGA based custom-computing systems are becoming especially important for domain-specific architectures due to their high performance-to-energy ratio.

This Special Issue will address advances from FPGA devices to FPGA systems and bring a compilation of recent research results in the areas listed below.

  • FPGA device architecture
  • CAD for FPGAs
  • Compilations tools for FPGAs
  • FPGA-based computing systems
  • FPGA applications

Prof. Dr. Dinesh Bhatia
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGAs
  • EDA (electronic design automation)
  • reconfigurable computing
  • compilation
  • accelerators
  • domain-specific computing

Published Papers (1 paper)

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Research

23 pages, 2845 KiB  
Article
VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC
by Bushra Sultana, Anees Ullah, Arsalan Ali Malik, Ali Zahir, Pedro Reviriego, Fahad Bin Muslim, Nasim Ullah and Waleed Ahmad
Electronics 2021, 10(8), 899; https://doi.org/10.3390/electronics10080899 - 09 Apr 2021
Cited by 2 | Viewed by 2133
Abstract
Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, [...] Read more.
Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches. Full article
(This article belongs to the Special Issue Architecture and CAD for Field-Programmable Gate Arrays (FPGAs))
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