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20 pages, 373 KiB

Open AccessArticle

A Hardware Trojan Detection and Diagnosis Method for Gate-Level Netlists Based on Machine Learning and Graph Theory

by Junjie Wang, Guangxi Zhai, Hongxu Gao, Lihui Xu, Xiang Li, Zeyu Li, Zhao Huang and Changjian Xie

Electronics 2024, 13(1), 59; https://doi.org/10.3390/electronics13010059 - 21 Dec 2023

Viewed by 965

Abstract

The integrated circuit (IC) supply chain has become globalized, thereby inevitably introducing hardware Trojan (HT) threats during the design stage. To safeguard the integrity and security of ICs, many machine learning (ML)-based solutions have been proposed. However, most existing methods lack consideration of [...] Read more.

The integrated circuit (IC) supply chain has become globalized, thereby inevitably introducing hardware Trojan (HT) threats during the design stage. To safeguard the integrity and security of ICs, many machine learning (ML)-based solutions have been proposed. However, most existing methods lack consideration of the integrity of HTs, thereby resulting in lower true negative rates (TNR) and true positive rate (TPRs). Therefore, to solve these problems, this paper presents a HT detection and diagnosis method for gate-level netlists (GLNs) based on ML and graph theory (GT). In this method, to address the issue of nonuniqueness in submodule partition schemes, the concept of “Maximum Single-Output Submodule (MSOS)” and a partition algorithm are introduced. In addition, to enhance the accuracy of HT diagnosis, we design an implant node search method named breadth-first comparison (BFC). With the support of the aforementioned techniques, we have completed experiments on HT detection and diagnosis. The HT implantation examples selected in this article are sourced from Trust-Hub. The experimental results demostrate the following: (1) The detection method proposed in this article, when detecting gate-level hardware trojans (GLHTs), achieves a TPR exceeding 95%, a TNR exceeding 37%, and F1 values exceeding 97%. Compared to existing methods, this method has improved the TNR for GLHTs by at least 25%. (2) The TPR for diagnosing GLHTs is consistently above 93%, and the TNR is 100%. Compared to existing methods, this method has achieved approximately a 4% improvement in the TPR and a 15% improvement in the TNR for GLHT diagnosis. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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19 pages, 631 KiB

Open AccessArticle

Research on Cache Coherence Protocol Verification Method Based on Model Checking

by Yiqiang Zhao, Boning Shi, Qizhi Zhang, Yidong Yuan and Jiaji He

Electronics 2023, 12(16), 3420; https://doi.org/10.3390/electronics12163420 - 11 Aug 2023

Viewed by 1342

Abstract

This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the processor and the correctness of the cache [...] Read more.

This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the processor and the correctness of the cache function. The main idea of this method is to analyze the register transfer level (RTL) code directly at the module level and variable level, and extract the key modules and key variables according to the code information. Then, based on key variables, conditional behavior statements are retrieved from the code, and unnecessary statements are deleted. The model construction and simplification of related core states are completed automatically, while also simultaneously generating the attribute library to be verified, using “white list” as the construction strategy. Finally, complete cache consistency protocol verification is implemented in the model detector UPPAAL. Ultimately, this mechanism reduces the 142 state-transition path-guided global states of the cache module to be verified into 4 core functional states driven by consistency protocol implementation, effectively reducing the complexity of the formal model, and extracting 32 verification attributes into 6 verification attributes, reducing the verification time cost by 76.19%. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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21 pages, 1494 KiB

Open AccessArticle

A Practical Non-Profiled Deep-Learning-Based Power Analysis with Hybrid-Supervised Neural Networks

by Fancong Kong, Xiaohua Wang, Kangran Pu, Jingqi Zhang and Hua Dang

Electronics 2023, 12(15), 3361; https://doi.org/10.3390/electronics12153361 - 06 Aug 2023

Viewed by 1153

Abstract

With the rapid advancement of deep learning, the neural network has become the primary approach for non-profiled side-channel attacks. Nevertheless, challenges arise in practical applications due to noise in collected power traces and the substantial amount of data required for training deep learning [...] Read more.

With the rapid advancement of deep learning, the neural network has become the primary approach for non-profiled side-channel attacks. Nevertheless, challenges arise in practical applications due to noise in collected power traces and the substantial amount of data required for training deep learning neural networks. Additionally, acquiring measuring equipment with exceptionally high sampling rates is difficult for average researchers, further obstructing the analysis process. To address these challenges, in this paper, we propose a novel architecture for non-profiled differential deep learning analysis, employing a hybrid-supervised neural network. The architecture incorporates a self-supervised autoencoder to enhance the features of power traces before they are utilized as training data for the supervised neural network. Experimental results demonstrate that the proposed architecture not only outperforms traditional differential deep learning networks by providing a more obvious distinction, but it also achieves key discrimination with reduced computational costs. Furthermore, the architecture is evaluated using small-scale and downsampled datasets, confirming its ability recover correct keys under such conditions. Moreover, the altered architecture designed for data resynchronization was proved to have the ability to distinguish the correct key from small-scale and desynchronized datasets. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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19 pages, 1635 KiB

Open AccessArticle

A Quantitative Analysis of Non-Profiled Side-Channel Attacks Based on Attention Mechanism

by Kangran Pu, Hua Dang, Fancong Kong, Jingqi Zhang and Weijiang Wang

Electronics 2023, 12(15), 3279; https://doi.org/10.3390/electronics12153279 - 30 Jul 2023

Viewed by 906

Abstract

In recent years, the deep learning method has emerged as a mainstream approach to non-profiled side-channel attacks. However, most existing methods of deep learning-based non-profiled side-channel attack rely on traditional metrics such as loss and accuracy, which often suffer from unclear results in [...] Read more.

In recent years, the deep learning method has emerged as a mainstream approach to non-profiled side-channel attacks. However, most existing methods of deep learning-based non-profiled side-channel attack rely on traditional metrics such as loss and accuracy, which often suffer from unclear results in practical scenarios. Furthermore, most previous studies have not fully considered the properties of power traces as long time-series data. In this paper, a novel non-profiled side-channel attack architecture is proposed, which incorporates the attention mechanism and derives a corresponding attention metric. By attaching the attention mechanism after the network layers, the attention mechanism provides a quantitative prediction of correct key. Moreover, this architecture can effectively extract and analyze the features from long power traces. The success rate on different datasets is at least 86%, which demonstrates the superior reliability of this architecture compared to other works when facing various countermeasures and noise. Notably, even in scenarios where traditional loss and accuracy metrics fail to provide reliable results, the proposed attention metric remains capable of accurately distinguishing the correct key. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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17 pages, 591 KiB

Open AccessArticle

A Low-Cost High-Performance Montgomery Modular Multiplier Based on Pipeline Interleaving for IoT Devices

by Hongshuo Li, Shiwei Ren, Weijiang Wang, Jingqi Zhang and Xiaohua Wang

Electronics 2023, 12(15), 3241; https://doi.org/10.3390/electronics12153241 - 27 Jul 2023

Cited by 1 | Viewed by 1040

Abstract

Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the [...] Read more.

Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03

μ

s and 2.13

μ

s, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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23 pages, 2510 KiB

Open AccessArticle

An Evolutionary Game Theory-Based Method to Mitigate Block Withholding Attack in Blockchain System

by Xiao Liu, Zhao Huang, Quan Wang and Bo Wan

Electronics 2023, 12(13), 2808; https://doi.org/10.3390/electronics12132808 - 25 Jun 2023

Cited by 3 | Viewed by 998

Abstract

Consensus algorithms are the essential components of blockchain systems. They guarantee the blockchain’s fault tolerance and security. The Proof of Work (PoW) consensus algorithm is one of the most widely used consensus algorithms in blockchain systems, using computational puzzles to enable mining pools [...] Read more.

Consensus algorithms are the essential components of blockchain systems. They guarantee the blockchain’s fault tolerance and security. The Proof of Work (PoW) consensus algorithm is one of the most widely used consensus algorithms in blockchain systems, using computational puzzles to enable mining pools to compete for block rewards. However, this excessive competition for computational power will bring security threats to blockchain systems. A block withholding (BWH) attack is one of the most critical security threats blockchain systems face. A BWH attack obtains the reward of illegal block extraction by replacing full proof with partial mining proof. However, the current research on the BWH game could be more extensive, considering the problem from the perspective of a static game, and it needs an optimal strategy that dynamically reflects the mining pool for multiple games. Therefore, to solve the above problems, this paper uses the method of the evolutionary game to design a time-varying dynamic game model through the degree of system supervision and punishment. Based on establishing the game model, we use the method of replicating dynamic equations to analyze and find the optimal strategy for mining pool profits under different BWH attacks. The experimental results demonstrate that the mining pools will choose honest mining for the best profit over time under severe punishment and high supervision. On the contrary, if the blockchain system is supervised with a low penalty, the mining pools will eventually choose to launch BWH attacks against each other to obtain the optimal mining reward. These experimental results also prove the validity and correctness of our model and solution. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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15 pages, 3759 KiB

Open AccessArticle

Hardware Design and Implementation of a Lightweight Saber Algorithm Based on DRC Method

by Weifang Zheng, Huihong Zhang, Yuejun Zhang, Yongzhong Wen, Jie Lv, Lei Ni and Zhiyi Li

Electronics 2023, 12(11), 2525; https://doi.org/10.3390/electronics12112525 - 03 Jun 2023

Viewed by 1277

Abstract

With the development of quantum computers, the security of classical cryptosystems is seriously threatened, and the Saber algorithm has become one of the potential candidates for post-quantum cryptosystems (PQCs). To address the problems of long delay and the high power consumption of Saber [...] Read more.

With the development of quantum computers, the security of classical cryptosystems is seriously threatened, and the Saber algorithm has become one of the potential candidates for post-quantum cryptosystems (PQCs). To address the problems of long delay and the high power consumption of Saber algorithm hardware implementation, a lightweight Saber algorithm hardware design scheme based on the joint optimization of data readout and clock (DRC) was proposed. Firstly, an analysis was carried out on the hardware architecture, timing overhead and power consumption distribution of the Saber algorithm, and the key circuits that limit the performance of the algorithm were identified; secondly, a dual-port SRAM parallel reading method was adopted to improve the data reading efficiency and reduce the timing overhead of double data reading in the multiplier module. Then, a clock gating technology was used to reduce the dynamic flipping probability of internal registers and reduce the hardware power consumption of the Saber algorithm; finally, data reading and clock gating were jointly optimized to design a high-speed and low-power Saber algorithm hardware IP core. Lightweight IP cores were integrated into RISC-V SoC systems via APB bus in a TSMC 65 nm process to complete the digital back-end design. The experimental results show an IP core area of 0.99 mm² and power consumption of 8.49 mW, which is 33% lower than that reported in the related literature. Under 72 MHz & 1 V operating conditions, the number of clock cycles for the Saber algorithm’s key generation, encryption and decryption are 3315, 9204 and 1420, respectively. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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Review

Jump to: Research

22 pages, 2955 KiB

Open AccessReview

Building Trust in Microelectronics: A Comprehensive Review of Current Techniques and Adoption Challenges

by Kwame Nyako, Suman Devkota, Frank Li and Vamsi Borra

Electronics 2023, 12(22), 4618; https://doi.org/10.3390/electronics12224618 - 11 Nov 2023

Cited by 1 | Viewed by 1332

Abstract

The field of microelectronics has experienced extensive integration into various aspects of our everyday lives, evident via its utilization across a wide range of devices such as cellphones, airplanes, computers, wristwatches, and other similar technologies. Microelectronics are vital to the healthcare and defense [...] Read more.

The field of microelectronics has experienced extensive integration into various aspects of our everyday lives, evident via its utilization across a wide range of devices such as cellphones, airplanes, computers, wristwatches, and other similar technologies. Microelectronics are vital to the healthcare and defense industries, making them vulnerable to counterfeit products. Currently, the complicated global microelectronics supply chain involves the production of varied components in multiple places, resulting in tremendous risk. In this scenario, it is possible for hostile or adversarial actors to exploit the situation by intentionally introducing counterfeit components. This hostile behavior could steal data or use these components as remote kill switches. To address these problems, enormous resources are being committed to research, innovation, and development to build trust in microelectronics. This research study provides a thorough analysis of the taxonomy associated with prominent attack, detection, and avoidance models in the realm of counterfeit microelectronics. This research aims to improve our understanding of dependable microelectronics. Prevention strategies like Physical Unclonable Functions (PUFs) and machine learning (ML), and detection methods like aging-based fingerprints are reviewed in this study. Finally, we underscore the significance of interdisciplinary cooperation, commitment to norms, and proactive methods. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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26 pages, 2247 KiB

Open AccessReview

A Survey of Side-Channel Leakage Assessment

by Yaru Wang and Ming Tang

Electronics 2023, 12(16), 3461; https://doi.org/10.3390/electronics12163461 - 15 Aug 2023

Viewed by 1278

Abstract

As more threatening side-channel attacks (SCAs) are being proposed, the security of cryptographic products is seriously challenged. This has prompted both academia and industry to evaluate the security of these products. The security assessment is divided into two styles: attacking-style assessment and leakage [...] Read more.

As more threatening side-channel attacks (SCAs) are being proposed, the security of cryptographic products is seriously challenged. This has prompted both academia and industry to evaluate the security of these products. The security assessment is divided into two styles: attacking-style assessment and leakage detection-style assessment. In this paper, we will focus specifically on the leakage detection-style assessment. Firstly, we divide the assessment methods into Test Vector Leakage Assessment (TVLA) and its optimizations and summarize the shortcomings of TVLA. Secondly, we categorize the various optimization schemes for overcoming these shortcomings into three groups: statistical tool optimizations, detection process optimizations, and decision strategy optimizations. We provide concise explanations of the motivations and processes behind each scheme, as well as compare their detection efficiency. Through our work, we conclude that there is no single optimal assessment scheme that can address all shortcomings of TVLA. Finally, we summarize the purposes and conditions of all leakage detection methods and provide a detection strategy for actual leakage detection. Additionally, we discuss the current development trends in leakage detection. Full article

(This article belongs to the Special Issue Computer-Aided Design for Hardware Security and Trust)

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