DigitalNizam: Shaping the Future of Pakistani Elections through Secure Field-Programmable Gate Array-Based Voting Solutions ^†

Abstract

This paper represents the ways in which a secure and reliable voting machine could be implemented using hardware descriptive language, which in this case is Verilog. In order to emphasize security, the proposed design is implemented in two ways. The first variant is a basic version comprising some basic safety protocols; however, the subsequent variant is a safer kind of FPGA-based voting machine. Furthermore, concrete illustration is presented using the Vivado and Artix-7-based FPGA Basys-3. Finally, the obtained conclusions seem to be encouraging to a certain extent, as, evidently, the system provides robust and assured voting, along with minimizing latency and power consumption. In addition to this, this design could be utilized as a starting point for the development of superior voting systems utilizing FPGAs in the future.

1. Introduction

In the realm of democracy, the integrity and transparency of elections play a vital role in shaping the fabric of a nation. In Pakistan, like many other countries, the electoral process has faced numerous challenges, including issues of fraud, manipulation, and a lack of transparency. These obstacles not only undermine the trust and confidence of citizens but also hinder the growth and stability of the democratic system.

To address these critical concerns, our project focuses on the development of a state-of-the-art electronic voting machine (EVM) using FPGA technology. Field-Programmable Gate Arrays (FPGAs) offer immense potential in revolutionizing the electoral landscape, providing a robust and secure platform for conducting elections. By leveraging the power of FPGA-based EVMs, we aim to introduce a new era of transparency, efficiency, and accountability to the Pakistani electoral process.

Through meticulous design and implementation, our project seeks to overcome the existing limitations of traditional voting systems and create an EVM that is resistant to tampering, ensures the accuracy of votes, and guarantees the privacy of individual voters. By harnessing the advanced capabilities of FPGA technology, we aim to enhance the integrity, reliability, and overall confidence in the electoral system of Pakistan. The significance of our project extends beyond the boundaries of technology. By fostering a secure and efficient voting environment, we strive to strengthen democratic principles and empower citizens to actively participate in shaping their nation’s future. With a focus on transparency, fairness, and inclusivity, our FPGA-based electronic voting machine endeavors to restore public trust and confidence in the electoral process.

2. Literature Review

Electronic Voting Machines (EVMs) revolutionize voting with efficiency, accuracy, and transparency. They offer accessibility, multilingual support, and swift result announcements. EVM types include paper-based, web-based, mobile-based, microcontroller-based, and FPGA-based systems, each with distinct features. Paper-based voting systems are vulnerable to manipulation, bias, errors, and tampering [1]. The absence of an electronic trail hinders verification and auditing.

Web-based voting systems improve upon paper-based voting [2], but challenges persist in ensuring integrity, confidentiality, transparency, and robustness. Vulnerabilities like theft or detection of OTPs and passwords compromise security, while facial recognition systems can be manipulated [3]. Strong security and robustness remain challenges for web-based voting.

Studies [4,5] introduced mobile-based electronic voting systems, but lacked thorough discussions on reliability, vulnerabilities, privacy concerns, security measures, authentication mechanisms, transparency, and usability.

Mobile-based voting systems are susceptible to security risks like malware, unauthorized access, and data breaches. Rare technical malfunctions can occur in DRE voting machines during vote recording and tallying [6]. To ensure reliability and accuracy, rigorous testing, maintenance, and strong security measures are crucial for both systems.

Microcontroller-based EVMs, studied for secure voting systems, revealed significant security vulnerabilities in integrating fingerprint technology [7]. In addition to this, as they are primarily based on software-based security practices, it makes them susceptible to any known software vulnerability which has not been patched yet. Some of these vulnerabilities affecting integrity and availability were found in ATmega16-based EVMs [8]. ARM9-based fingerprint EVMs had flaws in password detection, raising result alteration concerns [9]. Raspberry Pi-based EVMs faced scalability limitations due to low memory capacity [10].

The e-voting system in [11] lacked a crucial security feature, exposing it to tampering. In [12], integrating extra hardware components compromised the integrity and confidentiality of the voting process. Enhancing security in EVMs is imperative.

FPGA-based EVMs offer a promising solution with enhanced security, efficient data processing, scalability, and flexibility. Features like hardware-based random number generation, secure data storage, and real-time monitoring further enhance security and transparency compared to Raspberry Pi-based solutions. FPGAs outperform MCUs and Raspberry Pis in memory and security. This is evident by the fact that FPGAs can be expanded, making them ideal for voting areas which vary based on demographic changes. They have hardware-based designs with custom security features, making them resilient to software and hardware attacks.

In Pakistan, elections face challenges such as poor execution, fraud, and a lack of transparency, resulting in diminished trust in the democratic process [13]. This project introduces a secure electronic voting system using a Basys3 FPGA board to enhance the integrity and confidentiality of the voting process. The aim is to restore citizens’ faith in elections and promote transparency, thereby strengthening the democratic framework in Pakistan.

3. Finite State Machine: A Key Component of the System

The project aims to create a scaled-down electronic voting machine that can be used at the local level. It addresses the issue of outdated ballot systems and insecure email-based voting methods. Two variants of the system are proposed, offering an innovative and secure approach to voting. The FPGA-based system seamlessly integrates advanced technology with strong security measures.

The first variant of the system is designed to be simple and efficient, accommodating four candidates. It ensures confidentiality and transparency by limiting access to the voting results and total votes cast to the system owner. It is named “SecureBallot Lite”.

The second variant focuses on robust security measures and introduces features to enhance the voting experience. It presents three candidates and allows voters to see the total votes cast in real time. The winning candidate number is displayed only after the voting is completed and the correct security code is entered on the FPGA. It is named “UltraSecureVote”. Both variants use a general Finite State Machine (FSM) to facilitate a clear understanding of the system’s operation.

In Figure 1, initially, the system is in the “idle” stage until the reset signal is triggered. It then transitions to the “voting_on” state, where votes can be cast using the push buttons. Upon the stop signal being triggered, the FSM enters the “show_results” state, displaying the voting outcomes. In Figure 2, initially, the system is in the “idle” state; the system is ready for use, waiting for the reset signal to transition. In the “security_activated” state, the owner enters a secret switch code to initiate the security system. The “voting_on” state allows voters to cast their votes using push buttons, with a limit of 99 votes. Upon reaching the limit, the system transitions to “voting_off” and displays the winner in the “display_result” state. The owner can also force-stop the process using the “force_stop” state.

4. Discussion

4.1. Variant 1: SecureBallot Lite

4.1.1. RTL for SecureBallot Lite

The RTL diagram depicted in Figure 3 illustrates the presence of four buttons positioned on the left side. These buttons, namely bc1, bc2, bc3, and bc4, serve as modules through which users can input their votes for their preferred candidates. Each button corresponds to a specific candidate. Due to the limited number of push buttons available on the board, we have restricted the system to accommodate only four candidates. However, if the need arises to expand the system, additional push buttons can be incorporated independently.

Subsequently, we have a module named VL, which performs the task of validating the votes entered by the voters. Our system incorporates a security measure where the voter must press the button for approximately 1 second to ensure that accidental inputs or glitches do not result in the recording of a vote. This module safeguards the integrity of the voter’s record by first verifying its validity before allowing the valid vote to be registered in the system. Additionally, the diagram displays arrays that serve as storage for candidate records. Once the system verifies and approves a vote as valid, it will be stored in the corresponding arrays for future reference.

Moving on, we have two additional modules: the MC module and the LE module. The MC module carries several tasks. Firstly, it handles the reset button, which, when pressed, promptly resets all register values and restarts the system’s operation. The MC module also produces a signal called sel, which is subsequently directed to the LE module.

The LE module is responsible for displaying the votes on the LED lights corresponding to the respective candidates, but this display only occurs when the results option is activated. The signal sel guarantees that solely the votes corresponding to the chosen candidate are exhibited on the screen.

4.1.2. Timming Diagram

The initial evaluation of the system involved conducting tests using simulation software. For this purpose, a testbench was made with all the test cases, and the subsequent outcome was the generation of a timing diagram.

We can observe in Figure 4 that at 200,000 picoseconds (ps), Button 1 was pressed for a very brief duration, resulting in no alteration of the state of the LED. However, when Button 1 was pressed for an extended duration, the LED state transitions to off, which signifies that the vote has been successfully recorded and validated. Likewise, Button 2 was pressed twice in the case of candidate 2. Upon switching to mode 1, which displays the results, it becomes evident that two votes were duly registered for candidate 2. The timing diagram provides strong evidence that the simulation faithfully represents the system’s behavior. This validation allows us to confidently move forward and conduct hardware testing for this system.

4.2. Variant 2: UltraSecureVote

RTL Diagram for UltraSecureVote

The RTL diagram in Figure 5 includes four buttons on the left-hand side. The btncvov button is reserved for the authorized officer to start and stop the voting process, while btndebounce resets the system. As part of its basic security features, the Basys3 FPGA board utilizes a specific sequence of all 16 switches to generate a unique key. This key is used to initiate and terminate the voting process, ensuring a secure and controlled operation. btn1, btn2, and btn3 are used to input candidate votes, allowing a maximum of three voters in this implementation of the voting system of FPGAs.

Module SM serves as the state machine, indicating the readiness for voting and the need for the administrator’s code. It functions in a way similar to a physical polling booth, exhibiting a single round of voting. The admin code is validated through FPGA buttons, activating the LEDs upon successful validation. The state machine has four states: IDLE, Voting-enabled, Voting-disabled, and exhibit-win. A transition occurs when the admin enters their code, and the success of a candidate or a draw is determined through conditions.

The RTL diagram includes clock modules: OneHz and TwoHz. OneHz slows the clock to prevent multiple votes, while TwoHz increases it for LED flashing. The LED-driver module controls LED states based on the input code. The implementation of clock division in the project results in reduced power consumption and latency. By adjusting the clock frequency, the system achieves optimized operation timing, minimizing delays and enhancing responsiveness. This approach allows for selective module activation, maximizing efficiency and conserving power. The binbcd and seg7 modules control the Basys-3 board’s seven-segment displays. The right-side LEDs show the vote count (up to 99), and the left-side LED displays the winning candidate (1, 2, or 3) or 0 for a draw.

5. Hardware Implementation

The hardware implementation validates the RTL diagrams. The right-side LED displays the sum of votes cast till now. The sum of votes is displayed for the purpose of this experiment, in order to validate whether or not the number of votes changes after the button is pressed. Figure 6 shows the results and Figure 7 shows the voter voting, with the LEDs blinking in an alternating fashion, displayed as mentioned in the explanation of the RTL diagram.

6. Conclusions

In conclusion, this work shows the viability and efficiency of an FPGA-based secure voting machine. The created system addresses the goal of creating a safe voting environment with hardware-based authentication and tamper detection. The device strengthens the voting procedure’s confidentiality and integrity, increasing public confidence in the results of elections. The project stands out from previous studies in terms of memory and security. Unlike microcontroller-based systems and Raspberry Pi, it utilizes a Basys3 FPGA board, which offers ample memory resources and flexible memory management. This allows the system to overcome memory constraints and efficiently handle voting data.

Furthermore, it prioritizes security by leveraging the Basys3 FPGA board’s onboard security features. This eliminates the need for extra hardware, minimizing vulnerabilities associated with external devices. With secure key management and enhanced integrity and confidentiality measures, the system provides robust protection against tampering and unauthorized access. This paper advances the study of underlying secure voting systems and encourages improvements in assuring free and honest elections, even though scalability and performance optimization still require more study.