High Gain Boost Converter with Reduced Voltage in Capacitors for Fuel-Cells Energy Generation Systems

Abstract

This work presents a power-electronics based system for renewable energy applications, the system is driven with an only one switch quadratic type boost converter, the discussed converter is based on a stack of switching stages which provide a large voltage gain, a desirable feature for fuel cell generation systems, the converters gain function is the quadratic boost-type converters; furthermore, the topology can be extended. The major benefit of the topology is that there is not a capacitor that sustains the entire output voltage, in contrast to other similar topologies in which there is a capacitor rated to the output port voltage, there is no high voltage capacitor in this system. Experimental verification is presented to confirm the system principles; experiments included a fuel cell emulator that was built and used for the experiments.

1. Introduction

Step-up converters are widely used in electronic systems, such as green energy production systems like those based on fuel cells or photovoltaic panels. Converters applied to those applications usually require to step-up the low voltage provided by the fuel cell to meet the requirements of grid-tie inverters.

Several solutions exist that can fulfill the challenge and achieve high voltage conversion ratios, for example, topologies based on magnetic coupling such as transformers and/or coupled inductors [1,2,3].

Another plausible solution is the use of transformer-less topologies, which can be built with commercial components (off-the-shelf), which is an advantage for magnetic coupling-based converters, transformer-less topologies provide a reduced size solution. Transformer-less converters can be based on several principles such as (1) voltage multipliers based on switched capacitors [4,5]; (2) combination of circuits which input are parallel connected, and which outputs are connected in series [6,7,8]; (3) quadratic topologies [9,10], etc.

This article presents a boots type dc–dc converter with quadratic voltage gain and a reduced number of active components (it uses only one transistor). Previously presented in [11], in this case, the converter is intended to be used with a fuel-cell based renewable energy generation system, the converter quadratic-gain makes it a good option for the fuel-cell based application, in which a low voltage with variable amplitude requires to be boosted and regulated, the converter under study is based on a stackable structure of several switching stages, their main characteristic is a relatively high voltage gain given in a quadratic type gain equation, a desirable feature for fuel cell generation systems. The major benefits of the quadratic converter are: the output voltage is provided by all capacitors connected in additive series, in contrast with other circuits that have several capacitors, including a large capacitor that sustains the (relatively large) voltage at the output port. The system operation and the major benefits of the proposed system are corroborated with experimental results; a fuel cell emulator was built and used for the experimental results.

2. Quadratic Boost Converter

This section describes the discussed topology; the principle operation is also described. The quadratic topology is displayed in Figure 1; it is made by the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor): s, fast recovery diodes: s₁, ${\overline{s}}_1$, and ${\overline{s}}_2$, capacitors: C₁, and C₂, and inductors: L₁, and L₂.

2.1. Qualitative Comparison with Other Boost Type Converters

The classical boost topology and the quadratic boost topology are displayed in Figure 2. The major benefit of the quadratic converter shown in Figure 1, against the classic quadratic boost topology in Figure 2b, is that the output port voltage isn’t provided with only one capacitor, that capacitor would have to be rated to the output voltage, which is relatively high, the output port voltage in the discussed topology is provided with a series connection of the input port voltage and two both capacitors of the converter, each of them rated to a fraction of the output voltage.

Former quadratic types of topologies in the state-of-the-art are presented in [9,10,12,13,14]. For example, [9,14] in which a similar single-switch quadratic converter is presented, but in that case, only one capacitor has a reduced voltage compared to the traditional converter, and the output capacitor still supports the total output voltage, and stores the larger amount of energy.

In Figure 3, we illustrate the voltage stress across capacitors versus the duty ratio D in the discussed topology and the quadratic boost topology.

Voltages in Figure 3 are normalized to (divided over) the input source voltage, for instead, if D = 0.6, the voltage in C₂ for the new converter is around the input source voltage multiplied by four, while it is around six times the input voltage for the traditional converter, it is clear that for the entire range of duty cycle values, the voltages in capacitors for the topology in Figure 1 are always smaller than the voltage in capacitors for the topology in Figure 2b. This allows for reducing the price and volume of the system.

There are quadratic types of topologies in the state-of-the-art that perform switching ripple cancelation, in which series capacitors have shifted voltage ripple, for example, [15,16], in that case, those converters require at least two transistors and a particular PWM (Pulse-Width Modulation) strategy.

2.2. Mathematical Model and Operation Principle of the Converter

This section provides the mathematical model of the converter considering ideal components; this model can provide a reference for the converter operation. Losses produced by parasitic components tend to limit the real voltage gain of the converter; this limitation is derived and explained in Section 2.4.

The converter has two switching states, which are shown in Figure 1, those switching states can be used to derive the averaging model of the circuit, the derived model, which assumes that the voltage in capacitors and current through inductors have a small ripple, and inductors L₁ and L₂ operate in CCM (Continuous Conduction Mode).

When the transistor is closed, see Figure 1b, diode s₁ is also closed and conducts the current i_L1, the diode ${\overline{s}}_1$ is open since it is inversely polarized with (V_g + V_C1). In a similar manner, ${\overline{s}}_2$ is inversely polarized with (V_g + V_C1 + V_C2), which is actually the output port voltage. i_L1 rises during this switching state with a derivative equal to V_g/L₁, and i_L2 is also rising in this switching state with a derivative equal to (V_g + V_C1)/L₂. The mathematical model of the switching state would be given by Equations (1)–(4).

$$L_1\frac{d{i}_{L1}}{dt}=V_g$$

(1)

$$L_2\frac{d{i}_{L2}}{dt}=V_g+V_{C1}$$

(2)

$$C_1\frac{d{v}_{C1}}{dt}=i_{L2}-\frac{v_o}{R}$$

(3)

$$C_2\frac{d{v}_{C2}}{dt}=-\frac{v_o}{R}$$

(4)

In the other switching state, shown in Figure 1c, the current i_L1 drops with a derivative equal to −V_C1/L₁, the diode ${\overline{s}}_1$ closes charging capacitor C₁, the current i_L2 also decreases with a derivative equal to −V_C2/L₂, the diode ${\overline{s}}_2$ closes charging capacitor C₂, diode s₁ is inversely polarized with V_C2. The mathematical model of this state would be given by Equations (5)–(8).

$$L_1\frac{d{i}_{L1}}{dt}=-v_{C1}$$

(5)

$$L_2\frac{d{i}_{L2}}{dt}=-v_{C2}$$

(6)

$$C_1\frac{d{v}_{C1}}{dt}=i_{L1}-\frac{v_o}{R}$$

(7)

$$C_2\frac{d{v}_{C2}}{dt}=i_{L2}-\frac{v_o}{R}$$

(8)

The voltage at the output port V_o, see Figure 1, is given by the sum of voltage in all capacitors plus the input V_o = V_g + V_C1 + V_C2.

Considering the inductors current and capacitors voltage as state variables, the model of switching stages can be averaged to get the non-linear large-signal model given by Equations (9)–(12).

$$L_1\frac{d{i}_{L1}}{dt}=d{v}_g-\left(1-d\right)v_{C1}$$

(9)

$$L_2\frac{d{i}_{L2}}{dt}=d\left(v_g+v_{C1}\right)-\left(1-d\right)v_{C2}$$

(10)

$$C_1\frac{d{v}_{C1}}{dt}=-d{i}_{L2}+\left(1-d\right)i_{L1}-\frac{v_o}{R}$$

(11)

$$C_2\frac{d{v}_{C2}}{dt}=\left(1-d\right)i_{L2}-\frac{v_o}{R}$$

(12)

where d is the duty ratio, the proportion of time in which the transistor is closed, it is calculated by dividing the time period in which the MOSFET is closed over the full commutation or switching period T_S; the large-signal model can be used to get the equilibrium or steady-state. By zeroing the derivatives in Equations (9)–(12), the equilibrium would be described by Equations (13)–(16).

$$V_{C1}=\frac{D}{1-D}{V}_g$$

(13)

$$V_{C2}=\frac{D}{{\left(1-D\right)}^2}{V}_g$$

(14)

$$I_{L1}=\frac{1}{{\left(1-D\right)}^2}\frac{V_o}{R}$$

(15)

$$I_{L2}=\frac{1}{\left(1-D\right)}\frac{V_o}{R}$$

(16)

While the output voltage V_o is given, as mentioned, by Equation (17).

$$V_o=V_g+V_{C1}+V_{C2}=\frac{1}{{\left(1-D\right)}^2}{V}_g$$

(17)

Equation (17) is (as expected) the quadratic gain of the boost converter.

From Figure 1 and the mathematical model of the switching stages, the principle of operation can be explained in the following manner:

(1)

When the transistor is closed, see Figure 1b, inductors have positive voltage (while capacitors have negative current), which results in an increase of the energy stored in inductors, the current in inductors have a positive derivative, equations, inductor L₁ is getting charged with energy coming from the input source V_g (see Equation (1)), while inductor L₂ is getting charged with energy coming from both the input source V_g and capacitor C₁ (see Equation (2)).

(2)

When the transistor is open, see Figure 1c, capacitors have positive current (while inductors have negative voltage), which results in an increase of the energy stored in capacitors, inductor L₁ transfer energy to capacitor C₁ and inductor L₂ transfer energy to capacitor C₂.

(3)

The energy flows from the input source to L₁, when the transistor is closed, from L₁ to C₁ when the transistor is open, from C₁ (and V_g) to L₂ when the transistor is closed, from L₂ to C₂ when the transistor is open, and from C₂ (and C₁, and V_g) to the load during all the time.

(4)

The energy conservation produces that since the output voltage is larger than the input voltage, with a voltage gain given by Equation (17), the input current is larger than the output current with the same proportion. This can be observed from Equation (15), the dc input current is the same as I_L1 since the capacitor C₁ cannot drain dc current.

2.3. Extending the Topology to an N to the Power Boost Converter

The discussed circuit can be extended to an N to the power exponential boost converter; Figure 4 shows the generalized converter with N switching stages.

A general expression for the output port voltage gain can be derived by observing that inductor L₃ is charged (when the switch is on) by the input port voltage plus the sum of all capacitors in the previous switching stages, inductor L₁ is charged only with v_g, inductor L₂ is getting charged by v_g + v_C1, inductor L₃ is charged with v_g + v_C1 + v_C2, etc. The dynamic equation of L₃ would be written as

$$L_3\frac{d{i}_{L3}}{dt}=d\left(v_g+v_{C1}+v_{C2}\right)+\left(1-d\right)\left(-v_{C3}\right)$$

(18)

The dynamic equation of L_N would be written as Equation (19).

$$L_N\frac{d{i}_{LN}}{dt}=d\left(v_g+v_{C1}+\dots +v_{C\left(N-1\right)}\right)+\left(1-d\right)\left(-v_{CN}\right)$$

(19)

The voltage in capacitor C₃ would be expressed as Equation (20).

$$V_{C3}=\frac{D}{\left(1-D\right)}\left(V_g+V_{C1}+V_{C2}\right)$$

(20)

The voltage in the capacitor C_N would be expressed as Equation (21).

$$V_{CN}=\frac{D}{\left(1-D\right)}\left(V_g+V_{C1}+V_{C2}+\dots +V_{C\left(N-1\right)}\right)$$

(21)

The output voltage of a converter with three switching stages would be expressed as Equation (22).

$$V_{out\left(N=3\right)}=\left(V_g+V_{C1}+V_{C2}+V_{C3}\right)$$

(22)

This can be solved by remembering Equation (23).

$$V_g+V_{C1}+V_{C2}=V_g\frac{1}{{\left(1-D\right)}^2}$$

(23)

By substituting Equation (23) in Equation (20), the voltage V_C3 can be expressed as Equation (24).

$$V_{C3}=\frac{D}{\left(1-D\right)}\left(V_g\frac{1}{{\left(1-D\right)}^2}\right)=V_g\frac{D}{{\left(1-D\right)}^3}$$

(24)

By considering Equations (20) and (23), the output voltage of a converter with three switching stages would be expressed as Equation (25).

$$V_{out\left(N=3\right)}=\left(V_g\frac{1}{{\left(1-D\right)}^2}+V_g\frac{D}{{\left(1-D\right)}^3}\right)$$

(25)

$$V_{out\left(N=3\right)}=V_g\left(\frac{1}{{\left(1-D\right)}^2}+\frac{D}{{\left(1-D\right)}^3}\right)=\frac{V_g}{{\left(1-D\right)}^3}$$

(26)

Equation (26) is the cubic boost topology gain, with observations made in this procedure, Equation (19) can be rewritten as Equation (27).

$$L_N\frac{d{i}_{LN}}{dt}=d\left(v_{out\left(N-1\right)}\right)+\left(1-d\right)\left(-v_{CN}\right)$$

(27)

from which the voltage in the capacitor C_N can be expressed as Equation (28).

$$V_{CN}=\frac{D}{\left(1-D\right)}\left(V_{out\left(N-1\right)}\right)$$

(28)

and the output voltage of a converter with N switching stages would be expressed as Equation (29).

$$V_{out\left(N\right)}=V_{out\left(N-1\right)}+\frac{D}{\left(1-D\right)}\left(V_{out\left(N-1\right)}\right),V_{out\left(N\right)}=V_{out\left(N-1\right)}\left(1+\frac{D}{\left(1-D\right)}\right)=V_{out\left(N-1\right)}\frac{1}{\left(1-D\right)}$$

(29)

Each switching stage multiplies the previous voltage gain with a factor of the traditional boost gain; each switching stage adds an exponential to the previous voltage gain.

$$V_{out\left(N\right)}=V_g\frac{1}{{\left(1-D\right)}^N}$$

(30)

2.4. Real Voltage Gain Considering Inductor ESR (Equivalent Series Resistance)

The analysis provided in Section 2.2, does not include parasitic components, which affect the real voltage gain of the converter, especially those in the charging and discharging loop of inductors. This section is dedicated to analyzing this effect; for more information about the effects on parasitic components, readers may refer to [17,18,19,20,21,22,23,24,25,26,27].

The real gain, which considers losses, is smaller than the ideal, the main lossy element that limits the real gain is the inductor losses modeled as an equivalent series resistor ESR, due to the complexity of the circuit, the calculation requires an intermediate step. Therefore, we analyzed the real gain in a converter that contains only one inductor and capacitor, see Figure 5.

Observe that the circuits in Figure 5 contain the inductor ESR; when applying the averaging technique, this ESR would appear as a voltage drop in the inductors voltage equations, which according to the equivalent circuits in Figure 5b,c, can be expressed as Equations (31) and (32).

$$L\frac{d{i}_L}{dt}=d\left(v_g-R_L{i}_L\right)+\left(1-d\right)\left(-v_C-R_L{i}_L\right)$$

(31)

$$C\frac{d{v}_C}{dt}=d\left(-\frac{v_{out}}{R}\right)+(1-d)\left(i_L-\frac{v_{out}}{R}\right)$$

(32)

Equations (31) and (32) can be simplified to Equations (33) and (34).

$$L\frac{d{i}_L}{dt}=d{v}_g-\left(1-d\right)v_C-R_L{i}_L$$

(33)

$$C\frac{d{v}_C}{dt}=\left(1-d\right)i_L-\frac{v_{out}}{R}$$

(34)

The output voltage v_out is the series connection of the input voltage v_g plus the capacitor’s voltage. From Equations (33) and (34) the equilibrium can be derived, as well as in the last section, the state variables must be constant in the equilibrium, and by zeroing the left–hand–side of Equations (33) and (34) the steady-state can be expressed as Equations (35) and (36).

$$0=D{V}_g-\left(1-D\right)V_C-R_L{I}_L$$

(35)

$$0=\left(1-D\right)I_L-\frac{V_g+V_C}{R}$$

(36)

From Equation (36), the inductor current may be expressed as Equation (37).

$$I_L=\frac{V_g+V_C}{D’R}$$

(37)

By substituting Equation (37) into Equation (35), the capacitor voltage may be expressed as Equation (38).

$$V_C=V_g\frac{\left(D-\frac{R_L}{D’R}\right)}{\left(\left(1-D\right)+\frac{R_L}{\left(1-D\right)R}\right)}$$

(38)

The output voltage v_out is the series connection of the input voltage v_g plus the capacitor voltage (see Figure 5a), and then, by adding v_g plus Equation (38), the output voltage is expressed as Equation (39).

$$V_{out}=V_g\frac{1}{\left(1-D\right)+\frac{R_L}{\left(1-D\right)R}}$$

(39)

The output voltage port gain of the converter topology in Figure 5, which considers the equivalent series resistance in the inductance is calculated as Equation (40).

$$G=\frac{V_{out}}{V_g}=\frac{1}{\left(1-D\right)}\frac{1}{\left(1+\frac{R_L}{{\left(1-D\right)}^{2}R}\right)}$$

(40)

Equation (40) shows the same gain of the classical boost converter when considering parasitic resistance that limits the voltage across the inductor, those parasitic resistances may consider only the inductors ESR, or it may consider other parasitic resistances that appear in series with the inductor, such as the on-resistance in the MOSFET.

Equation (40) may also be represented in a circuital manner, as Figure 2a [13].

The circuit in Figure 6 is based on transformers with (1 − D):1 turns ratio. The circuit representation of Equation (40) allows us to derive a general representation of the converter since the circuital representation of the cascade connection of switching stages is simpler to solve than in the algebraic equations.

If two switching stages are connected in a manner, then the second converter is the load of the first one, both converters may be represented by Figure 6b, the input source and the first resistor may be pushed to the secondary side of the first transformer [13], and the total circuit would be equal to the one shows in Figure 6c, similar to Figure 6a and have the gain represented by Equation (40) when the total inductor resistance is written as Equation (41).

$$R_L=\frac{R_{L1}}{{\left(1-D\right)}^2}+R_{L2}$$

(41)

In the same manner, three switching stages in cascaded would have the same gain in Equation (40) when the total inductor resistance would be

$$R_L=\frac{R_{L1}}{{\left(1-D\right)}^4}+\frac{R_{L2}}{{\left(1-D\right)}^2}+R_{L3}$$

(42)

Finally, if N switching stages are connected in cascaded, Equation (40) holds when the total inductor resistance is

$$R_{LT}=\frac{R_{L1}}{{\left(1-D\right)}^{2^{\left(N-1\right)}}}+\frac{R_{L2}}{{\left(1-D\right)}^{2^{\left(N-2\right)}}}+\dots +\frac{R_{LN-1}}{{\left(1-D\right)}^{2^{\left(N-\left(N-1\right)\right)}}}+\frac{R_{LN}}{{\left(1-D\right)}^{2^{\left(N-N\right)}}}$$

(43)

2.5. Component Selection

Passive components are usually selected according to the desired maximum ripple, when the switch is on, see Figure 2a, both inductors are getting charged; in this switching state, their current ripples are calculated with Equations (34) and (35).

$$\mathsf{\Delta }{i}_{L1}=\frac{V_g}{2L_1}D{T}_S$$

(44)

$$\mathsf{\Delta }{i}_{L2}=\frac{V_g+V_{C1}}{2L_2}D{T}_S$$

(45)

where T_S = 1/f_S is the converter’s switching period, the inverse of the switching frequency, from Figure 4, the current ripple in an arbitrary inductor L_x (when the switch is on) can be expressed as Equation (46).

$$\mathsf{\Delta }{i}_{Lx}=\frac{\left(V_g+V_{C1}+\dots +V_{C\left(x-1\right)}\right)}{2L_x}D{T}_S$$

(46)

From Figure 2b, when the switch is off, both capacitors are getting charged, their voltage ripples mathematical expressions are Equations (47) and (48).

$$\mathsf{\Delta }{v}_{C1}=\frac{\left(I_o-I_{L1}\right)}{2C_1}\left(1-D\right)T_S$$

(47)

$$\mathsf{\Delta }{v}_{C2}=\frac{\left(I_o-I_{L2}\right)}{2C_2}\left(1-D\right)T_S$$

(48)

From Figure 4, the current ripple in an arbitrary capacitor C_x (when the switch is off) can be expressed as Equation (46).

$$\mathsf{\Delta }{v}_{Cx}=\frac{\left(I_o-I_{Lx}\right)}{2C_x}\left(1-D\right)T_S$$

(49)

From Figure 2b, when the switch is on, both capacitors are getting charged with and, their voltage ripple is calculated with Equation (46). From the provided equations, passive components can be chosen to meet the desired percentage of the switching ripple.

When the MOSFET is open, see Figure 1, it sustains the output voltage, which is expressed by Equation (17) in the case of the base topology (Figure 1), and it is expressed by Equation (30) for the case of the generalized topology (Figure 4). The MOSFET must be then rated to the maximum output voltage plus a safety range, to ensure the voltage will not overpass the rated voltage. New silicon carbide devices are usually rated to a larger voltage compared to traditional silicon-based MOSFETS.

When the MOSFET is closed, it drains the summation of the current through both inductors, in the case of the base topology (Figure 1), and then, their RMS current can be calculated as Equation (50).

$$I_{S(RMS)}=\left(I_{L1}+I_{L2}\right)\sqrt{D}\sqrt{1+\frac{1}{3}{\left(\frac{\mathsf{\Delta }{i}_{L1}+\mathsf{\Delta }{i}_{L2}}{I_{L1}+I_{L1}}\right)}^2}$$

(50)

For the generalized topology, see Figure 4, the transistor current is the summation of the current through all inductors; in that case, their RMS current can be calculated as Equation (51).

$$I_{S(RMS)}=\left(I_{L1}+I_{L2}+\dots +I_{Lx}\right)\sqrt{D}\sqrt{1+\frac{1}{3}{\left(\frac{\mathsf{\Delta }{i}_{L1}+\mathsf{\Delta }{i}_{L2}+\dots +\mathsf{\Delta }{i}_{Lx}}{I_{L1}+I_{L1}+\dots +I_{Lx}}\right)}^2}$$

(51)

3. Experimental Results with the Fuel Cell Emulator

A dynamic model of a PEMFC (Proton-Exchange Membrane Fuel Cell) using a hardware-in-the-loop set-up was implemented to validate the implementation of the proposed converter under a realistic scenario, as is illustrated in Figure 7. The PEMFC model was programmed using LabVIEW, a data acquisition hardware, and a controlled DC source as an actuator. In particular, we measure the output current of the emulated PEMFC and define in a dynamic manner, the corresponding value of voltage according to the first principle model of the cell.

An algorithm based on the fuel cell equations was developed in the LabView environment and ran on a CompactRIO system, the idea is to measure the current drawn from the fuel cell and with that current to compute the voltage at terminals that a real cell would have. The CompactRIO controls the power supply in real-time, which is an independent system from the dc–dc converter, which has its own closed-loop control; the entire system is a hardware-in-the-loop real-time system.

The studied converter is feed by the programable DC source. This emulation is done in real-time using a National Instruments cRIO 9039 and a DC power source Keysight N6953A.

The realization of the fuel cell model is based on the Nernst reversible voltage equation based on four voltage components [28,29,30], i.e.,

$$V_{fc}=E_{Nernst}-V_{act}-V_{conc}-V_{ohm}$$

(52)

where E represents the Nernst voltage V_act is the activation loss, V_conc is the concentration loss, and V_ohm is the ohmic loss. Figure 8 shows the electrical model representation of the FC (Fuel Cell). The voltage at the output port varies according to the electric load. As mentioned before, three types of losses occur within the model; they are classified as activation, concentration, and ohmic losses.

3.1. Cell Reversible Voltage

The Nernst voltage or the reversible voltage corresponds to the potential at the output port of the FC with no-load. In [30] a modified version of the equation of this voltage drop is presented with a term that considers the temperature, P_O2 and P_H2 are the partial pressures of oxygen and hydrogen, respectively.

$$E_{Nernst}=1.229-0.85\times {10}^{-3}\left(T-298.15\right)+4.31\times {10}^{-5}T\left[\ln (P_{H2})+\frac{1}{2}\ln (P_{O2})\right]$$

(53)

3.2. Activation Voltage Drop

Activation voltage losses have a greater impact when low currents circulate through the cell [31].

$$V_{act}=-\left[{\xi }_1+{\xi }_{2}T+{\xi }_{3}T\ln C_{O2}+{\xi }_{4}T\ln (I_{FC})\right]$$

(54)

where I_FC is the fuel cell current demanded by the load and ξ’s are parameters for the fuel cell model, and their values are based on kinetic, thermodynamic, and electrochemical theoretical equations.

$$C_{O2}=\frac{P_{O2}}{5.08\times {10}^6{e}^{-498/T}}$$

(55)

3.3. Concentration Voltage Drop

Concentration or diffusion losses occur when there’s a change in the concentration of reactants; on the contrary of the activation losses, this has a greater impact at very high current, this can be seen in Equation (56).

$$V_{conc}=-B\ln \left(1-\frac{J}{J_{\max }}\right)$$

(56)

3.4. Ohmic Voltage Drop

The ohmic losses occur because of electrode resistance, current collectors, and polymeric membrane. They are proportional to the current that circulates in the fuel cell.

$$V_{ohm}=I_{FC}\left(R_M+R_C\right)$$

(57)

where RC is the transfer of protons resistance through the membrane with a value of 300 µΩ and R_M is the membrane resistance expressed with Equation (58).

$$R_M=\left(\frac{{\rho }_{M}l}{A}\right)$$

(58)

The polarization curve of the PEMFC is depicted in Figure 9, and the parameters of the Avista fuel cell stack 500 W are shown in

Table 1. Avista 500 W fuel cell stack parameters.

Param.	Value	Param.	Value
n	32	ξ1	−0.948
T	333 °K	ξ2	0.00286 + 0.0002lnA + (4.3 × 10−5) lnCH2
A	64 cm2	ξ3	7.6 × 10−5
l	178 µm	ξ4	−1.93 × 10−4
PH2	1 atm	ψ	23
PO2	0.2095 atm	Jmax	469 mA/cm2
B	0.016 V	Jn	3 mA/cm2
RC	0.0003 Ω	Imax	30 A

.

3.5. Important Voltage and Current Signals

In Figure 10, we show a picture of the experimental prototype, which can corroborate some of the features of the converter, e.g., its small compact design even though it exhibits a much higher (quadratic) voltage gain, with respect to traditional topologies.

A controller is implemented to regulate the output port voltage. The diagram of the controller is depicted in Figure 11, which encompasses an input-current control loop as well as an output–voltage loop. The control was designed by using the small signal linearization approach [13], despite equations obtained from the averaging technique being non-linear (for example see Equations (9)–(12)) the small signal approach allows us to design a stable converter for a certain operation region by following the technique in part II of [13].

This is a convenient control architecture considering that it only requires two sensors for the input current and the output voltage, even though it is a high-order controller with four dynamic equations. The parameters of the experiment are shown in

Table 2. Parameters of the experiment.

Parameter	Value/Information
Input voltage	36 V
Output voltage	250 V
Switching frequency	50 kHz
Inductor L1	Ferrite core pot 330 µH, 74 mΩ
Inductor L2	Ferrite core pot 820 µH, 154 mΩ
Capacitor C1	Film polypropylene 20 µF
Capacitor C2	Film polypropylene 20 µF
MOSFET	IPW65R037C6 650 V
Diode	BYV229400 on voltage 1.05 V
Load	BK precision electronic load 250 W
Controller gains k1, k2, g1, g2	100, 0.01, 10, 0.05

.

The control is designed in such a way that a stable output voltage is achieved indirectly by regulating the input current. The input-current control loop is implemented by a proportional and integral controller. This is because the quadratic converter has a non-minimum phase characteristic with respect to the output voltage, which is an instability condition for boost converters. The control loop is designed according to the consideration that a stable operation-point is achieved in steady-state, a linearization around this point was carried out, and the proportional and integral controllers were designed.

The transfer function of the converter can be expressed as Equation (59)

$$T{F}_{converter}=\frac{7.236s^4+3.568\times {10}^5{s}^3+7.785\times {10}^8{s}^2+2.008\times {10}^{13}s+1.653\times {10}^{16}}{s^4+400s^3+6.113\times {10}^7{s}^2+1.826\times {10}^{10}s+3.695\times {10}^{14}}$$

(59)

Figure 12 shows the bode plots of the converter both for both the open-loop and closed-loop operation.

In Figure 13, we include the comparison between the ideal polarization function of the FC and the experimental measurements that were performed to validate its behavior.

Some of the experimental measurements in terms of oscilloscope traces, as well as the dynamics of the FC emulator, are displayed in Figure 14, under continuous variations using a resistive load. In the case of Figure 14, the output voltage of the emulator (Vout) (not from the converter) which was built with the programable power source (see Figure 7) is changed un purpose, to perform the test, the closed-loop controller of the converter, adjust their duty cycle, requiring more current from the emulator (Iout) (which would be the input current of the converter), in order to maintain the output voltage, in which a resistive load is connected.

In Figure 15, we show the experiment result of the quadratic topology with stackable switching stages using a dc power source.

In order to show the effectiveness of the controller, we evaluated the dynamic response of the converter under continuous variations at the input-voltage. The results of this experiment are shown in Figure 16. It can be corroborated that the output voltage remains practically constant.

Finally, in Figure 17, we show the dynamic response of the converter in closed-loop when connected to the PEMFC emulator under continuous variations at the output load or the converter. Notice that the voltage remains constant, displaying a robust performance and providing a high-voltage gain, which makes it suitable for the proposed application.

A final test was performed in which an LC filter (L = 45 µH and capacitor C = 20 µF) was added between the fuel cell and the dc–dc converter, this to ensure the operation in the case a filter is required to smoot the current waveform, the test result was successfully, the voltage of the FC emulator was changed and the controller of the converter adjusts the current to successfully maintain their output voltage in a constant value, see Figure 18.

3.6. Efficiency and Cost Comparison

An efficiency comparison was performed, with parameters in Table 2, for both the traditional quadratic boost converter and the converter under study, which can be a so-called new quadratic boost converter, the result is shown in

Table 3. Efficiency (in percentage) for converters with parameters of Table 2.

Pout	25	50	75	100	125	150	175	200	225	250
Traditional QBC	94.87	94.73	94.52	94.28	94.04	93.80	93.55	93.31	93.06	92.82
New QBC	94.96	94.77	94.53	94.29	94.04	93.79	93.53	93.28	93.03	92.79

and Figure 19.

The internal operation of the converter has some differences. For example, in the new converter, when the switch is on, C₁ drains the current through L₂ when the switch is on, as well as in the traditional quadratic boost, but in this case, it also drains the output current at the same time. On the other hand, in the traditional converter, the output current is drained by C₂ all the time. When the switch is off, the current through C₁ in the proposed converter is I_L1 − I_out, while in the traditional case is I_L1 − I_L2, which is a smaller value.

Despite the differences in the internal operation, there is no significant change in the efficiency; furthermore, capacitors usually dissipate a small percentage of the converter losses, their equivalent series resistance ESR is in the order of milliohms. Due to the similarity of efficiencies (see Table 3 and Figure 19), we can conclude the size of the converter (due thermal design) is not affected.

The efficiency is not the main advantage of the converter since it is similar to the available technology. The advantages of the converter topology are the cost, and the size, a capacitor is larger and more expensive as the voltage rating increases (for the same capacitance). For example, C₁ sustains a voltage of 59 V in the example of Table 2, and C₂ sustains a voltage of 95 V, against the traditional quadratic boost converter in which C₁ sustains a voltage of 155 V in the same example, and C₂ sustains a voltage of 250 V.

The cost comparison is focused on the capacitor selection, as other components have the same voltage and current rating in both the new and the traditional quadratic boost converter,

Table 4. Kemet capacitor selection for converters.

		Kemet Part Number	Unit Cost	Max Voltage	Volume	ESR
New Converter	C1	R60ER51004040K	$3.94	100 V DC	4924 mm3	-
	C2	R75GR510050H0J	$4.97	160 V DC	26,118 mm3	4.8 mΩ
Traditional Converter	C1	C4ATDBW5100A30J	$5.85	250 V DC	19,008 mm3	3.1 mΩ
	C2	R75MW510050H3J	$7.91	400 V DC	43,923 mm3	4.8 mΩ

shows examples of capacitors of the same brand (Kemet) and type (film capacitors), which can be used to synthesize the converter, the information was obtained from Digi-Key, and the voltage rating was chosen for around 160% the voltage they need to sustain, which is a common practice for safety reasons, all capacitors are 10 µF, which is a common value (the capacitance of 20 µF can be obtained with two paralleled capacitors).

It can be observed from the selection, then for capacitors of the same type and capacitance, the increase of the voltage represents an increase on the cost and volume, the largest output capacitor of the traditional quadratic boost converter has to sustain 250 V, to achieve a safety overrating of 60%, we need to choose a 400 V capacitor, which volume and cost stand out others.

4. Conclusions

This article studies a boots type dc–dc converter with quadratic voltage gain and reduced number of active components (it uses only one transistor), is intended to be used with a fuel-cell based renewable energy generation system, the discussed converter is based on a stackable structure of several switching stages, their main characteristic is a relatively high voltage gain given in a quadratic type gain equation, a desirable feature for fuel cell generation systems. The major benefits of the quadratic converter are: (1) the output voltage is provided by all capacitors connected in additive series, in contrast with other circuits that have several capacitors, including a large capacitor that sustains the (relatively large) voltage at the output port; (2) the system operation and the major benefits of the proposed system are corroborated with experimental results; a fuel cell emulator was built and used for the experimental results.