Switched Capacitor Compensation of Supply Distortion in Class-D Amplifiers

Abstract

This paper presents a switched capacitor technique for bus-pumping compensation in a half-bridge class-D amplifier. The proposed approach, in addition to the almost complete reduction of the bus-pumping effect, allows the half-bridge class-D amplifier to preserve maximum energy efficiency. The studied hardware implementation of the proposed technique demonstrates its advantages of high efficiency, simple circuit, and low cost. The principal design and operating principles are analyzed and described. The experimental static characteristics and time-domain waveforms for the proposed technique are shown to verify its feasibility.

1. Introduction

A class-D output stage in half-bridge (HB) configuration is one of the most used output stages in general-purpose power conversion, especially when the load is in single-ended form. Apart to audio amplifiers [1,2,3,4,5,6,7], it can be found in many other applications, including power electronic converters [7,8,9,10,11], power amplifier in grid testing equipment [12,13], as a compensation amplifier in feedback systems [14,15,16,17], etc. As a power amplifier, class-D HB is a simple, portable, and space and energy-efficient replacement for a linear class-AB amplifier.

As a configuration, class-D HB has long been matured. In the case of audio amplifiers, all important issues are investigated, and many solutions are proposed. However, for the case of applications in other engineering fields, some problems are still worthy of attention.

One of the problems in HB is known as a bus-pumping (BP) effect [1,7,8,15], which, in audio applications, increases distortion and noise and degrades the sound quality. It arises when the HB stage is supplied with a unilateral power source and when the amount of BP disturbance generated at power supply busses is equal to [1]:

$$\mathsf{\Delta }{V}_{BB}=V_{BB}/(8\pi \cdot f_a\cdot C_a\cdot R_a).$$

(1)

In Equation (1), V_BB is power supply voltage, R_a is load resistance, C_a is power supply blocking capacitance, and f_a is the frequency of an audio signal.

An alternative to HB output stage is a full-bridge (FB) output stage, which is structurally immune to BP effect. However, for a class-D amplifier supplied by front-end switching power supply, HB is still more used, due to simple circuit architecture, especially for multi-channel amplification [9,10,12,13,18,19]. Additionally, FB is limited to applications in which the load can be differentially driven [1,16].

The most commonly used solutions to this issue are not to eliminate the cause of the problem but to treat the consequences. This kind of solutions perform active techniques, based on feedback and feed-forward compensation, thus achieving noticeable results in the elimination of acoustic noise [5,20,21,22,23]. In power electronics applications, as well as in some high power audio applications, hardware methods that directly reduce BP are applied [7,8,24,25,26].

In some sensor applications, where HB class-D is used as a compensation amplifier, quantities f_a, or R_a approaches to zero [14,15,17]. As a consequence, voltage disturbance on power supplies can be large enough to disable regular operation of the system, or even to damage power stage and other related electronics. Since f_a can be zero, blocking capacitors of any reasonable size are ineffective. Existing hardware solutions are applicable, but they are too complex for portable sensor devices where simplicity and cost efficiency are required.

This paper treats the possibilities of eliminating BP primarily on DC, as well as at low frequencies where the efficiency of blocking capacitors is insufficient. A dissipative solution of BP compensation is analyzed in details as a foundation for non-dissipative switched-capacitor (SC) bus-pumping suppression solution. Based on that analysis, an SC circuit was designed for which it was experimentally determined to possess ability to greatly reduce BP and to preserve energy efficiency of ideal HB class-D amplifier.

2. Power Efficiency of an Ideal Class-D HB Amplifier and the Root of the BP Problem

For the case of AC operation, various analysis of the BP effect can be found in literature. However, it is difficult to find analysis of the DC transfer dependence of supply currents against PWM duty ratio (D). Therefore, simplified derivation of this dependence is performed, which serves as a foundation for rest of discussion.

For that purpose a HB output stage from Figure 1 is considered. DC power supply PS is ideal (bilateral) with output currents i_SS and i_DD. Gate drive logic is managed with clock CLK of switching period T. It controls ideal MOS switches, turning on M₁ for D∙T seconds during first part of the switching period, and turning on M₂ for (1−D)T seconds during second part of the switching period, where D is PWM duty ratio. Output stage load is represented as a serial connection of large inductance L and small serial resistance R. For simplicity, it is assumed that the time constant of the load τ = L/R is sufficiently large; therefore, i_l(t) → 0 and i_L(t) ≈ I_L. As a function on D, load current I_L is equal to:

$$I_L=I_{D2}-I_{D1}=((1-D)V_{SS}-D{V}_{DD})/R.$$

(2)

By inverting Equation (2), duty factor D can be evaluated as:

$$D=(V_{SS}-R{I}_L)/(V_{SS}+V_{DD}).$$

(3)

For D = 1 or D = 0, load current reaches maximal possible amplitude:

$$I_{LM}=V_S/R.$$

(4)

Using Equation (4), Equations (2) and (3) can be written in more suitable form:

$$D=0.5-R{I}_L/(2V_S)=0.5-I_L/(2I_{LM}),$$

(5)

and

$$I_L=I_{LM}(1-2D).$$

(6)

Using Equation (5) and Equation (6), currents I_D1, I_D2 and their sum can be represented as:

$$\begin{array}{l}{I}_{D1}=-D{I}_L=-I_{LM}D(1-2D);\\ I_{D2}=(1-D)I_L=I_{LM}(1-D)(1-2D)\\ I_{D1}+I_{D2}=I_{LM}{(1-2D)}^2\end{array}.$$

(7)

Normalized values I_D1/I_LM and I_D2/I_LM, in respect to D, are displayed in Figure 2. It can be seen that current I_D1 reaches minimum of −I_LM/8 for D = 1/4, whereas current I_D2 reaches the same minimum for D = 3/4.

Since I_DD = I_D1 and I_SS = I_D2, precisely one of the supply currents (I_DD or I_SS) is negative regardless of D. That means that part of the energy, deposited in L during the first part of a switching period, is recuperated during rest of the period. Using Equations (4), (5), and (7), total power consumption P_tot, as a function of D is in a form:

$$\begin{array}{l}{P}_{tot}=V_{DD}\cdot I_{DD}+V_{SS}\cdot I_{SS}=V_S(I_{D1}+I_{D2})=\\ V_S{I}_{LM}{(1-2D)}^2=R{I}_{LM}^2{(1-2D)}^2=R{I}_L^2.\end{array}$$

(8)

According to Equation (8), the total power delivered by the supply is dissipated only on the load resistance R, so the class-D amplifiers’ theoretical power efficiency is optimal.

As a comparison, power consumption of an ideal class-AB power amplifier, with the same supply, and fictive parameter D, is equal to:

$$P_{lin}=\left|V_S{I}_L\right|=R{I}_{LM}^2\left|1-2D\right|.$$

(9)

Normalized power consumption as a function of D for previous two cases is depicted in Figure 3.

In typical applications, the power supply is usually unidirectional, which can be modeled with ideal diodes D₁ and D₂, Figure 4. Consequently, currents I_DD and I_SS cannot be negative. For example, if I_D1 is negative, then I_DD is zero, and blocking capacitor C₁ has been charging much over V_S, causing BP effect on V_DD bus [15]. A similar effect occurs for negative I_D2. Therefore, some countermeasures should be taken in order to prevent such behavior.

If the negative current I_DD (or I_SS) is entirely dissipated [15], then BP is fully stopped. In that case, only positive current I_SS (or I_DD) contribute to power consumption, which is described as:

$$P_h=\{\begin{array}{c}{V}_S{I}_{D2}=R{I}_{LM}^2(1-D)(1-2D),\hspace{1em}D<0.5\\ V_S{I}_{D1}=-R_0{I}_{LM}^{2}D(1-2D),\hspace{1em}D>0.5\end{array}.$$

(10)

Normalized power consumption P_h is depicted in Figure 3. Power consumption for the case (c), Equation (10), is positioned approximately in the middle between ideal case (a) and the power efficiency of class-AB amplifier, case (b).

3. Analysis of a Passive BP Suppression and Impact on Power Consumption

Principal schematic of class-D HB amplifier without control circuitry, powered with unidirectional power supply, and augmented with bus-pumping suppression circuitry, is presented in Figure 4.

Apart to dissipation on R, there is, in reality, an additional dissipation caused by power demands of used electronic components. This dissipation, modeled as current sources I₀ in Figure 4, is usually small and negligibly affects the compensation of negative I_D1 or I_D2 [15,16].

With the help of additional passive circuit, modeled by r₀ and V_DZ, it is possible to significantly absorb negative I_D1 or I_D2 and perform partial or full compensation of the BP effect. For the simplicity, combination of I₀, r₀ and V_DZ, inside subcircuits U₁ and U₂, can be replaced by a serial connection of r₀ and voltage source V₀, Figure 5:

Without loss of generality, from now on, analysis is limited to D < 0.5. For D > 0.5, conclusions are equivalent due to symmetry.

Let us assume that size of r₀ is sufficient so that V₀ + r₀∙I₀₁ is greater than V_S for some values of D. Then, the V_DD portion of the power supply is blocked, I_DD = 0, and I₀₁ = −I_D1. The voltage on V_DD bus is:

$$V_{DD}=\max \{V_S,V_0-I_{D1}{r}_0\},$$

(11)

while the voltage on −V_SS bus is equal to −V_SS = −V_S. According to Equation (2), current I_L is equal to

$$I_L=((1-D)V_0-D{V}_{DD})/R,$$

(12)

and, for the case of V_DD > V_S, it is satisfied that:

$$V_{DD}=V_0+D{I}_L{r}_0=V_0+r_{0}D\frac{(1-D)V_S-D{V}_{DD}}{R}.$$

(13)

That means:

$$V_{DD}=\frac{R{V}_0+r_{0}D(1-D)V_S}{R+r_0{D}^2}.$$

(14)

For complete interval 0 < D < 0.5, V_DD portion of power supply is equal to:

$$\begin{array}{l}{V}_{DD}=\max \left\{V_S,\frac{R{V}_0+r_{0}D(1-D)V_S}{R+r_0{D}^2}\right\}=\max \left\{V_S,V_S\frac{V_0/V_S+(r_0/R)D(1-D)}{1+(r_0/R)D^2}\right\}=\\ =\max \left\{V_S,V_S\frac{\alpha +\beta \cdot D(1-D)}{1+\beta \cdot D^2}\right\}=\max \left\{V_S,V_S\cdot g(\alpha ,\beta ,D)\right\},\end{array}$$

(15)

where $\alpha =V_0/V_S,\mathrm{and}\beta =r_0/R,\mathrm{and}g(\alpha ,\beta ,D)=\left(\alpha +\beta \cdot D(1-D)\right)/\left(1+\beta \cdot D^2\right).$

Since D(1−D) > D² for 0 < D < 0.5, if α > 1, then g(α, β, D) is always greater than 1. Therefore, in order to prevent BP, a necessary condition is that V₀ < V_S. Due to symmetry, the conclusion is also valid for U₂.

3.1. Maximal Efficiency–Ideal Dissipative Method

A theoretically “ideal” case arises when r₀ → 0, and α = 1 + ε, ε → 0. Then, I_DD = 0 for all values of D in the range 0 < D < 0.5. Only −V_SS portion of power supply delivers energy to the load, which corresponds to Equation (10), and dependence marked as case (c) in Figure 3. In reality, both V_DZ and V_S can be decently stable. But, V_S can be intentionally variable, and V_DZ is not precise in a simple implementation. So, if it happened that V_S > V_DZ, then excessive dissipation would occur.

For that reason, simple passive realizations, for example, Zener diode for V_DZ, are hardly usable. For performance described by Equation (10), active clamp circuit can be applied, which performs active tracking between V_S and V_DZ [15].

3.2. Maximal Simplicity

For a low cost, low supply, or space critical designs, an active clamp circuit proposed in Reference [15] can be inappropriate. Furthermore, due to the negative feedback configuration, in some circumstances, it can face stability issues. Thus, with some lower performance regarding power efficiency, and proper selection of component parameters, the passive alternative from Figure 5 may be used.

For some combinations of β and α < 1, and some values of D < 0.5, it is satisfied that

$$g(\alpha ,\beta ,D)=\frac{\alpha +\beta \cdot D(1-D)}{1+\beta \cdot D^2}<1.$$

(16)

Therefore, I_DD = I_D1+I₀₁, and, consequently, I_SS = I_D2 + I₀₂. For that case, total power consumption is greater than consumption derived in Equation (10), and, according to Equations (3)–(7), it is equal to:

$$\begin{array}{l}{P}_{tot}=V_S(I_{D1}+I_{01}+I_{D2}+I_{02})=V_S(-D{I}_L+(1-D)I_L+I_{01}+I_{02})=\\ =R{I}_{LM}^2{(1-2D)}^2+V_S(I_{01}+I_{02})=R{I}_{LM}^2{(1-2D)}^2+2(V_S-V_0)/r_0.\end{array}$$

(17)

Parameters α < 1, and β can be selected for complete suppression of BP effect. In that case, Equation (16) should be satisfied for all values of D, including extreme condition, i.e., for D = 1/4:

$$\frac{\alpha +3\beta /16}{1+\beta /16}\le 1\Rightarrow \beta \le 8(1-\alpha ).$$

(18)

Minimal consumption is achieved for the equality sign in the previous equation. Then, using V₀ = αV_S, and r₀ = 8(1 − α)R and Equation (17), total power consumption in respect to D is equal:

$$\begin{array}{l}{P}_{tot1}=R{I}_{LM}^2{(1-2D)}^2+2(V_S-V_0)/r_0=R{I}_{LM}^2{(1-2D)}^2+2V_S\frac{V_S-\alpha V_S}{8\left(1-\alpha \right)R}=\\ =R{I}_{LM}^2{(1-2D)}^2+R{I}_{LM}^2/4.\end{array}$$

(19)

Since ${(1-2D)}^2+1/4>\left|1-2D\right|$ for any value of D, P_tot1 in Equation (19) is worse than P_lin in Equation (9), as in Figure 3. Therefore, regarding power efficiency, the simple passive realization that guarantees BP-free operation is worse than a class-AB case; see Figure 3.

On the other hand, if some BP is allowed, power consumption can be positioned between P_lin and P_h:

$$P_{tot2}=\max \left\{V_S{I}_{D2},P_{tot1}\right\}.$$

(20)

For example, if it is allowed that V_DD and V_SS could race up to 1.1V_S, then, for α = 0.53 and β = 5, expression g(0.53, 5, D) is greater than 1 in a range of $1/8<D<3/8.$ In that range, I_DD = 0, only −V_SS portion of power supply delivers energy to the load, and power dissipation complies expression from Equation (10). For $D<1/8\mathrm{or}D>3/8,$ current I_DD > 0, and power dissipation complies expression from Equation (17). Graphical representation of P_tot2 for the whole range of D is depicted in Figure 3.

If the application requirements are such that factor D is limited to a narrower range, i.e., $0<D_{LO}<D<D_{HI}<1$, and if a particular deviation of V_DD from V_S is tolerated, i.e., a small overshoot is allowed, then such a realization is quite competitive to active clamp solution proposed in Reference [15].

However, regarding power efficiency, passive suppression of BP effect cannot provide the full potential of HB topology.

4. SC Compensation of BP Effect

SC techniques have long been routinely migrated from mixed-signal processing to power converter electronics [27,28,29,30,31,32]. With a simple rearrangement of switches, or by manipulation of frequency and phase of clock signals, SC counterparts of continuous circuits can easily acquire new features that are difficult to achieve in the continuous domain. One of the features is a flexible energy transfer from one part of the circuit to another, which is regularly used in power electronics designs [29,30,31,32].

Let us consider circuit from Figure 6, with a BP SC suppression subcircuit. The analysis is performed for 0 < D < 0.5, while the conclusions for 0.5 < D < 1 are symmetric and can be deduced from analogy. The SC subcircuit consists of capacitor C₃ << C₁, C₂, MOS switches P₁, P₂, P₃, and P₄, and gate-drive logic (not shown on the picture). The gate-drive logic of P₁, P₂, P₃, and P₄ is clocked with a two-phase clock scheme CLK₁ with nonoverlapping phases having duty factor of 0.5. The CLK₁ with frequency f₁ = 1/T₁ is physically distinct to CLK. Clock phase φ₁, which is active during the first half of switching period T₁, turns on P₁ and P₂, while P₃ and P₄ are in the blocked state. During the second part of the switching period, clock phase φ₂ is active, and it turns on P₃ and P₄, while P₁ and P₂ are in a blocked state. Therefore, during the first half of the period T₁, capacitor C₃ is connected in parallel with capacitor C₁, while, during the rest of the period, it is connected in parallel with C₂.

4.1. Power Efficiency Analysis

For values of D, which makes V_DD greater than V_S, a simplified version of the circuit, from Figure 6, is presented in Figure 7a,b. The current i_DD is equal to zero, the V_DD portion of the power supply is blocked, and, therefore, it is not shown. On the other hand, i_SS > 0, maintaining negative supply active, and −V_SS = −V_S. Since capacitor C₂ is at constant voltage V_S, then i_c2 = 0. Thus, C₂ does not affect circuit operation, so it is not included in Figure 7.

Figure 7a describes the active part of the BP suppression SC circuit during the first half of the switching period T₁. Switches P₁ and P₂, are closed, and C₃ is connected in parallel with C₁. C₁ is large enough so that voltage V_DD can be considered constant over several periods of T₁. Since C₃ << C₁, capacitor C₃ is charged to voltage V_DD.

Figure 7b describes the active part of the BP suppression SC circuit during the second half of the switching period T₁. Switches P₃ and P₄ are closed; capacitor C₃ is connected to PS and charged to voltage V_S.

Voltage change ΔV_C3 (1) on capacitor C₃, at the beginning of first half of the period T₁, is equal to $\mathsf{\Delta }{V}_{C3}(1)=V_{DD}-V_S,$ thus having the charge flowing through C₃ equal to $\mathsf{\Delta }Q(1)=\mathsf{\Delta }{V}_{C3}(1)\cdot C_3.$ Consequently, the average value of current i_B1 during single switching period T₁ is equal to

$$I_{B1}=\mathsf{\Delta }Q(1)/T_1=C_3(V_{DD}-V_S)/T_1.$$

(21)

Voltage change ΔV_C3 (2) on capacitor C₃, at the beginning of second half of the period T_1, is equal to $\mathsf{\Delta }{V}_{C3}(2)=V_S-V_{DD}=-\mathsf{\Delta }{V}_{C3}(1).$ Therefore, the charge flowing through C₃ is equal to $\mathsf{\Delta }Q(2)=-\mathsf{\Delta }Q(1),$ and the average value of current i_B2 during single switching period T₁ is equal to −I_B1. According to Figure 7a, it is fulfilled that −I_B1 = I_D1, from which it follows that I_B2 = I_D1. Since I_SS = I_B2 + I_D2, it follows that I_SS = I_D1 + I_D2, and total power consumption is equal to P_tot = V_S(I_D1 + I_D2). The obtained result confirms that P_tot is the same as in the ideal case and that applied SC circuit provides maximum consumption efficiency of the class-D amplifier.

4.2. BP Analysis

Based on Figure 7 and Equation (21), it can be seen that the SC circuit behaves as the circuit from Figure 5, where V_DD bus is connected via SC equivalent resistor r₀ = T₁/C₃ to the generator V_DZ = V_S and that I_B1 ⇔ I₀₁

$$I_{B1}=\frac{V_{DD}-V_S}{T_1/C_3}=\frac{V_{DD}-V_S}{r_0}=I_{01}.$$

(22)

Therefore, for BP analysis, circuits from Figure 4 and Figure 5, together with corresponding Equations, can be used.

If we neglect I₀, then V₀ = V_DZ = V_S, α =1, and BP effect occurs for full range 0 <D < 0.5:

$$V_{DD}=V_S\frac{1+\beta \cdot D(1-D)}{1+\beta \cdot D^2}>V_S.$$

(23)

Contrary to dissipative BP suppression, SC equivalent resistor r₀ can be arbitrarily small. Therefore, BP effect can be made negligible. For example, if β = 0.5, maximum voltage on V_DD bus is achieved approximately at D = 1/4 and is equal to:

$$V_{DD}=V_S\frac{1+0.5\cdot 3/16}{1+0.5\cdot 1/16}=1.06V_S.$$

(24)

In practical realizations, there is always a small current I₀, which causes the current I_DD to be greater than zero during a small part of the period T. Still, this fact does not change the essence of the conducted analysis.

4.3. Dynamical Behavior

Due to the existence of the zero-order hold effect, SC circuits are well equivalent to their continual counterparts up to ≈1/10 of the sampling frequency [27,28]. From that side, proposed SC compensation of BP effect is useful to at least 1/10 of f₁ = 1/T₁. With the current state of technology, sampling frequencies can routinely go over 50 kHz, so that blocking capacitors solve the BP problem easily at f₁/10. As an illustration, we may consider the following “worst-case” example. Let us assume that the sampling frequency of the SC BP suppression circuit is f₁ = 10 kHz. Thus, we can pessimistically consider that over f₁/10 = 1 kHz SC circuit is ineffective regarding BP suppression. Furthermore, let us assume that class-D amplifier has the following parameters: R_a =1 Ω, and C_a = 4.7 mF. At f₁/10 = f_a = 1 KHz, according to Equation (1), ΔV_BB/V_BB = 1/(4.7∙8π) = 0.0085, which is below 1%. Therefore, if usual switching frequencies are used, modeling performed in the paper is sufficient for accurate prediction of the dynamical behavior of the proposed SC BP suppression method.

When frequencies below f₁/10 are observed, the transient behavior of the voltages v_DD and v_SS is defined by the time constants τ_DD = r₀ ∙ C₁ and τ_SS = r₀ ∙ C₂. For the case of positive supply bus, when diode D₁ is blocked, and R_B is disconnected, as in Figure 6, Unit-step response of the voltage v_DD is in the form

$$S_{DD}(t)=1\left[\mathrm{A}\right]\cdot r_0(1-e^{-t/{\tau }_{DD}})\cdot \mathrm{u}(t),$$

(25)

where u(t) is Unit-step function, and assumed excitation is current i_D1. The same equation is valid for a negative supply bus. It can be seen that the worst case is on DC and that the purpose of the dynamic behavior analysis can only be to optimize the values of the blocking capacitors C₁ and C₂.

4.4. Experimental Verification

Previous derivations regarding power consumption and suppression of BP effect are verified using experimental setup based on Figure 6. Power source PS is configured as ±12 V desktop power supply modified with diodes D₁ and D₂ (MUR1045), which gives final output voltage as ±V_S ≈ ±11.5 V at 0.5 A load and load regulation of 0.6 V/A. When needed, the bilateral power supply is simulated by adding a blinder resistor R_B = 215 Ω between nodes A and B, as in Figure 6, so that currents I_DD and I_SS could flow in both directions. The current through R_B has a negligible effect on the load regulation; it does not affect I_DD or I_SS and is not covered by the measurements. Measured electrical quantities are I_DD, I_SS, V_DD, V_SS, and I_L in a range of 0.05 < D < 0.95. For each pair of MOS transistors, and an accompanying gate driving logic, one-half of each of the three different L6202 is used. Capacitors C₁ and C₂ have values of 1000 μF. Quiescent supply current for D = 0.5 is I₀ ≈ 20 mA, giving power consumption at rest as

$$P_0=2V_S\cdot I_0=460\mathrm{mW}.$$

(26)

Used load is made of coil with L = 50 mH, r_L = 5.3 Ω, and resistor R_L = 10 Ω, which gives R = R_L + r_L = 15.3 Ω. Switching periods are T₁ = T = 100 μs. For a set of different C₃ values, the calculated characteristic quantities, used in paper equations, are given in

Table 1. Characteristic quantities r₀, V₀, α, β, and extreme values for V_DD and V_SS.

C3 [μF]	r0 = T1/C3 [Ω]	V0 = VS − I0∙r0 [V]	α	β	Max{VDD} at D = 1/4, Equation (15) Max{VSS} at D = 3/4 [V]	Time Constant C1∙r0 [ms]
2.07	48.3	10.53	0.916	3.157	14.48	τ1 = 48.3
5.16	19.4	11.11	0.966	1.267	12.83	τ2 = 19.4
10.3	9.7	11.31	0.983	0.635	12.19	τ3 = 9.7
24.3	4.1	11.42	0.993	0.269	11.80	τ4 = 4.1

. V_DD supply bus voltage is calculated for D = 1/4, which is near the extreme value for both V_DD and V_SS.

Measured supply voltages V_DD and V_SS for the selected set of C₃ values, as well as calculated supply voltages based on Table 1, are given in Figure 8. Measured voltages are presented as line charts, whereas calculated voltages are presented as symbol + line charts. The picture shows a good agreement between experiment and theory.

Measured supply currents I_DD and I_SS against D, are presented in Figure 9. For cases (b) and (c), supply currents are greater than or equal to zero for a complete range of D, whereas sum I_DD + I_SS is the same for all 3 cases, which corroborates theoretical predictions.

Power consumption, for several measured or theoretically calculated cases, is presented in Figure 10. For cases (b) and (c), power supply is unidirectional, and the SC circuit is fully active. For the case (a) in which power supply is bilateral, capacitor C₃ is removed (C₃ = 0) so that SC circuit contributes to quiescent consumption, but it does not engage in BP suppression.

When power consumption is measured, for cases (a), (b), and (c), it is done indirectly as

$$P_{tot}=V_{DD}\cdot I_{DD}+V_{SS}\cdot I_{SS}.$$

(27)

For the case (d) and (e), power consumption is calculated on the basis of Equation (8) and Equation (10), augmented with quiescent consumption P₀:

$$P_{tot}=P_o+R{I}_{LM}^2{(1-2D)}^2,$$

(28)

for bilateral power supply, and

$$P_{tot}=\{\begin{array}{c}{P}_0+R{I}_{LM}^2(1-D)(1-2D),D<0.5\\ P_0+-R_0{I}_{LM}^{2}D(1-2D),D>0.5\end{array},$$

(29)

for unilateral power supply.

It can be observed that the use of proposed SC circuit preserves energy efficiency, as in the case of ideal power supply.

The waveforms for illustrating dynamic behavior of the positive and negative supply voltages when the duty factor alternately changes from 0.5 to 0.25, and vice versa, with intervals of 50 ms, are shown in Figure 11. Responses are captured in a following way: for the case of bilateral supply, case (a); for the case of unilateral power supply and two different values of capacitor C₃, cases (b), (c). Voltage v_L, a seen in Figure 6, is displayed on channel CH 1, voltage +v_DD is displayed on channels CH 5–CH 7, and voltage −v_SS is displayed on channels CH 2–CH 4.

For the case (a), there is no bus-pumping, and power supply voltages +v_DD and −v_SS suffer from voltage drops caused by load regulation. Transient response of supply voltages follows the transient response of the load, with time constant τ_L = L/R = 3.3 ms.

For the cases (b) and (c), only positive portion of the power supply is blocked during time periods when D = 0.25, and +v_DD bus experiences BP. Transient response of +v_DD is slowed down due to time constants τ₃ and τ₄, Table 1. On the other hand, the negative portion of the power supply is active, and transient response of the voltage −v_SS follows transient response of the load, according to time constant τ_L.

5. Conclusions

For the case of standard unilateral power supplies, described dissipative methods for BP suppression in class-D amplifiers can be extremely simple and cost-effective. Still, they cannot provide the full potential of HB topology regarding power efficiency. As an alternative, a high-efficiency SC technique for BP reduction in HB class-D amplifiers is proposed in this paper. It is shown that the proposed SC technique can reduce BP significantly and preserve energy efficiency of ideal HB class-D amplifier, with advantages of high efficiency, simple implementation possibility, and low cost. Analytical results are given to verify the operation principles. Hardware implementation of the proposed technique and its operation considerations were analyzed and described. A laboratory prototype was implemented and tested to show its performance, regarding BP suppression, power efficiency, and dynamical characteristics.