# An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT

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## Abstract

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## 1. Introduction

- New overall implementation architecture is proposed, which includes the embedded CPU, AHB-SIC, the SM3 circuit module and other modules. The AHB-SIC is designed to easily convert SM3 modules with the non-standard interface into the standard AHB slave interface. The SM3 circuit module is implemented by the software/hardware co-design method to enhance flexibility and reduce the hardware resource.
- Task scheduling and hardware resource optimization methods are applied in the expansion process to reduce the hardware area and power consumption so as to improve overall performance of SM3 implementation. The task scheduling and critical path optimization techniques are also applied in compression module design to reduce time delay and improve efficiency. The identical controller is shared in both expansion and compression modules to simplify the control circuit and reduce the hardware overheads.
- The proposed architecture is implemented on FPGA and ASIC, and also applied to an intelligent gateway. Combined with the other cryptographic modules, our proposed SM3 module can realize the digital signature and identity authentication to protect the security of user data. This framework can also be integrated into other IoT devices.

## 2. SM3 Background

#### 2.1. Padding and Parsing

#### 2.2. Expansion

- Divide the message ${B}^{\left(i\right)}$ into 16 words ${W}_{0},{W}_{1},\dots ,{W}_{15}$. The size of each word is 32-bit.
- FOR $i=16$ to 67$${W}_{i}={P}_{1}({W}_{i-16}\oplus {W}_{i-9}\oplus ({W}_{i-3}\u22d815))\oplus ({W}_{i-13}\u22d87)\oplus {W}_{i-6}$$ENDFORIn the Equation (1), ⊕ and ⋘ represent the bitwise XOR and ROL operations, respectively; ${P}_{1}\left(X\right)=X\oplus (X\u22d815)\oplus (X\u22d823)$ is the permutation function.
- FOR $i=0$ to 63$$W{{}^{\prime}}_{i}={W}_{i}\oplus {W}_{i+4}$$ENDFOR

#### 2.3. Compression

## 3. Proposed Architecture

#### 3.1. Overall Implementation Architecture

#### 3.2. The AHB-SM3 Interface Controller

#### 3.3. SM3 Implementation

#### 3.3.1. Software/Hardware Co-Design

#### 3.3.2. Controller Design

#### 3.3.3. Expansion Module Design

#### 3.3.4. Compression Module Design

## 4. Analysis and the Experiment Result

#### 4.1. The Setting and Implementation of the Experiment

#### 4.2. Time and Resource Consumption Analysis

#### 4.3. Computation Amount Analysis

#### 4.4. Comparison with Pure Software

#### 4.5. Comparison with Other Related Work

## 5. An Example of IoT Application of SM3

## 6. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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Algorithms | SHA-224 | SHA-256 | SHA-384 | SHA-512 | SHA3-224 | SHA3-256 | SHA3-384 | SHA3-512 | SM3 |
---|---|---|---|---|---|---|---|---|---|

Message size | <${2}^{64}$ | <${2}^{64}$ | <${2}^{128}$ | <${2}^{128}$ | − | − | − | − | <${2}^{64}$ |

Block size | 512 | 512 | 1024 | 1024 | 1152 | 1088 | 832 | 576 | 512 |

Digest size | 224 | 256 | 384 | 512 | 224 | 256 | 384 | 512 | 256 |

Security | 112 | 128 | 192 | 256 | 112 | 128 | 192 | 256 | 128 |

Value Range | ${\mathit{T}}_{\mathit{j}}$ | ${\mathit{FF}}_{\mathit{j}}$ | ${\mathit{GG}}_{\mathit{j}}$ |
---|---|---|---|

$0\u2a7dj\u2a7d15$ | $79cc4519$ | $X\oplus Y\oplus Z$ | $X\oplus Y\oplus Z$ |

$16\u2a7dj\u2a7d63$ | $7a879d8a$ | $(X\wedge Y)\vee (X\wedge Z)\vee (Y\wedge Z)$ | $(X\wedge Y)\vee (\neg X\wedge Z)$ |

Operation | Clock Cycles | Register | Additions of the Critical Path | Slack |
---|---|---|---|---|

Non-optimized | 196 | 148 | 5 | 0.0 |

Optimized | 70 | 36 | 4 | 1.31 |

Operation | LOAD | STORE | XOR | LOAD | ADD | AND | OR | NOT | Total |
---|---|---|---|---|---|---|---|---|---|

Non-optimized | 596 | 900 | 632 | 720 | 512 | 240 | 144 | 48 | 3792 |

Optimized | 400 | 192 | 632 | 528 | 512 | 240 | 144 | 48 | 2696 |

Design | Platforms | Frequency (MHz) | Clock Cycles | Areas (Gates) | Power (mW) | Throughput (Mbps) |
---|---|---|---|---|---|---|

This work | 0.13-$\mathsf{\mu}$m | 36 | 70 | 6036 | 1.24 | 263 |

SHA-3 [30] | 0.04-$\mathsf{\mu}$m | 28.8 | 3329 | 886 | 4.87 | 14 |

SM3 [20] | 0.18-$\mathsf{\mu}$m | 200 | 1 | 8800k | - | 105k |

SM3 [24] | 0.065-$\mathsf{\mu}$m | 526.3 | 80 | 5370 | - | 3368 |

SM3 [12] | 0.13-$\mathsf{\mu}$m | 250 | 464 | 8277 | - | 276 |

0.13-$\mathsf{\mu}$m | 200 | 68 | 12,956 | - | 1506 | |

SM3 [31] | 0.13-$\mathsf{\mu}$m | 216 | 68 | 9458 | - | 1619 |

SHA-256 [32] | 0.13-$\mathsf{\mu}$m | 102 | 1120 | 9036 | 3.06 | 47 |

Design | Platforms | Frequency (MHz) | Clock Cycles | Areas | Throughput (Mbps) |
---|---|---|---|---|---|

This work | Virtex-7 | 36 | 70 | 808 Slices | 263 |

Virtex-7 | 50 | 70 | 808 Slices | 366 | |

Virtex-7 | 100 | 70 | 808 Slices | 731 | |

SHA-256 [33] | Cyclone II | 116.24 | 68 | 7219 Logic Cells | 875.22 |

Cyclone II | 87.08 | 68 | 10,918 Logic Cells | 655.66 | |

SM3 [25] | ZYNQ-7020 | 167.8 | 64 | 1743 Slices | 1342 |

Standard-SM3 | Virtex-5 | 214 | 7.53 | 384 Slices | 1611 |

C-SM3 | Virtex-5 | 215 | 7.53 | 234 Slices | 1619 |

T-SM3 [31] | Virtex-5 | 362 | 7.53 | 328 Slices | 2726 |

SHA-3 [34] | Virtex-5 | 372 | 846 | 56 Slices + 2 BRAM | 225 |

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**MDPI and ACS Style**

Zheng, X.; Hu, X.; Zhang, J.; Yang, J.; Cai, S.; Xiong, X.
An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT. *Electronics* **2019**, *8*, 1033.
https://doi.org/10.3390/electronics8091033

**AMA Style**

Zheng X, Hu X, Zhang J, Yang J, Cai S, Xiong X.
An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT. *Electronics*. 2019; 8(9):1033.
https://doi.org/10.3390/electronics8091033

**Chicago/Turabian Style**

Zheng, Xin, Xianghong Hu, Jinglong Zhang, Jian Yang, Shuting Cai, and Xiaoming Xiong.
2019. "An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT" *Electronics* 8, no. 9: 1033.
https://doi.org/10.3390/electronics8091033