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Article

A Sliding Mode Controller with Signal Transmission Delay Compensation for the Parallel DC/DC Converter’s Network Control System

1
Yatai Construction Science & Technology Consulting Institute Co., Ltd., Beijing 100120, China
2
School of Electrical Engineering and Automation, Harbin Institute of Technology, Harbin 150001, China
*
Author to whom correspondence should be addressed.
Electronics 2024, 13(1), 121; https://doi.org/10.3390/electronics13010121
Submission received: 9 October 2023 / Revised: 5 December 2023 / Accepted: 15 December 2023 / Published: 28 December 2023

Abstract

:
The network control system (NCS) of the parallel DC/DC converter is always affected by the signal transmission delay, and the ideal output performance is lost. In this paper, a typical parallel buck converter is taken as the research object. Firstly, a sliding mode controller (SMC) in the discrete domain is designed to enhance the robustness of the system. On this basis, the effects of different delays on the stability of the converter’s NCS are analyzed, and the actual effects of long/short delays on the converter’s NCS are obtained. To further solve the problem of damage to transmitted signals of the NCS by long delay, the SM controller designed in this paper is improved by incorporating a multi-step prediction method. This enhancement enables effective prediction and compensation of the delay signals lost by the NCS, ensuring the output performance of the parallel buck converter. Finally, the superiority of the proposed method is verified by designing simulations and experiments.

1. Introduction

The parallel DC/DC converter finds extensive application across various domains, including electric vehicles, photovoltaic systems, telecommunication base stations, and other electric energy conversion fields [1,2]. Its remarkable attributes include the mitigation of physical stress on the converter during energy flow by employing voltage equalization and parallel techniques [3,4]. Consequently, these features contribute to the enhancement of the converter’s output power [5,6].
In engineering applications, network control systems (NCSs) are employed to manage parallel DC/DC converters because of their ease of deployment and operation [7,8]. Since the control signals for parallel DC/DC converters as well as the status signals from sensors and actuators are transmitted via network channels, the network transmission is often assumed to be ideal during the system design phase [9,10]. However, practical experience reveals that, owing to limitations in network bandwidth and signal processing speed, network controllers exhibit signal transmission delays, resulting in packet loss [10,11]. This phenomenon significantly impairs the stability of the control system’s output [12,13]. Furthermore, the network signal transmission delay and packet loss rate are influenced by various factors that change over time, rendering them highly uncertain [14,15]. Given the random occurrence of network transmission delays and packet losses, selecting and adjusting the signal sampling period for parallel DC/DC converters is a formidable challenge. This not only impacts the quality of the converter’s output power but also hampers the overall control performance enhancement of the NCS [16,17].
When comparing the delay in network transmission with the system sampling period, the delay can be categorized into two types: short delay and long delay. Short delay refers to cases where the signal transmission delay is less than or equal to a single sampling period, while long delay occurs when the delay exceeds the sampling period [18,19]. Addressing the impact of these different delays on NCS has emerged as a prominent research area. Initially, Pang et al. assumed that the signal transmission delay between the sensor, controller, and actuator made up a short delay. Accordingly, they developed a controller that considered the impact of this delay. However, this method’s reliance on the assumption of only short delays overlooked the possibility of encountering long delays, thereby imposing limitations on its effectiveness [20]. Yan et al. designed an event-triggered H∞ controller for NCSs with network channel delay. The network channel delay is modeled as a distributed delay with a probability density function as its kernel, and the closed-loop event-triggered control system is established as a distributed delay system. However, the method proposed in the literature is based on the continuous domain without exploiting the potential influence of discretization on the stability of the event-triggered H∞ controller. Hence, the implementation and application performance of the designed method is reduced [21]. Kim et al. proposed a new method to obtain a maximum allowable delay bound for the scheduling of NCSs. The method is planned in terms of linear matrix inequalities and can provide a much less conservative delay bound than the existing methods, and a network scheduling method is presented based on the delay obtained through the proposed method. However, the method of obtaining the transmission delay of NCSs is not clearly provided in the literature, and only the estimated delay length is used to assign network nodes to the transmission signal of the system, which reduces the reliability of the system [22]. Heemels et al. presented a general framework that incorporates communication constraints, varying transmission intervals and varying delays, and an explicit construction of a continuum of Lyapunov functions is provided based on a newly developed NCS model including all these network phenomena, then the maximally allowable transmission interval and the maximally allowable delay to guarantee stability of the NCS in the presence of communication constraints. However, the literature has not put forward an exact and effective solution for different transmission intervals and delays [23]. Bibhu et al. presented the development of a novel synchrophasor measurement-based wide-area centralized damping controller to improve the stability of a power system in the presence of time-varying delay and packet dropout in the communication network. This method depends on the measurement of the transmission delay itself, which requires high precision of the control system [24]. In this literature [25], a networked predictive control strategy is proposed for discrete networked systems to deal with the random delay. However, this method treats the network transmission delay as a fixed delay and cannot be applied to complex network delays. Based on the analysis provided, most studies predominantly focus on the continuous time domain, neglecting the discrete state of NCSs and the nuanced performance analysis concerning various types of delays affecting the system. And the problem of measuring the transmission delay of the system has become a difficult problem restricting the design of the controller, the challenge of effectively compensating random delays in control signals of NCSs requires further improvement. This paper systematically considers the practicability of continuous domain control design and discrete domain controller transformation, analyze the impact of different types of delay on the system NCS, and use the signal retention characteristics of the sensor to avoid the measurement of transmission delay.
A large amount of literature shows that the application of sliding mode control (SMC) in parallel DC/DC converters combines robustness, fast response, and enhanced current-sharing capabilities. These advantages make the SMC strategy an attractive choice for enhancing the performance and reliability of parallel DC/DC converter systems [26,27]. The literature [28] proposes a novel nonlinear control method for the input-parallel output-series modular dual active bridge DC/DC converter, which regulates the DC-bus voltage and individual module voltages together. A uniform quantization design method for the parallel text DC-DC converter’s NCS is proposed in [29] in combination with the SMC strategy to solve the problem that the performance of the system is poor. The literature [30] shows the analysis and design of a parallel-connected converter system using sliding mode control techniques. And a new general SMC is proposed for the DC-DC converter that can regulate the output voltage in the literature [31]. The literature [32] also presents a control design procedure for DC-DC power converters, which develops SMC algorithms for several types of DC-DC converters with different control objectives, and complete and incomplete information about system states.
In this paper, a discrete domain SM current-sharing controller based on linear sliding mode control (LSMC) strategy is designed for the parallel DC/DC converter’s NCS, with the buck type being used as an example. The study focuses on analyzing the impact of uncertain and random transmission delays on performing the parallel buck converter’s NCS, particularly in the presence of system disturbances. To address this, a multi-step prediction method is employed for compensating the delay signal in the NCS. The article makes the following specific contributions:
  • Considering a parallel buck converter’s NCS with a random time delay, a master-slave current-sharing controller is designed based on the LSMC in the continuous domain. Then the zero-order holder (ZOH) is used to realize the discretization of the designed system, and the stability conditions of the discrete system are further determined through the Lyapunov equation;
  • Based on the length characteristics of different transmission delays, the effects of uncertainty and randomness on performing parallel buck converter’s NCS with system disturbance are analyzed, which lays a foundation for the design of delay compensation strategy;
  • In order to solve the problem of the influence of random delay on the system stability, the LSM controller is improved based on the multi-step prediction method, and the system parameter conditions are provided based on analyzing the stability of the designed control system;
  • Designed simulations and experiments prove the effectiveness of the proposed method.

2. Design of SMC for the Parallel DC/DC Converter

This paper takes a typical n-phase parallel buck converter system as an example of designing its NCS. The overall structure of the system is shown in Figure 1 below.
In Figure 1, E is the DC input voltage source; vO is the output voltage of the parallel buck converter; R is the load resistance; Li and Ci represent the filter inductance and capacitance of phase i (i = 1, 2, …, n), respectively; iLi and iCi represent the current flowing through Li and Ci, respectively; iRi indicates the current output of each phase to load R, and satisfying iRi = iLiiCi; VDi is phase i continuous current diode; Swi represents the phase i switching power tube, often used by N-MOSFET or IGBT, whose “on” and “off” state are controlled by the “1” and “0” pulses of the signal ui; Vref represents the output reference voltage of the converter; and si is the system state variable output by the SM controller.
In order to be closer to the real NCS, the time delay of signal transmission between the feedforward channel and the feedback channel is considered in Figure 1, and it is assumed that the delay from the sensor to the controller is τs, the delay from the controller to the actuator is τc. In fact, if the feedback control system can maintain static properties, these two delays can be lumped together as τ = τs + τc, and the τ is the total delay in the NCS [31]. For the convenience of description, the subscript “τ” is used to represent signals with transmission delays, such as iLiτ, vOτ, and uiτ. It should be noted here that the delay τ does not change the characteristics of the signal itself, such as uiτ and ui are all output “1” or “0” control signals.

2.1. Modeling of the Parallel Buck Converter System

In order to facilitate the analysis of the energy flow process of the converter, the switching loss of the converter is ignored here, and it is assumed that the parallel buck converter works in continuous current mode (CCM), and each phase control signal uτ is generated by the same pulse width modulation (PWM). Thus, the output current of each phase of the system can meet iRi = vO/(nR). By analyzing the working process of the converter when the power tube Swi is switched on and off, and combining Kirchhoff’s circuit law and the characteristics of Li and Ci components, the following converter model can be obtained:
S w i   on   d i L i d t = 1 L i E v O d v O d t = 1 C i i C i = 1 C i i L i i R i ,   S w i   off   d i L i d t = 1 L i v O d v O d t = 1 C i i L i i R i
Using the characteristic of control signal uiτ output “0” or “1”, and substituting iRi = vO/(nR) into (1), then the system model can be represented uniformly as:
d i L i d t d v O d t = 0 1 L i 1 C i 1 n R C i i L i v O + E L i 0 u i τ

2.2. Design of the SM Controller

Due to the simple structure of LSM, the impulse switching control of uiτ signal can be satisfied on the basis of ensuring the robustness of the system [29]. Therefore, this paper adopts the LSM to design the parallel DC/DC converter control system in the continuous domain. For the circuit topology is shown in Figure 1, the phase i is taken as the object, and the output voltage deviation and its derivative of the phase i are respectively defined as state variables x1 and x2 as:
x 1 i τ = v O τ V r e f x 2 i τ = x ˙ 1 i τ = v ˙ O τ
where Vref is the reference value of the output voltage v of the converter; x1 and x2 are bounded variables and satisfy |x1| ≤ ψx1 and |x1| ≤ ψx2, ψx1 > 0 and ψx2 > 0 are boundary constants. By further substituting (2) into (3), the state space model of the buck system can be obtained as:
x ˙ i τ t = A i x i τ t + b i u i τ t + f i + ζ i t
where the state vector x(t) = [x1(t), x2(t)]T, and there is ||x(t)|| ≤ ψxiτ, ψxiτ = [ψx1, ψx2]T is the boundary constant vector; ζi(t) is the matching disturbance of the system, which satisfying ζi(t) = biδi(t), where δi is the actual bounded disturbance of the external input, which satisfying |δi(t)| ≤ βi, and βi is the upper bound constant. The coefficient matrix Ai, bi, and fi can be expressed as:
A i = 0 1 1 L i C i 1 n R C i ,   b i = 0 E L i C i ,   f i = 0 V r e f L i C i
The design of LSMC generally includes LSM surface and control law. And the LSM surface of the system can be designed by the state variables in (4) as:
s i t = λ i x 1 i τ t + x 2 i τ t + k i 0 t x 1 i τ t d t
where si(t) is the sliding variable of the phase i controller; λi and ki are the coefficients of the SM surface, and satisfying λi > 0 and ki > 0.
Remark 1.
It should be noted that λi can be used to adjust the convergence rate of the si(t) of the system, but the chattering of the system state will also be aggravated with the increase in λi. Hence the integral term is introduced in (6) to help adjust the steady-state error of the system output and further enhance the robustness of SMC. And it is necessary to analyze the motion characteristics of the designed sliding surface in (6):
When the system state reaches the preset SM surface si(t) = 0, it can be obtained that:
x ¨ 1 i τ t + λ i x ˙ 1 i τ t + k i x 1 i τ t = 0
Here defining x1iτ(0) and x2iτ(0) = x ˙ 1 i τ ( 0 ) as the initial values of x1iτ(t) and x2iτ(t). By introducing the Laplace transform, can we get the unique solution to (6a) as:
x 1 i τ ( t ) = x 1 i τ 0 2 λ i + λ i 2 4 k i + x ˙ 1 i τ 0 2 λ i 2 4 k i e λ i + λ i 2 4 k i 2 t + x 1 i τ 0 2 λ i λ i 2 4 k i + x ˙ 1 i τ 0 2 λ i 2 4 k i e λ i λ i 2 4 k i 2 t
It can be obviously seen from (6b) that the coefficient ki can be used to adjust the convergence rate of the exponential terms in each term, which not only avoids the chattering problem caused by the use of larger λi, but also clearly provides the limit range λi2 > 4ki of λi, i.e., the selection of ki should also be smaller to improve the output accuracy of the system.
As for the control law usiτ(t) of the LSMC in the phase i, which is usually composed of the equivalent control law ueqiτ(t) and the switching control law uNiτ(t). In the process of system convergence, the system state rapidly reaches the preset SM surface si(t) = 0 under the action of ueqiτ(t), and then moves along si(t) = 0 under the action of uNiτ(t) to the convergence point. Combining the above state motion characteristics of the SMC system, ueqiτ(t) can be obtained by finding the zero crossing of the first derivative of si(t) in (6). Therefore, the first derivative of si(t) and the system state variable in (3) can be substituted into it as:
s ˙ i t = 1 L i C i x 1 i τ t + λ i 1 n R C i x 2 i τ t + E L i C i u s i τ t V r e f L i C i + E L i C i δ i t
In (7), if s ˙ i t u e q i τ = 0 , the expression of ueqiτ(t) can be expressed as:
u e q i τ t = 1 E x 1 i τ t L i C i E λ i 1 n R C i x 2 i τ t + V r e f E δ i t
Considering the switching characteristics of the parallel buck converter corresponding to (1), uNiτ(t) can be further designed as:
u N i τ t = η i sgn s i t
where ηi is the switching control gain and satisfying ηi > 0. By combining (8) and (9), the control law usiτ(t) of LSM can be obtained as:
u s i τ t = u e q i τ t + u N i τ t = k PWM u i τ t
where kPWM represents the required gain after the continuous control signal usiτ(t) is converted into the switching signal u(t) by PWM. According to the literature [33], usiτ(t) is essentially the switching duty cycle of the converter, so the LSMC designed in this paper is essential to adjust the output voltage of the system by controlling the switching duty cycle of the parallel buck converter.

2.3. Discretization and Stability Analysis of the System

In order to further expand the application of the designed SMC system in digital circuits and facilitate the analysis of the transmission delay process of the NCS, the SMC of the parallel buck converter designed in (4), (6), and (10) will be discretized. Here the ZOH is used to discretize the system, and system states in (4) can be transformed into:
x i τ k + 1 h = Φ i x i τ k h + Γ i u s i τ k h + Λ i + Γ i δ i k h
where x(kh) = [x1(kh), x2(kh)]T represents the state of the discrete system, and relationship of ||x(kh)|| ≤ ψxiτ is held; usiτ(kh) stands for the discrete control law; h is the signal sampling period, and satisfying 0 < h << 1; the expressions of the discrete coefficient matrix Φi, Γi and Λi can be expressed as:
Φ i = e A i h = I + 0 h e A i t d t A i = I + A i h + A i 2 h 2 2 ! + O h 3 Γ i = 0 h e A i t d t b i = b i h + A i b i h 2 2 ! + O h 3 Λ i = 0 h e A i t d t f i = f i h + A i f i h 2 2 ! + O h 3
where O(h3) is the third-order infinitesimal of h. Since the h always remains unchanged during the operation of the discrete system, it can be regarded as a constant value in theory, and (11) can be further simplified as:
x i τ k + 1 = Φ i x i τ k + Γ i u s i τ k + Λ i + Γ i δ i k
Similarly, the LSMC designed in (6), (8) and (9) can be discretized by ZOH, and discrete SM surface si(k), discrete equivalent control law ueqiτ(k) and discrete switching control law uNiτ(k) can be obtained respectively as:
s i k = λ i x 1 i τ k + x 2 i τ k + k i k = 0 t x 1 i τ k = c i x i τ k
u e q i τ k = c i Γ i 1 c i Φ i I x i τ k c i Λ i c i Γ i δ i k
u N i τ k = η i sgn s i k
where the parameter matrix ci = [λi + kiSxi, 1], Sxi is the sum operator of discrete variables. The discrete SM control law usiτ(k) = ueqiτ(k) + uNiτ(k) can be obtained from (15) and (16).
Remark 2.
The sum operator Sx represents summing the discrete variables of the system throughout sampling time, which is introduced in (14) for simplifying the formula expression of the discrete system and satisfies:
S x x i τ k = k = 0 t x i τ k = k = 0 t x 1 i τ k + x 2 i τ k = k = 0 t x 1 i τ k + k = 0 t x 2 i τ k
It is worth noting that Sx belongs to the bounded operator when applied to discrete variables, and the following relationship can be obtained:
k = 0 t S x x i τ k 2 = k = 0 t k = 0 t x i τ k 2 k = 0 t k = 0 t x i τ k 2 k = 0 t k = 0 t ψ x i τ 2
It can be further deduced from (16b) that:
S x x i τ k ψ x i τ x i τ k ψ x i τ S x 1
Since the summation form Sxx corresponds to the integral operation ∫xdt in the continuous field, it needs to be emphasized here that Sxx is satisfied when the forward difference or the backward difference is checked and divided (the backward difference was divided into examples):
S x x i τ k S x x i τ k 1 h = k = 0 t x i τ k k = 0 t x i τ k 1 h = x i τ k
It can be seen from (16d) that introducing the sum operator does not change the properties of each variable and is only used to represent the operation process.
The stability of the discretized system will be analyzed below. First, the Lyapunov equation Vi can be designed as:
V i k = s i 2 k
In order to ensure that the system state in the discrete domain can converge under the action of the LSMC, (17) must meet the following conditions [29]:
Δ V i k = s i 2 k + 1 s i 2 k < 0
By substituting (13) into (14), the si(k + 1) can be obtained as:
s i k + 1 = c i Φ i x i τ k + c i Γ i u s i τ k + c i Λ i + c i Γ i δ i k = s i k + c i Φ i I i x i τ k + c i Γ i u s i τ k + c i Λ i + c i Γ i δ i k
Theorem 1.
For the discrete LSMC system designed in (14)–(16), if the sampling period h meets h < 2nRCi, the state of the discrete system can converge along the preset SM surface in finite steps.
Proof of Theorem 1.
By substituting usiτ(k) and (19) into (18), ΔVi(k) can be rewritten as:
Δ V i k = s i k c i Γ i η i sgn s i k 2 s i 2 k = 2 c i Γ i η i s i k + c i Γ i η i 2
In (20), the term O(h3) of Γi can be ignored. Taking into account the opposite effect of (ciΓiηi)2 on the negative of ΔVi(k), it is possible to subtract it from (20) and subsequently transform (20) by substituting (12) into it in the following manner:
Δ V i k > 2 c i Γ i η i s i k 2 E h L i C i + λ i + k i S x i E h 2 2 L i C i E h 2 2 n R L i C i 2 η i s i k
Due to the switching control gain ηi > 0 in (21), when the system state does not reach the SM surface, that is, when si(k) ≠ 0, in order to ensure the establishment of Lyapunov stability theorem ΔVi(k) < 0, the following relationship must be satisfied:
E h L i C i + λ i E h 2 2 L i C i + k E h 2 2 L i C i E h 2 2 n R L i C i 2 > E h L i C i E h 2 2 n R L i C i 2 > 0 h < 2 n R C i
By combining the parameter attribute of E, Li, Ci, λi in (22), it is easy to get that the limited range h < 2nRCi of h. Thus si2(k + 1) < si2(k) in (18), i.e., ||si(k + 1)|| < ||si(k)||, hence ||si(k)|| decreases monotonously and after a finite number of steps, the system state will enter the admissible domain where ||si(k)||→0, and the subsequent part of the state trajectory will be in si(k) = 0 under ueqiτ(k) and discrete-time sliding mode will take place.
It is clear from (22) that the stability of the discrete system is influenced by h. The circuit parameters of the parallel buck converter dictate the maximum permissible value for h. In real-world applications, setting h excessively large is not advisable, as it compromises the desirable output performance of the LSMC system. □

3. Analysis of the Influence of Signal Transmission Delay on the System

The signal transmission delay in a discrete NCS can be categorized into two types: short delay and long delay. Short delay occurs when the signal transmission delay is less than or equal to one sampling period, while long delay occurs when the delay exceeds one sampling period. In the forthcoming simulations designed in Matlab/Simulink, the paper will conduct a detailed analysis of how both short and long transmission delays impact the performance of the discrete NCS system designed in (14)–(16). The focus of this study is on the three-phase parallel buck converter, and the circuit parameters are presented in Table 1 below.

3.1. Analysis of the Influence of the Short Delay on the NCS

Considering the stability condition of the discrete system in (21), the sampling period h = 0.1 ms is selected here, and the transmission delay τ of the parallel buck converter NCS is within two random delay intervals [0, 0.05 ms] and [0, 0.1 ms], and the τ determined instantaneously in the current step is randomly split into τs and τc to ensure the reliability of the simulation system. In order to further highlight the effect of different random short delays on the system output performance, the case of no delay is added as a control group. The simulation results are shown in Figure 2 and Table 2.
From the output voltage v shown in Figure 2a,c, it is observed that when the transmission delay τ randomly falls within the range of 0–0.05 ms and 0–0.1 ms, the v remains essentially the same in both cases. This observation is further supported by the steady-state errors Δv, as observed in Table 2, which amount to 0.09 V and 0.12 V, respectively. These errors closely approach the output performance in the absence of any delay. It can be concluded that short delays have minimal impact on the system output v, thus rendering its influence negligible in practical engineering applications.
Figure 2b,d display the system inductance current iLiτ under different short delays. According to the data presented in Table 2, the maximum ripple amplitude ΔiLiτ at random time delays within the interval [0, 0.05 ms] and [0, 0.1 ms] amounts to 0.38 A and 0.57 A, respectively, both of which exceed the value of 0.21 A observed in the absence of time delay. This amplitude of ΔiLiτ gradually increases with increasing delay duration. It is important to note that the system continues to operate under CCM in both cases. This observation signifies that the system can maintain a continuous current output even in the presence of short delays, with the output voltage being essentially unaffected.

3.2. Analysis of the Influence of Long Delay on the NCS

With h = 0.1 ms unchanged, three kinds of random delay τ of different lengths [0, 0.2 ms], [0, 0.4 ms], and [0, 0.6 ms] were added to the system, respectively, τs and τc are also randomly obtained from τ in the current step, and a delay-free group is also added for control. The simulation results are shown in Figure 3 and Table 2 below.
The impact of random long delays on the stability of the NCS is evident in the findings presented in Figure 3. In the scenarios depicted in Figure 3a,b, when the random long delay falls within the range of [0, 0.2 ms], the output current error ΔiLiτ of phase i reaches 1.02 A. Despite this, the system operates within CCM, maintaining a steady state error Δv of 0.22 V. During this period, the system exhibits fundamental stability.
Contrastingly, as illustrated in Figure 3c,e, when the random long delay extends to [0, 0.4 ms] or [0, 0.6 ms], the system’s output voltage v experiences significant fluctuations. The corresponding Δv values reach 0.31 V and 0.35 V, respectively. Examination of the iLiτ diagrams in Figure 3d,f reveals that, in both delay cases, ΔiLiτ surpasses 1.2 A, indicating a transition to discontinuous current mode DCM and consequent system instability.
These observations emphasize the substantial impact of prolonged delays on the NCS. Notably, as the delay length increases relative to the sampling period h, the system’s stability deteriorates. In summary, the findings underscore the critical role of delay management in preserving the stability of the NCS.

4. Transmission Delay Compensation Strategy Based on Multi-Step Prediction Method

Based on the analysis above, it can be concluded that while the impact of short delays can be negligible, long delays significantly deteriorate the steady-state performance of the NCS. To mitigate this issue, this study proposes a multi-step prediction method with SMC to analyze the current system state and predict the system state backwards in multiple sampling periods. By doing so, the lost control signal because of transmission delay can be compensated, ensuring the desired output performance of the system.

4.1. Design of the Sliding Mode Controller Based on Multi-Step Prediction Method

For bounded delay τ (τ > h), which can be expressed as a multiple of sampling period h relations, i.e., τ = (d’ + l)h, where the d’ ∈ [1, M − 1] ∈ N+, l ∈ [0, 1) and M is the upper limit positive integers of (d’ + l). Due to the random variation in l, τ is not always an integer multiple of h. To simplify the analysis and design, this study compensates l to 1, resulting in τ = dh, where d ∈ [2, M] ∈ N+. It should be noted that this compensation for l does not significantly alter the original influence of long delay τ on the system, as shown in Figure 3. Therefore, the discrete model of the system in (13) can be re-expressed as:
x i τ k + 1 = Φ i x i τ k + Γ i u s i τ k d Γ i V r e f E + Γ i δ i k
The delay compensation of the system will be realized based on the multi-step prediction method, and its specific working principle is shown in Figure 4 below:
As shown in Figure 4, since the upper bound of the NCS signal transmission delay is Mh, a buffer uMi = [uMi(1), uMi(2), ⋯, uMi(d), ⋯, uMi(M)] of length M can be added in front of the actuator to store the pre-predicted control quantity usi, and the initial value of all elements in uMi is zero. By sampling the system output signal every single sampling period h, the obtained sampled data x(k) is sent to the LSM controller by the transmission delay τc; the designed LSM controller generates control signal packet usi(k + p)(p = 1, 2, ⋯, M) according to the current system state x(k) prediction; after the usi(k + p) enters the buffer after the transmission delay τs, and is loaded into the corresponding uMi in order to be stored, and then the required uMi(d) is transmitted to the actuator after the delayed judgment, so as to complete the effective compensation of the system transmission delay within the current h sampling period. It is worth noting that when the packet or actual sample data xi(k) = [x1i(t), x2i(t)]T with v, cannot be updated in real-time due to the delay τc greater than h, the buffer will transmit the control signal uMi(d + q) to the actuator in order, where q represents the integer quotient of τc divided by h, so as to achieve uninterrupted sequential compensation control.
Remark 3.
It should be noted here that in the multi-step prediction-based the NCS shown in Figure 4, both τc and τs are taken into account in the feedback system. The relationship between τc and h directly influences the state of the control signal compensated to the system actuator, while the size of τc and τs jointly affects the determination of the upper limit of the transmission delay M. This paper determines whether τc is greater than h by evaluating the equality of system states x(k) and x(k + 1), which cleverly takes the advantage of the fact that when τc > h, sensors will transmit the system state saved at the last time when the next sampling time h arrives, avoiding the trouble caused by the delay monitoring of the NCS.
Based on the analysis mentioned above, the crucial step for the compensation system to uphold its efficient output lies in acquiring the buffer control amount uMi. Hence, the subsequent paragraphs will outline the entire design procedure for the sliding mode controller based on the prediction method, which is shown in Figure 5.
Step 1: Estimate system state x(k + j)(j = 1, 2, ⋯, M) based on sampled data x(k).
In the discrete model of (13), when x(k) and usiτ(k) are known, xi(k + 1) and usiτ(k + 1) can be obtained. In this way, the system state prediction formula can be designed as
x ^ i k + j = Φ i x ^ i k + j 1 + Γ i u ^ s i k + j 1 Γ i V r e f E + Γ i δ i k
where x ^ i k + j is the estimated value of system state xiτ(k + j) after the j-th sampling period predicted by state xiτ(k), and there is x ^ i k = xiτ(k); u ^ s i k + j 1 is the control signal corresponding to the predicted state and satisfying u ^ s i k = usiτ(k). Since the M times sampling period needs to be estimated backwards, the number of elements u ^ s i is M, and the initial value of each element is zero. For x ^ i k = xiτ(k) and u ^ s i k = usiτ(k), this will be further explained later in terms of estimated errors. In the process of algorithm implementation, by using the iterative relationship shown in (24), the predicted state x ^ i k + j of the system at the next time can be obtained to acquire the system-predicted control signal u ^ s i k + j 1 .
Step 2: Discrete the LSM controller is designed based on the predicted state.
As seen from (24), in order to obtain x ^ i k + j , the control signal u ^ s i k + j 1 must be obtained first. The discrete LSM surface corresponding to a can be obtained from (14) that:
s ^ i k + j 1 = c i x ^ i k + j 1
By substituting (15) and (16) into (25), the equivalent control law u ^ e q i k + j and u ^ N i k + j the switching control law can be obtained respectively as:
u ^ e q i k + j 1 = c i Γ i 1 c i Φ i I x ^ i k + j 1 + V r e f E δ k + j 1
u ^ N i k + j 1 = η i sgn s ^ i k + j 1
The control law u ^ s i k + j 1 can be further obtained by combining (25) and (26) as:
u ^ s i k + j 1 = u ^ e q i k + j 1 + u ^ N i k + j 1 = c i Γ i 1 c i Φ i I x ^ i k + j 1 + V r e f E η i sgn s ^ i k + j 1 δ k + j 1
Therefore, after x(k) is obtained from each sampling period, u ^ s i k + j 1 and x ^ i τ k + j in the following M sampling periods can be predicted by steps 1 and 2 respectively, u ^ s i k + j 1 can also be turned into a switching signal u ^ i k + j 1 by PWM as shown in (10). Hence, the predicted control signals in the controller buffer are continuously supplemented.
Step 3: Update the buffer data with predictive control signals.
The M predictive control signals obtained in step 2 are arranged in sequence and sent to the buffer in a unified package to update the data in uMi, that is, uMi(j) = u ^ s i k + j . After that, the system will select the corresponding uMi(d) according to the measured system transmission delay τ and send it to the actuator. If the data in the buffer is not updated and the next sampling period has been entered at this time, the system will successively send uMi(d + 1) and subsequent control signals in the buffer to the actuator to ensure the continuity of the output signals of the controller, and the converter maintains stable operation; if the buffer has been updated, repeat step 3.
By repeating the above steps according to the sampling time h, the transmission delay of the NCS signal in the parallel buck converter can be compensated.

4.2. System Stability Analysis

The approach proposed in this paper aims to use the current system state for predicting future state quantities, enabling the proactive acquisition of corresponding control quantities to compensate for signal transmission delays. Thus, the crucial aspect of analyzing system stability lies in evaluating the accuracy of these predictions. This paper introduces an error variable following, which indicates the discrepancy between the estimated value and the actual value of the subsequent system:
e i ( j ) = x i τ ( k + j ) x ^ i ( k + j )
where ei(j) represents the deviation between the actual state value of the system and the true state value. And the expression of x(k + j) can be obtained from (13) as:
x i τ k + j = Φ i x i τ k + j 1 + Γ i u s i τ k + j 1 Γ i V r e f E + Γ i δ i k + j 1
Further substitute (24) and (30) into Equation (29) to obtain:
e i ( j ) = Φ i j x i τ ( k ) + Φ i ( j 1 ) Γ i u s i ( k ) + + Φ i Γ i u s i ( k + j 2 ) + Γ i u s i ( k + j 1 ) + Φ i ( j 1 ) Γ i δ i ( k ) + + Φ i Γ i δ i ( k + j 2 ) + Γ i δ i ( k + j 1 ) Φ i j x i τ ( k ) Φ i ( j 1 ) Γ i u s i ( k ) Φ i Γ i u ^ s i ( k + j 2 ) Γ i u ^ s i ( k + j 1 ) = q = 0 j 1 Φ i q Γ i δ i ( k + j 1 q )
According to the design idea of the buffer, its memory length should meet Md. Since d is constant, the control signal predicted by the sampled system state x(k) is u ^ s i k + d , which corresponds to the LSM surface s ^ i k + d . The Lyapunov equation can also be designed as:
V ^ i k + d = s ^ i 2 k + d
According to the stability conditions of the discrete LSMC system, in order to ensure the stability of the multi-step predictive control system, (32) must meet the following conditions:
Δ V ^ i k + d = V ^ i k + d + 1 V ^ i k + d = s ^ i 2 k + d + 1 s ^ i 2 k + d < 0
For ease of analysis, Equation (32) can be further rewritten as:
Δ V ^ i k + d = s ^ i k + d + 1 s ^ i k + d 2 + 2 s ^ i k + d s ^ i k + d + 1 s ^ i k + d < 0
Let Δ s ^ i k + d = s ^ i k + d + 1 s ^ i k + d , then from (24) to (29) we can get:
Δ s ^ i k + d = s ^ i k + d + 1 s ^ i k + d = c i x ^ i k + d + 1 c i x ^ i k + d = c i Φ i e i d c i e i d + 1 + c i Γ i u ^ N i k + d + c i Γ i δ i k + d
By substituting (35) into (34), there is:
Δ V ^ i k + d = Δ s ^ i k + d 2 + 2 s ^ i k + d Δ s ^ i k + d = c i Φ i e i d c i e i d + 1 + c i Γ i u ^ N i k + d + c i Γ i δ i k + d 2 + 2 s ^ i k + d c i Φ i e i d c i e i d + 1 + c i Γ i u ^ N i k + d + c i Γ i δ i k + d < 0
In (36), without considering s ^ i k + d = 0 , it can be divided into s ^ i k + d > 0 and s ^ i k + d < 0 to discuss system stability:
(1)
When s ^ i k + d > 0 , from (36) we can get:
Δ V ^ i k + d = Δ s ^ i k + d 2 + 2 s ^ i k + d Δ s ^ i k + d = c i Φ i e i d c i e i d + 1 + c i Γ i u ^ N i k + d + c i Γ i δ i k + d 2 + 2 s ^ i k + d c i Φ i e i d c i e i d + 1 + c i Γ i u ^ N i k + d + c i Γ i δ i k + d q = 0 d 1 c i Φ i q + 1 Γ i β i p = 0 d c i Φ i p Γ i β i + c i Γ i β i + c i Γ i u ^ N i k + d 2 + 2 s ^ i k + d q = 0 d 1 c i Φ i q + 1 Γ i β i p = 0 d c i Φ i p Γ i β i + c i Γ i β i + c i Γ i u ^ N i k + d = c i Γ i u ^ N i k + d 2 + 2 s ^ i k + d c i Γ i u ^ N i k + d < 0
Since s ^ i k + d > 0 , in order to ensure that the relationship in (36) holds, the parameters of the control system need to meet the following conditions:
c i Γ i u ^ N i k + d < 0 2 s ^ i k + d > c i Γ i u ^ N i k + d
By substituting (27) into (38), (38) can be rewritten as:
c i Γ i η i < 0 2 s ^ i k + d > c i Γ i η i
When the sampling period h meets 0 < h < 2nRCi, ciΓi > 0 is established by substituting ci and Γi into (39). Since the switching gain ηi > 0, the establishment condition of (39) is
s ^ i k + d > E h L i C i + λ i + k i S x i E h 2 2 L i C i E h 2 2 n R L i C i 2 η i 2
(2)
When s ^ i k + d < 0 , from (36) we can also get:
Δ V ^ i k + d = c i Γ i u N i k + d 2 + 2 s ^ i k + d c i Γ i u ^ N i k + d < 0
Given that s ^ i k + d < 0 , it is essential to satisfy the following conditions for the parameters of the control system in order to maintain the validity of the relationship expressed in Equation (41):
c i Γ i u ^ N i k + d > 0 2 s ^ i k + d < c i Γ i u ^ N i k + d
And (42) can be rewritten as follows by further substituting (27) into it:
c i Γ i η i > 0 2 s ^ i k + d < c i Γ i η i
The parameter matrixes ci and Γi can also be substituted into (43) as:
s ^ i k + d < E h L i C i + λ i + k i S x i E h 2 2 L i C i E h 2 2 n R L i C i 2 η i 2
According to (40) and (44), the stability condition of the multi-step predictive control system designed in this paper can be expressed as:
0 < c i Γ i η i 2 < s ^ i k + d
From (45), the results show that the system state will eventually converge to the vicinity of the SM surface as:
s i Δ = s i k + j c i Γ i η i 2 s ^ i k + d c i Γ i η i 2

5. Simulation and Experimental Verification

5.1. Simulation Analysis and Verification

The performance of the SMC system designed in this paper will be evaluated through simulations. Specifically, the output current and system control quantity for phase i of the parallel buck converter’s NCS will be investigated. The sampling period is set to h = 0.1 ms, and the controller parameters are set as λi = 600, ki = 100. Random delays τ, ranging from [0, 0.2 ms], [0, 0.4 ms], and [0, 0.6 ms], will be introduced to the NCS, and τs and τc obtain the delay randomly assigned by τ, while keeping the parameters in Table 1 unchanged. And the random noise disturbance of 0–1 V is superimposed on the input of each phase of the control signal of the buck converter. Table 3 and Figure 6 below show the simulation results before and after processing with the delay signal compensation.
The system output v, before and after compensation, under different intervals of long delay are presented in Figure 6a,c,e. When the delay τ falls in [0, 0.2 ms], it can be seen that the compensated v is 0.2 V lower than the uncompensated voltage fluctuation, and the dynamic response time of the voltage is nearly 0.01 s higher, and the maximum voltage error Δv_max is reduced from 0.78 V to 0.01 V by compensation. When the delay τ further increases to the range with [0, 0.4 ms], the uncompensated v shows more violent fluctuations, and the steady-state error reached 0.31 V, while the compensated v remained stable, with only 0.08 V steady-state error, and the Δv_max is also reduced 1.38 V. When the τ falls in the range [0, 0.2 ms], it can be seen from the uncompensated v that the transmission of the control signal of the system is seriously damaged at this time, and the Δv and Δv_max reach 0.35 V and 2.41 V, respectively. However, they can be reduced by 0.24 V and 0.99 V through compensation, so that the voltage curve can remain stable, which also evidences that the addition of multi-step predictive control significantly reduces the fluctuation range of the output voltage and current, leading to a more stable system output.
Figure 6b,d,f show the system output current signal iLiτ before and after compensation. With the increase in the system transmission signal delay τ, the fluctuation steady-state error ΔiLiτ of the uncompensated signal iLiτ increases from 1.02 A to 1.61 A, and the maximum current error ΔiLiτ_max increases from 0.44 A to 1.39 A, almost doubling the rated current value, the iLiτ also changes from CCM to DCM. While the fluctuating peak current will cause damage to the stability of the converter load. After the compensation controller is added, it can be seen that the ΔiLiτ decreases by 0.21 A, 0.26 A and 0.23 A, respectively, and the ΔiLiτ_max decreases by 0.07 A, 0.56 A, and 0.72 A, respectively, and the current stability increases significantly. It can further be observed that the enhanced NCS leads to the system output iLiτ operating under CCM, which is attributed to the effective compensation of the multi-step predictive controller for losing the system control signal caused by delays.
Figure 6h visually confirms the continuity of the system control signal usi. It can be observed that with the increase in system transmission delay τ, usi gradually fluctuates, but it can remain continuous and stable under the compensation of the multiple unpredictable controller. When the τ reaches 4 times and 6 times the sampling time h, usi can already remain near 0.5 in the initial 0.5 s to maintain the stable operation of the system. The improvement effectively mitigates the impact of long delays on system output performance, further enhancing the steady-state output performance of the parallel buck converter system.
Figure 6g demonstrates the sliding variable si of the system with different time delays after compensation. Thanks to the multi-step predictive controller, si maintains both continuity and stability despite delays. This not only leverages the characteristics of SMC but also ensures the system’s strong robustness.

5.2. Experimental Verification

In this paper, the dSPACE1006 controller with powerful data computing capability is selected to verify the designed control strategy and some theories. The experimental platform of the parallel buck converter control system based on dSPACE1006 is established as shown in Figure 7a, and its operating process is illustrated in Figure 7b.

5.2.1. Verification of the Effect of Different Delays on NCS’s Output Performance

Keep the converter circuit parameters consistent with those in Table 1. And the controller parameter λi = 600, ki = 100 and the sampling period h = 0.1 ms are set unchanged, so that the signal transmission delay is within four random intervals of [0, 0.1 ms], [0, 0.2 ms], [0, 0.4 ms] and [0, 0.6 ms], respectively. The experimental results are shown in Table 4 and Figure 8 below.
The output voltage v shown in Figure 8a demonstrates that the presence of random delays in the NCS has minimal impact on the output voltage characteristics when the delay is equal to or less than one sampling period. Thus, the effect of this delay type on the system performance can be disregarded. However, further examination of Figure 8b–d and Table 4 reveals that as the transmission delay increases, both the rise time and the maximum error of the system output voltage increase. Precisely, when the random delay ranges from 0 to 0.2 ms, 0 to 0.4 ms, and 0 to 0.6 ms, the maximum error corresponds to values of 0.74 V, 0.89 V, and 0.91 V, respectively. These results indicate a poor steady-state performance that fails to meet the required performance standards, necessitating the implementation of delayed compensation processing. The experimental findings confirm that short delays have a negligible impact on the NCS performance, while longer delays adversely affect both the transient and steady-state performance of the control system and increase the steady-state error. These conclusions align with the outcome of the simulation analysis obtained in Figure 3.

5.2.2. Verification of Compensation Strategy for NCS Transmitted Delay Signal Based on Multi-Step Prediction Method

As seen from Figure 8 and Table 4, performing the control system with random delays of [0, 0.4 ms] and [0, 0.6 ms] is poor, hence, it is very important to compensate the long transmission delay of the NCS in the parallel buck converter, which is one of the important conclusions of this paper. The actual compensation effect of the LSM controller designed in this paper based on the multi-step prediction method to the long transmission delay of the system NCS will be verified by designed experiments.
Similarly, the 0–1 V random noise disturbance signal is superimposed on the input side of each phase control signal of the parallel buck converter. Here, typical random long transmission delay intervals [0, 0.4 ms] and [0, 0.6 ms] shown in Figure 8c,d are selected to verify the effectiveness of the designed controller, and the experimental results are shown in Table 5 and Figure 9.
As evidenced by the output voltage v presented in Figure 9 and the accompanying data in Table 5, both the buffer method and the multi-step prediction method effectively mitigate the adverse impact of signal transmission delay on the steady-state performance of NCS. This mitigation is reflected in a substantial reduction in the maximum error in the system’s output voltage, from 0.89 V and 0.91 V to 0.48 V and 0.57 V, respectively, resulting in a marked improvement in steady-state performance. Following implementing delay compensation, the rise time of the system’s output voltage decreases from 148 ms and 173 ms to 64 ms and 67 ms, respectively, signifying a noticeable enhancement in system response speed. It is worth noting that the system experiences an overshoot phenomenon, with overshoot values of 0.48 V and 0.57 V, respectively, because of employing advanced prediction techniques, which have a detrimental effect on transient performance. An examination of the output voltage waveform reveals sporadic occurrences of minor peaks during the steady-state phase. This observation underscores certain limitations in the multi’s utilization-step prediction method for delay compensation.

6. Conclusions

In this paper, the effect of random long delay on the NCS performance of the parallel buck converter system is analyzed in detail. The results show that the effect of short delays on the system can be ignored, but long delays will increase the steady-state error of the system output and seriously affect the system’s stability. Therefore, this paper proposes a sliding mode control strategy based on the multi-step prediction method. Firstly, the discrete domain model of the system and the LSM controller are constructed and constructed. On this basis, the influence of long delay and matching disturbance on the NCS is fully considered, and the compensation strategy of the multi-step prediction method is designed. Through the continuous supply of the predictive control quantity stored in the buffer, losing the NCS control signal in the case of long delays is compensated, thus easing the impact of signal transmission delay on the system performance and ensuring the stability of the system output. Finally, the multi-step predictive control strategy proposed in this paper demonstrates remarkable improvements in system performance through the designed experiments. On average, this strategy reduces the system’s output steady-state error by 41.6%, while also reducing the output response time by 61.2% and the maximum error of the output signal by 20.6%. These significant improvements clearly validate the superiority of the proposed method, which proves the correction of the proposed method.

Author Contributions

Conceptualization, J.Y. and W.X.; methodology, W.Z.; software, W.Z.; validation, Y.W., J.Y. and W.X.; formal analysis, W.Z.; investigation, J.Y.; resources, W.X.; data curation, W.Z.; writing—original draft preparation, Y.W.; writing—review and editing, Y.W.; visualization, W.Z.; supervision, Y.W.; funding acquisition, Y.W. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the National Natural Science Foundation of China, grant number 51307035 and 62073095.

Data Availability Statement

Data are contained within the article.

Conflicts of Interest

Authors Juan Yu and Wenwen Xiong were employed by the company Yatai Construction Science & Technology Consulting Institute Co., Ltd. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.

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Figure 1. An NCS with transmission delays of the n-phase parallel buck converter.
Figure 1. An NCS with transmission delays of the n-phase parallel buck converter.
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Figure 2. System output performances in random short delay interval: (a) v in 0.05 ms delay; (b) iLiτ in 0.05 ms delay; (c) v in 0.1 ms delay; (d) iLiτ in 0.1 ms delay.
Figure 2. System output performances in random short delay interval: (a) v in 0.05 ms delay; (b) iLiτ in 0.05 ms delay; (c) v in 0.1 ms delay; (d) iLiτ in 0.1 ms delay.
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Figure 3. System output performances in random long delay interval: (a) v in 0.2 ms delay; (b) iLiτ in 0.2 ms delay; (c) v in 0.4 ms delay; (d) iLiτ in 0.4 ms delay; (e) v in 0.6 ms delay; (f) iLiτ in 0.6 ms delay.
Figure 3. System output performances in random long delay interval: (a) v in 0.2 ms delay; (b) iLiτ in 0.2 ms delay; (c) v in 0.4 ms delay; (d) iLiτ in 0.4 ms delay; (e) v in 0.6 ms delay; (f) iLiτ in 0.6 ms delay.
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Figure 4. NCS signal transmission process based on multi-step prediction method.
Figure 4. NCS signal transmission process based on multi-step prediction method.
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Figure 5. Design flow chart of the LSM controller based on multi-step prediction method.
Figure 5. Design flow chart of the LSM controller based on multi-step prediction method.
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Figure 6. The output performance of NCS before and after compensation under different delays: (a) v in 0.2 ms delay; (b) iLiτ in 0.2 ms delay; (c) v in 0.4 ms delay; (d) iLiτ in 0.4 ms delay; (e) v in 0.6 ms delay; (f) iLiτ in 0.6 ms delay; (g) si in long delays; (h) usi in long delays.
Figure 6. The output performance of NCS before and after compensation under different delays: (a) v in 0.2 ms delay; (b) iLiτ in 0.2 ms delay; (c) v in 0.4 ms delay; (d) iLiτ in 0.4 ms delay; (e) v in 0.6 ms delay; (f) iLiτ in 0.6 ms delay; (g) si in long delays; (h) usi in long delays.
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Figure 7. Illustration of the experimental platform based on the dSPACE1006: (a) experimental platform diagram; (b) experimental operation flow.
Figure 7. Illustration of the experimental platform based on the dSPACE1006: (a) experimental platform diagram; (b) experimental operation flow.
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Figure 8. System output voltage v under different time delays: (a) v in 0.1 ms delay; (b) v in 0.2 ms delay; (c) v in 0.4 ms delay; (d) v in 0.6 ms delay.
Figure 8. System output voltage v under different time delays: (a) v in 0.1 ms delay; (b) v in 0.2 ms delay; (c) v in 0.4 ms delay; (d) v in 0.6 ms delay.
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Figure 9. The experimental results of the system output voltage before and after the multistep prediction method: (a) v in 0.4 ms delay; (b) v in 0.6 ms delay.
Figure 9. The experimental results of the system output voltage before and after the multistep prediction method: (a) v in 0.4 ms delay; (b) v in 0.6 ms delay.
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Table 1. System parameters of the parallel buck converter.
Table 1. System parameters of the parallel buck converter.
ParameterValue
Load resistance R10 Ω
Filter inductance Li1 mH
Filter capacitance Ci1000 μF
Reference voltage Vref10 V
Input DC voltage E20 V
Table 2. Effect of different delays on output performances of the NCS.
Table 2. Effect of different delays on output performances of the NCS.
Delay Typeτ (ms)Δv (V)ΔiLiτ (A)System Current Mode
no delay-0.070.21CCM
short delay0.050.090.38CCM
0.100.120.57CCM
long delay0.200.221.02CCM
0.400.311.29DCM
0.600.351.61DCM
Table 3. System performance results before and after delay compensation in different intervals.
Table 3. System performance results before and after delay compensation in different intervals.
τ (ms)Compensated StateΔv (V)Δv_max (V)ΔiLiτ (A)ΔiLiτ_max (A)System Current Mode
0.2No0.220.781.020.44CCM
Yes0.020.010.810.37CCM
0.4No0.312.961.291.01DCM
Yes0.081.581.030.45CCM
0.6No0.352.411.611.39DCM
Yes0.111.421.380.67CCM
Table 4. System output voltage characteristics under different time delays.
Table 4. System output voltage characteristics under different time delays.
τ (ms)Rise Time (ms)Mean Steady-State Error (V)Maximum Amplitude Error (V)
01030.220.37
0–0.11220.400.50
0–0.21380.741.01
0–0.41480.891.41
0–0.61730.911.61
Table 5. The output voltage characteristics before and after treatment with the multi-step prediction method.
Table 5. The output voltage characteristics before and after treatment with the multi-step prediction method.
τ (ms)Compensated StateRise Time (ms)Mean Steady-State Error (V)Maximum Amplitude Error (V)
0–0.4No1480.890.99
Yes640.480.78
0–0.6No1730.911.39
Yes670.570.62
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Yu, J.; Zhang, W.; Xiong, W.; Wang, Y. A Sliding Mode Controller with Signal Transmission Delay Compensation for the Parallel DC/DC Converter’s Network Control System. Electronics 2024, 13, 121. https://doi.org/10.3390/electronics13010121

AMA Style

Yu J, Zhang W, Xiong W, Wang Y. A Sliding Mode Controller with Signal Transmission Delay Compensation for the Parallel DC/DC Converter’s Network Control System. Electronics. 2024; 13(1):121. https://doi.org/10.3390/electronics13010121

Chicago/Turabian Style

Yu, Juan, Weiqi Zhang, Wenwen Xiong, and Yanmin Wang. 2024. "A Sliding Mode Controller with Signal Transmission Delay Compensation for the Parallel DC/DC Converter’s Network Control System" Electronics 13, no. 1: 121. https://doi.org/10.3390/electronics13010121

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