A 87 dB SNR and THD+N 0.03% HiFi Grade Audio Preamplifier

Abstract

This paper presents a significant contribution to high-fidelity audio technology through the comprehensive design and implementation of an advanced audio-grade preamplifier integrated with a high-performance digital-to-analog converter (DAC). The versatility of the digital section allows seamless integration of audio sources from Universal Serial Bus (USB), Bluetooth, or Sony-Philips Digital interface (SPDIF). In addition, the preamplifier accommodates various analog sources, offering flexibility to users. The unique architecture features an innovative resistor network-based DAC and precision components in the analog section, paving the way for achieving unparalleled audio fidelity. The measured distortion values are remarkably low, with a total harmonic distortion plus noise (THD+N) of only 0.03%. Furthermore, the system exhibits a signal-to-noise ratio (SNR) of 87 dB, comparable to industry benchmark. The hardware design sections went into meticulous details, providing an in-depth exploration of each block of the project. The inclusion of test and measurement data from the actual prototype enhances the credibility of the proposed work. This research not only showcases the theoretical operation of the preamplifier and DAC stage but also validates the practical implementation through many rounds of testing and validation. Our proposed work contributes to the field of high-fidelity audio by presenting a novel solution that is comparable to industry standards. The design’s adaptability to many different audio sources, coupled with robust performance metrics, positions it as a benchmark in the field of audio reproduction. The measurement results and findings presented in this paper are poised to influence future advancements in HiFi audio technology.

1. Introduction

In a market dominated by cheap, low quality, mass-produced audio components, finding a quality preamplifier with a rich feature set at an appropriate price point can be quite challenging. Most consumer products utilize delta sigma converters with highly integrated components that are focused on reducing cost and physical footprint [1]. This project seeks to integrate a high-performance digital-to-analog converter, preamplifier, and headphone amplifier into a single unit with high performance. The DAC will be based around an R2R resistor network DAC for reduced total harmonic distortion and improved linearity [2]. The analog section is based on a DC-coupled topology with dual rail power supplies for improved output voltage swing as compared to single rail-powered analog stages. Utilizing high performance integrated circuits in this proof-of-concept allows faster prototyping without the complexities associated with a pure discrete design, without major compromises in performance. Good electronic design is a necessity to have an audio reproduction system with high performance. An ideal high-fidelity (Hi-Fi) component will allow audio to be reproduced with no signal degradation or coloration [3]. The preamplifier will support the connection of multiple digital sources. The onboard digital analog converter should be able to support sampling rates up to 96 kHz with low noise and low distortion audio reproduction. The device will also permit the user to connect and select other external analog sources, with an on-board headphone amplifier based on parallel op-amp architecture which can drive high impedance headphones and a separate line level output. Typical specifications for the prototype would be a targeted signal-to-noise ratio of 75 dB for the digital and analog sections with a total harmonic distortion of 0.05%. The headphone amplifier is targeted to have a signal-to-noise ratio of 65 dB or better and a distortion value of 0.2% in the worst case. These values are defined based on the lowest measurable limits of the test instruments available.

2. System Architecture Overview

The system is comprised of three main sections, namely, the digital, analog, and ancillary sections. Figure 1 depicts an overall block diagram that shows the audio signal flow from a top-level perspective, while Figure 2 and Figure 3 provide the detailed individual schematic IC diagram of each block for the digital and analog sections, respectively. Four digital audio sources are provided in the digital section where the user can switch between them. The output of the digital section meets the analog section after the output stage of the digital-to-analog converters. The user can connect three external analog sources and switch between them. The selected source is routed to either the headphone or line level outputs where a pair of amplified speakers may be connected. Additional sections will need to be designed to accept audio data from a Bluetooth source or USB source, including the required logic to perform audio clock recovery and regeneration. A microcontroller will be used to implement full control of the various functional blocks with options made available to the end user via a user interface.

2.1. Digital Section

The digital section is responsible for receiving digital audio data from various digital sources and converting them to a suitable common format for digital-to-analog conversion. Figure 2 contains a block diagram of the digital section. All received digital audio passes through a SPDIF receiver and is converted to the Philips Inter-IC Sound (I2S) standard before it is passed to the oversampling filter and digital-to-analog converter. The analog current outputs from the DAC are fed to the DAC post-analog stage before output to the preamplifier board. Additional sections handle audio streaming over Bluetooth and USB with the required clock regeneration devices to regenerate a master clock to operate the system. The synchronous and asynchronous data outputs from these chipsets are sent to a SPDIF transmitter so all resulting bitstream will be in a synchronous format.

2.2. Analog Section

Figure 3 depicts an overview of the analog hardware. The current output of the DAC is converted to a voltage using the transimpedance amplifier. The voltage output of the transimpedance amplifier is low-pass filtered before it is provided as a source to the 4:1 input multiplexer. The input multiplexer serves as a source selection where the user can connect three other external analog sources. The output of the multiplexer passes through a buffer and the programmable gain amplifier which functions as a volume control. The two output 2:1 multiplexers determine if the output signal is routed to the line out jack or headphone amplifier with unused output shunted to ground through a resistor to prevent noise coupling. The headphone amplifier comprises of a switchable gain stage and a parallel op-amp driving stage with a relay that connects the amplifier output to the load. All multiplexers, analog switches, and the programmable gain amplifier are controlled via the microcontroller.

2.3. Ancillary Section

The microcontroller controls all operations of the preamplifier and receives input from the user. Figure 4 is an overall block diagram for the control section of the system. The user interacts with the device through a set of push buttons and an alphanumeric liquid crystal display (LCD). The microcontroller interfaces with the peripheral devices over various serial protocols or by switching the state-of-control lines to change the state of various analog and digital hardware components. The first Inter-Integrated Circuit (I2C) bus will be used to interface with the digital audio hardware and the second I2C bus is used for the port expanders operating the user interface elements and the analog section. The programable gain amplifier interfaces with the microcontroller over the SPI serial bus.

3. Circuit Analysis and Design

3.1. Digital Section

3.1.1. Bluetooth Audio Receiver

A Bluetooth audio receiver module is used to handle audio streaming over Bluetooth from portable devices such as notebooks and cellular phones. For the purposes of this implementation, raw audio data can be encoded using the Sub-band Codec (SBC) or Advanced Audio Codec (AAC) codecs prior to transmission over the Bluetooth link due to licensing limitations for the newer and higher data rate codecs such as aptX and LDAC, which are proprietary. The Bluetooth module is also responsible for implementing the Bluetooth stack to facilitate the operation of the necessary Bluetooth profiles for device discovery, media transport, and control signaling. The Microchip BM64 Bluetooth audio module was selected for this project since it offers the higher performance AAC codec support in addition to the mandatory SBC codec. The module is also able to output the received audio in a digital format over I2S but lacks a master clock signal for a downstream receiver to reference. All programming and runtime interfacing is accomplished over a regular UART serial port with the host controller or development system.

3.1.2. USB Audio Receiver

The USB audio receiver receives uncompressed audio over USB. It complies with the USB Implementer’s forum specification to function as a USB audio device with the host device. The host device identifies the USB chipset as an audio class device and can send an uncompressed audio stream to it as USB packets based on its capabilities and defined sampling rate. The Silicon Labs CP2615 USB Digital audio bridge will be used in this project to function as a USB source. CP2615 is based on a system-on-chip (SOC) with an on-board USB transceiver and the necessary logic to implement the functions of a USB audio device. The audio controller can operate in synchronous and asynchronous clocking modes. For this application, the audio controller will be configured to operate in asynchronous mode to allow it to function on its own timing reference, separate from the USB bus clock. The supported sampling rates using this chipset are CD-quality 44.1 kHz and DVD-quality 48 kHz at a maximum bit depth of 24 bits. The received audio is made available over the I²S interface, but the audio controller transmits the audio payload asynchronously during the word clock cycle. The 32-bit clock cycles for an audio sample of a single channel can occur at almost any time during the half cycle of the word clock, which causes compatibility issues with certain timing-sensitive receiving equipment or DACs. To provide compatibility, the asynchronous I²S signal needs to be passed to an I²S receiver that can receive asynchronous data. In this case, the receiver typically implements a free-running state machine with a sufficiently fast settling time to clock the data bits into a register. The register contents are transferred only at the appropriate word clock transition. This task will be handled by the SPDIF transmitter which accepts an asynchronous bitstream and is able to generate a synchronous serial bitstream with a reference clock provided. Figure 5 contains a recorded waveform of the asynchronous I²S transmission. The waveform shows the audio data and bit clock occurring in bursts.

3.1.3. Clock Generator and SPDIF Transmitter

For sources such as the Bluetooth receiver and USB interface that lack a master clock or transmit data asynchronously, the phase-lock loop (PLL)-based clock generator is used to regenerate the master clock which operates at 256 times the base rate of the bit clock. The word clock is used as a reference for the clock generator, which will generate the master clock based on its crystal oscillator reference. The master clock is required to operate the digital core within the SPDIF transmitter.

The SPDIF transmitter accepts synchronous and asynchronous I2S bit streams and converts it to SPDIF format. This arrangement allows sources without a master clock signal to operate the SPDIF transmitter to produce a synchronous bitstream as illustrated in Figure 6. This provides ease of cabling between the boards and allows signal routing using the existing SPDIF multiplexer within the SPDIF receiver. The SPDIF bitstream is always synchronous under the IEC specifications [4]. Hence, when the SPDIF data are received and formatted back to I2S at the receiver, the resulting I2S signal is synchronous and is capable of functioning with almost most DACs or digital filters. The PLL clock generator selected is the Cirrus Logic CS2000 clock synthesizer. The CS2000 is a flexible clock synthesizer and generator which can work with or independently from a reference input clock. It generates its timing reference from a low jitter source from an internal or external crystal oscillator which will be used to operate the frequency synthesizer [5]. Signals entering and leaving the CS2000 clock generator pass through a low propagation delay buffer at the recommendation of Cirrus Logic for improved stability in operation. The CS2000 has a 12 MHz reference crystal attached to its local oscillator which serves as a low jitter timing reference. The CS8406 from Cirrus Logic was selected as the SPDIF transmitter for this application due to its ability to handle asynchronous I2S bitstreams [6]. The SPDIF transmitter can receive I2S bitstreams up to 192 kHz and convert them to a SPDIF signal. The SPDIF transmission protocol allows for 24-bit uncompressed stereo audio to be transmitted in a single frame alongside additional control bits. A complete set of channel status bits can be reconstructed from 192 frames of audio to form the channel status block, which contains control information about the audio stream such as its sampling rate, bit depth, and additional flags [4]. The digital core requires a master clock signal to function and this master clock is 256 times the base sampling rate [6], which also needs to be synchronous to the word clock. The SPDIF encoder encodes the incoming audio data and mixes in the control bits to form a SPDIF signal encoded with Biphase–Mark encoding (Bi-Ø-M) before it is sent to the driver.

3.1.4. SPDIF Receiver

The SPDIF receiver receives incoming SPDIF signals, extracts the embedded timing and clocking information, and generates a matching I2S bitstream from the received data. The SPDIF receiver was selected based on low jitter and sampling rate support. The master clock produced by the receiver needs to have low jitter to minimize the effects of jitter-induced harmonic distortion at the connected converter [7]. The CS8416 from Cirrus Logic was selected as the SPDIF receiver for this application. The CS8416 performs clock recovery on the incoming SPDIF bitstream to regenerate the master clock and the required bus clocks for the I2S data port. It also decodes the incoming SPDIF bitstream such as when the incoming audio samples are repackaged in the I2S format for the downstream device. The channel status block data from the incoming bitstream are made available as a series of control registers which can be accessed over the I2C control serial port [8]. The CS8416 also contains an 8:1 SPDIF multiplexer which functions as an input selector, allowing seven digital inputs to be selectable as a source to the receiver [8]. The receiver is capable of decoding audio with a sampling rate from 32 kHz to 192 kHz with a word length from 16 to 24 bits. Four digital inputs are available, providing optical, coaxial, and two CMOS-level connections from the Bluetooth and USB boards. The coaxial input is galvanically isolated with a transformer to prevent stray currents from interfering with the digital signals and to prevent ground loops at the receiver and the source. For improved low jitter performance, the PLL section of the receiver is powered by a separate power supply from the digital core and logic. A standalone 12 MHz oscillator is provided for instances when the input source is removed. This allows the receiver to continue to maintain the clocking signals at the I2S port in the absence of a valid digital audio input. The downstream device will continue to receive a valid clock signal which will prevent noise or erratic operation when the PLL goes into an unlocked state. The generated master clock from the CS8416 drives the connected digital filter. The waveform of the signals present at the I2S port for SPDIF source material with a sampling rate of 44.1 kHz from a CD player is presented in Figure 7. The recovered master clock to operate the downstream digital filter or DAC runs at a multiple of 256 times the word clock rate and the bit clock operates at 64 times the word clock rate.

3.1.5. Digital Oversampling Filter

The digital oversampling filter up-samples the incoming audio bitstream by a factor of eight times and performs low-pass filtering in the digital domain. The use of an oversampling filter comes with two main advantages. The process of oversampling involves the scaling of the sampling frequency by a factor of eight by extending each sample by zero padding to retain the original output spectrum [9]. The oversampled signal is used to operate the connected digital-to-analog converters at a higher sampling rate than the base audio sampling rate to allow a lower order analog low-pass filter to be used. For this application, the DF1704 from Texas Instruments was selected as it supports the maximum input sampling rate of 96 kHz at a bit depth of 24 bits. The DF1704 filter is based on a cascade finite-impulse response (FIR) filter with linear phase response. It also converts the incoming I²S bitstream to the EIAJ-RJ format required to operate the connected R2R DACs and applies digital de-emphasis as required for sources encoded with emphasis.

3.1.6. Digital-to-Analog Converter

The output of the digital filters is passed to a pair of DACs which will convert the digital signal to an analog current signal which will be passed to the DAC post-stage, where the current will be converted to a voltage signal and low-pass filtered. To improve the noise performance of the DAC, it is recommended to isolate the high-speed digital circuits such as the SPDIF receiver and digital filter from the DAC which contains an analog section. For this application, the PCM1704 was selected as it meets the specifications for a 24-bit resolution DAC that supports the oversampling rate from its companion digital interpolation filter. It also meets the design specifications and very low noise and distortion performance for high-end audio applications. The selected DAC can operate at an eight times oversampling frequency for audio content with a base sampling rate of up to 96 kHz [10]. The PCM1704 employs a Bi-CMOS sign-magnitude architecture which is used to reduce distortions at the zero crossings and to improve linearity [10]. The selected digital isolator for the DAC section is the ISO7820 capacitive barrier digital isolator from Texas Instruments. The digital isolator has a maximum data rate of 100 Mbps, which is better than the requirements of this application at 24.576 Mbps when the digital filter is operating at the maximum output sampling rate of 768 kHz with a bit clock cycle of 32 bits per sample. Using this method, the digital filter section and the DAC can be isolated to prevent noise coupling [11].

3.2. Analog Section

3.2.1. Transimpedance Amplifier

A transimpedance amplifier is used to convert the current output from the digital-to-analog converter to a voltage output. The necessity of current-to-voltage conversion is needed for DACs that have current outputs. The transimpedance amplifier should transparently convert the output of the DAC to a voltage without affecting the audio or limiting the performance of the DAC. Figure 8 shows the schematic of the transimpedance amplifier using the OPA627 precision operational amplifier from Texas Instrument. The OPA627 was selected for its lower voltage noise density for lower frequencies below 1 kHz and because it has the lowest input bias current of the range shown here. The lower bias current contributes to lower intrinsic noise. The target full-scale voltage from the DAC is rated to be 6 volts peak-to-peak. This translates to an RMS value of 2.12 volts, which fulfils the output requirements of the DAC section. A voltage supply of ±8 volts is sufficient for the op-amp to function for the rated output voltage range, as the specified output signal range on the datasheet of the op-amp has a maximum value of 2.7 to 3.5 volts less than the supply rails. The DAC has a full-scale current output of 2.4 mA peak-to-peak. The resistor (R₁) across the output and the inverting input of the operational amplifier is responsible for the current-to-voltage conversion gain. Equation (1) shows the relationship between the voltage output and the gain resistor [12]. Equation (2) shows the calculated value of R₁ for a defined value of V_out and I_in.

$$V_{out}=I_{in}\times R_1$$

(1)

$$R_1=\frac{V_{out}}{I_{in}}=\frac{{6V}_{pp}}{2.4{mA}_{pp}}=2.5 \mathrm{k}\mathsf{\Omega }$$

(2)

A feedback capacitor (C1) is typically paralleled to the gain resistor in the transimpedance amplifier to provide compensation to prevent oscillations [13]. This is used to maintain the stability of the amplifier. The use of this compensation capacitor in conjunction with the gain resistor will form a first-order low-pass filter with a real pole [13]. It will be necessary to ensure that the bandwidth of this filter does not interfere with the converted audio, so it has minimal impact on the frequency and phase response of the downstream low-pass filter [12]. For this specific DAC operating at the maximum base sampling frequency of 96 kHz, its actual oversampled operating frequency will be 768 kHz when used with the 8X oversampling filter. In this case, the Nyquist frequency after oversampling is half of the new operating frequency at 384 kHz. This determines the minimum required bandwidth for the transimpedance stage. The recommended corner frequency for the transimpedance stage is recommended to be 1.35 MHz for the PCM1704 DAC from Texas Instruments based on the application note [10]. The corner frequency of a low-pass filter is defined as the half-power point, which is the point where the magnitude of the output of the filter decreases by 3 dB when compared with the passband gain. This fulfils the minimum corner frequency requirement for the transimpedance stage such that 384 kHz is within the passband of the transimpedance stage with minimal attenuation. Equation (3) shows how R1 and C1 affect the corner frequency of the transimpedance stage. Equation (4) shows the actual value of C1 calculated for a known corner frequency and value of R1. C1 was selected as 47 pF based on actual physical component values.

$$f_c=\frac{1}{2\pi \left(R_1\right)\left(C_1\right)}=1.35 \mathrm{M}\mathrm{H}\mathrm{z}$$

(3)

$$C_1=\frac{1}{2\pi \left(R_1\right)\left(f_c\right)}=\frac{1}{2\pi \left(2.5k\right)\left(1.35M\right)}\approx 47 \mathrm{p}\mathrm{F}$$

(4)

The precise corner frequency of the transimpedance stage changes slightly and Equation (5) shows the new calculated corner frequency as 1.35451 MHz. This still fulfils the required specifications for cut-off frequency of the transimpedance stage.

$$f_c=\frac{1}{2\pi \left(2.5k\right)\left(47p\right)}=1.35451 \mathrm{M}\mathrm{H}\mathrm{z}$$

(5)

The required gain bandwidth product (GBW) of the op-amp can be found using Equation (6) [12]. The input capacitance of the op-amp can be found using Equation (7) with the differential (C_differntial) and common-mode (C_common-mode) capacitance as provided by the specifications for the selected op-amp [12]. When the input capacitance is calculated in Equation (8), the required gain bandwidth is calculated in Equation (9) and is found to be 1.6427 MHz. The OPA627 has a GBW of 16 MHz, which exceeds this requirement and is suitable for this application.

$${GBW}_{req}=\frac{C_{in}+C_1}{2\pi \left(R_1\right){\left(C_1\right)}^2}$$

(6)

$$C_{in}=C_{source}+C_{differential}+C_{Common-mode}$$

(7)

$$C_{in}=0+8 \mathrm{p}\mathrm{F}+7 \mathrm{p}\mathrm{F}=15 \mathrm{p}\mathrm{F}$$

(8)

$${GBW}_{req}=\frac{15p+47p}{2\pi \left(2.5k\right){\left(47p\right)}^2}=1.6427 \mathrm{M}\mathrm{H}\mathrm{z}$$

(9)

If C_in increases by 20% to account for parasitic or trace capacitance, C_in will yield a value of 18 pF, and the required gain bandwidth extends to 1.873258 MHz, which is still within the GBW of the op-amp. To ensure the transimpedance amplifier is operating in the region of stability, it is necessary to determine to the minimum value of the C₁ to ensure the op-amp does not oscillate and the Barkhausen criteria is not fulfilled. Equation (10) calculated the minimum value of C₁, with a 60% gain bandwidth product of the op-amp taken to factor in manufacturing tolerances [13]. The resulting value as calculated using Equation (11) shows that the minimum value of C₁ is 13.826 pF and the select C₁ of 47 pF is acceptable for stable operation of the amplifier.

$$C_{1,min}=\frac{1}{4\pi \left(R_1\right)\left(0.6\times GBW\right)}(1+\sqrt{1+\left(8\pi R_1{C}_{in}\right(0.6\times GBW\left)\right)})$$

(10)

$$C_{1,min}=\frac{1}{4\pi \left(2.5k\right)\left(0.6\times 16M\right)}\left(1+\sqrt{1+\left(8\pi \left(2.5k\right)\left(15p\right)\left(0.6\times 16M\right)\right)}\right)$$

(11)

The required slew rate of the op-amp can be found using Equation (12). The required slew rate was found to be 25.53 V/µs, which is within the capabilities of the op-amp with a specified slew rate of 55 V/µs.

$${SR}_{required}=(\pi ·V_{pp}·f_c)=(\pi ·6·1.354M)=25.53\mathrm{V}/\mu \mathrm{s}$$

(12)

Noise considerations for the transimpedance amplifier will factor both current and voltage noise sources within the noise model of the op-amp [14]. Current noise modelled at an external current source at the inverting input of an ideal op-amp is amplified by the gain resistor between the output and the inverting input as shown in Figure 9. To reduce the influence of the current noise on the output, R1 should not be excessively large. However, since R1 sets the conversion gain for the amplifier and is mostly predefined for a specific application, choosing an op-amp with low current noise will be beneficial. Equation (13) shows the current noise contribution at the output of the op-amp.

$$i_{nn} Contribution=(R_1·i_n)=(2.5k·2.5\mathrm{f}\mathrm{A}/\sqrt{\mathrm{H}\mathrm{z}})=6.25\mathrm{p}\mathrm{V}/\sqrt{\mathrm{H}\mathrm{z}}$$

(13)

$$e_n Contribution=e_n(1+(2\pi ·R_1·C_{in}·f\left)\right)$$

(14)

$$R_1 Contribution={V_n}^2=4kRT ({\mathrm{V}}^2/\mathrm{H}\mathrm{z})$$

(15)

The resulting noise contribution by the current noise source is minimal from the calculations shown above. The op-amp also has an internal voltage noise source, which experiences a noise gain as shown in Equation (14), that increases with frequency [14]. Minimizing the amount of voltage noise will improve the noise performance of the amplifier. The OPA627 has a low-input voltage noise density at 5.6 nV/√Hz, which is acceptable in this application. R₁ should not be too large in order not to amplify the voltage noise excessively and to minimize resistor thermal noise. The equation for resistor thermal noise is provided in Equation (15), which increases with temperature (T) in Kelvin [15]. K is defined as Boltzmann’s constant in the equation. At lower frequencies, resistor noise will dominate and at higher frequencies, the op-amp internal noise sources will have significant contribution to the output noise [14]. Minimizing the contributions from these noise sources allows for a low-noise design to be realized. Additionally, the grounding for the op-amp should be free from interference since the non-inverting terminal is grounded for the inverting operation. A clean ground source for the analog circuits will avoid the introduction of noise to the non-inverting terminal of the op-amp and compromise the noise performance of the transimpedance stage [11].

3.2.2. Low-Pass Filter

A low-pass filter is used to reconstruct the analog audio from the converted digital audio at the output of the DAC [16]. This filter attenuates spectra content above half the Nyquist rate to smooth the staircase-like pulse amplitude modulated signal to a continuous analog signal [16]. Since the DAC is used concurrently with a digital oversampling filter, the requirements for this analog low-pass filter are less complex [17]. The specifications for the recommended low-pass filter for the PCM704 DAC, based on the Texas Instruments datasheet [11], are provided in

Table 1. Low-pass filter design specifications.

DAC LPF Design Specifications
Passband Gain:	0.0 dB
Cut-off Frequency:	46.8 kHz
Filter Order:	Second-order Butterworth

below.

Considering that the highest base sampling rate of the digital audio signal provided to the digital oversampling filter is 96 kHz, the bandwidth of the reconstructed audio content will have a frequency of up to 48 kHz, which is half of the sampling rate. Despite going through the process of oversampling, the output spectrum contains signals which are already bandlimited to almost half the sampling rate by the digital low-pass filter [17]. Hence, the audio bandwidth of half the base sampling rate continues to apply. The specified cut-off frequency at 46.8 kHz is acceptable in meeting this specification at the fastest sampling rate. A second-order filter would translate to a roll-off of 40 dB per decade. A Butterworth filter is more appropriate in this application as the passband ripples found in a Chebyshev filter are not suitable for audio applications [18]. A Bessel filter will typically need to be of a higher order to meet the similar performance specifications of an equivalent Butterworth filter [18]. A higher order Bessel filter will introduce more phase shift in the audible band, which is undesirable and increases the complexity of the filter design with additional stages added. Additional stages will increase the floor noise of the filter and reduce low noise and distortion performance [19]. The second-order low-pass filter was designed using the multiple feedback (MFB) topology which produces a complex pole pair in the S-plane, which allows more flexible tuning [18]. It also has the highest stopband attenuation of the other filter architectures, making it the most suitable filter for analog signal reconstruction at the output of the DAC. OPA2132 operational amplifier from Texas Instruments was selected since it has low total harmonic distortion and noise value. The OPA2134 has a high slew rate and low bias current, which translates to better transient response and lower shot and flicker noise. Lower current noise density is an important factor when selecting an op-amp for use in a filter as the feedback network contains resistors which can amplify this noise source [19]. A voltage supply of ±8 volts for the transimpedance stage is also used to power the op-amps used in the filter stage. The specified output signal range on the datasheet of the op-amps has a maximum value of 1.2 to 2.5 volts less than the supply rails. The MFB filter is of an inverting nature since it uses the inverting input of the op-amp. For a second-order low-pass filter, only a single stage is necessary [20]. Figure 10 shows the schematic for a typical second-order unity gain low-pass filter with unity gain. The passband gain of the filter is governed by resistors R₁ and R₂ as shown in Equation (16). For a unity gain filter, this gain is set to −1 and R₁ and R₂ will have identical values.

$$A_v=-\frac{R_2}{R_1}=-1$$

(16)

The cut-off frequency is controlled by the two capacitors and the two resistors within the feedback loop as denoted in Equation (17). The transfer function of the filter is given in Equation (18) [20]. It has a quadratic expression in the denominator which can result in a complex pole pair.

$$f_c=\frac{1}{2\pi \sqrt{R_2{R}_3{C}_1{C}_2}}=46.8 \mathrm{k}\mathrm{H}\mathrm{z}$$

(17)

$$Y(s)=\frac{A_0}{(1+a_{1}S+b_1{S}^2)}$$

(18)

Equations (19)–(21) show the relations between the coefficients and the circuit component values as well as the required coefficient values for a second-order Butterworth-type filter with unity gain. These coefficients are also related to the component values of the filter and the actual values of the coefficients may be obtained from a filter design handbook. In this case, values are obtained from “Texas Instruments Op Amps for Everyone Design Reference—Chapter 16” [20]. Coefficient A₀ corresponds to the gain of the filter.

$$A_0=-1$$

(19)

$$a_1=\left(2\pi f_c\right)\left(C_1\right)\left(R_2+{2R}_3\right)=1.4142$$

(20)

$$b_1={\left(2\pi f_c\right)}^2\left(C_1{C}_2\right)\left(R_2{R}_3\right)=1$$

(21)

Design simplifications exist for the MFB topology, and the resistor and capacitor values may be taken as ratios as shown in Equations (22) and (24) [18]. The ratio in turn will establish the Q factor for the filter as found in Equation (30). The quality factor of 0.71 was obtained from the design reference.

$$R_3=m{R}_2$$

(22)

$$C_2=n{C}_1$$

(23)

$$Q=\frac{\sqrt{mn}}{(2m+1)}=0.71$$

(24)

As a criterion for stability, capacitor C₂ must be larger than C₁ by a factor of the coefficients as presented in Equation (25) [20]. In this case, C₂ must be greater than four times the capacitance of C₁ for real values of R₂ and R₃. For this case, C₂ was taken to be 2200 pF and C₁ was taken as 510 pF based on physical component values, with the resulting ratio of 4.3137 between them as shown in Equation (26).

$$C_2>\frac{4b_1(1-A_0)}{{a_1}^2}{C}_1; C_2>4.000076721C_1$$

(25)

$$n=\frac{C_2}{C_1}=\frac{2200p}{510p}=4.313$$

(26)

With the values of the capacitors defined, the value of the resistors can be worked out using Equations (27) and (28). The actual resistance for R2 was found to be 3.852 kΩ and R3 to be 2.526 kΩ. Considering the values of actual practical components, the values were adjusted to 3.83 kΩ and 2.5 kΩ for R2 and R3, respectively. The ratio between the resistors, m, was found to be 0.6527 in Equation (29).

$$R_2=\frac{a_1{C}_1-\sqrt{{a_1}^2{C_2}^2-4b_1{C}_1{C}_2(1-A_0)}}{4\pi f_c{C}_1{C}_2}\approx 3.83\mathrm{k}\mathsf{\Omega }$$

(27)

$$R_3=\frac{b_1}{4{\pi }^2{f_c}^2{C}_1{C}_2{R}_2}\approx 2.5 \mathrm{k}\mathsf{\Omega }$$

(28)

$$m=\frac{R_3}{R_2}=\frac{2.5k}{3.83k}=0.6527$$

(29)

The current Q of the filter can be found by substituting the values of ratios m and n into Equation (24). This yields a quality factor of 0.72784 as shown in Equation (30). The current Q-factor of the filter compares favorably with the defined value of Q of 0.71. Since the component values changed for physically realizable components, the cut-off frequency of the filter will differ from the initial specifications. Equation (31) shows that the current calculated value for the cut-off frequency is 48.5573 kHz, which is acceptable for this application.

$$Q=\frac{\sqrt{\left(0.6527\right)\left(4.3137\right)}}{\left(2\right(0.6527)+1)}=0.72784$$

(30)

$$f_c=\frac{1}{2\pi \sqrt{\left(3830\right)\left(2500\right)\left(510p\right)\left(2200p\right)}}=48.55 \mathrm{k}\mathrm{H}\mathrm{z}$$

(31)

Finally, 1% tolerance film capacitors and 0.1% tolerance film resistors were used for the components in the signal path to minimize the impact of component variance on the performance of the filter.

3.2.3. Headphone Amplifier

A headphone amplifier is used to provide sufficient current drive to low impedance loads such as the transducers in stereo headphones and in-ears. The impedance of such devices can vary, typically from 32 Ω for typical consumer headphones to 400 to 600 Ω for professional studio-grade headphones [21]. To cater to different loading impedances and sensitivities, a switchable gain stage is provided. The power deliver stage of the headphone amplifier will be based on a parallel class AB op-amp architecture to increase the current drive provided by a single op-amp [22]. Class AB amplifiers offer lower distortion with good linearity [23]. A parallel op-amp stage has several advantages, such as lower offset error and lower noise, as opposed to a single high-power op-amp driver [22]. This architecture is also scalable, where more op-amps may be added to meet the desired power rating in the design specifications [22]. The OPA1688 from Texas Instruments was selected for its low distortion performance and high-output drive capability. Each op-amp is configured as a non-inverting buffer and then paralleled with additional op-amps to increase the power output to meet the design specifications.

Figure 11 shows the actual schematic for the headphone amplifier section. The parallel op-amp-based composite amplifier topology has several benefits over a single high-powered amplifier. The DC offset at the output of the amplifier is averaged closer to zero, since having more op-amps in the group will cause the DC offset to average out as the offset is uncorrelated and is usually an error parameter due to manufacturing [22]. Having more paralleled op-amps will also reduce the overall noise floor as noise is a random process and is uncorrelated [24]. By paralleling n number of op-amps to the output, the input noise density for a single op-amp is reduced by a factor of √n. This increases the signal-to-noise ratio of the amplifier. The SNR of a single op-amp can be expressed in Equation (32). S_in refers to signal input power and N_in refers to noise at the input. N_amp refers to noise contributed by the amplifier. If the amplifier is of unity gain and the input noise is negligible, the SNR equation can be simplified to Equation (33).

$$SNR=\frac{{\left(S_{out}\right)}^2}{{\left(N_{out}\right)}^2}=\frac{{(S_{in}\times Gain)}^2}{{(N_{in}\times Gain)}^2+{\left(N_{amp}\right)}^2}$$

(32)

$$SNR=\frac{{\left(S_{out}\right)}^2}{{\left(N_{out}\right)}^2}\approx \frac{{\left(S_{in}\right)}^2}{{\left(N_{amp}\right)}^2}$$

(33)

If two identical op-amps are paralleled, the equation changes to that shown in Equation (34). When two uncorrelated noise sources are added, the resulting noise increases by √2. Equation (35) is a generalized equation for n number of parallel op-amps. For eight parallel op-amps, the theoretical increment in SNR is eight times greater than a single op-amp.

$$SNR\approx \frac{{(2\times S_{in})}^2}{{\sqrt{2}\left(\right(N_{amp})}^2+{\left(N_{amp}\right)}^2)}\approx \frac{{(2\times S_{in})}^2}{{\sqrt{2}\left(2\right(N_{amp})}^2)}$$

(34)

$$NR\approx \frac{{(n\times S_{in})}^2}{{\left(\sqrt{n}{N}_{amp}\right)}^2}\approx \frac{{(n\times S_{in})}^2}{{n\left(N_{amp}\right)}^2}\approx \frac{{n\left(S_{in}\right)}^2}{{\left(N_{amp}\right)}^2}$$

(35)

The outputs of the op-amps are connected to a common output bus using 1 Ω resistor to reduce current flow between the op-amps due to differences in DC-offset. The output to the load passes through a 5 Ω series resistor which is used to limit the overall current output if the output pins on the headphone jack are inadvertently shorted. The resistance of this series current-limiting resistor should be low to prevent power loss. The headphone amplifier also contains a switchable gain stage which utilizes the OPA1612 op-amp and the MAX313 analog switch from Maxim Integrated. The MAX313 was selected for its low resistance and matching resistance between the four channels. It also features low THD and good isolation between the channels. Figure 12 is the schematic for the gain stage. A switchable resistor network at the input of the op-amp allows the gain to be varied in steps under micro-controller control with the use of the analog switch. The gain for the inverting amplifier is given in Equation (36), which depends on the amount of resistance provided between the input source and input node of the op-amp. As more switches are closed, the resistance of at the input node decreases as more resistors are paralleled. Gain is switchable, with 1X, 2X, 4X, and 6X settings.

$$A_v=-\frac{R_1}{R_2//R_3//R_4//R_5}$$

(36)

3.2.4. Preamplifier

The preamplifier board consists of various analog multiplexers to facilitate signal routing, a programmable gain amplifier functioning as an attenuator, and buffers to isolate the various stages. The components used are selected to operate from a ±5-volt supply which will be provided by a complementary pair of voltage regulators from the common 9-volt rail. The negative rail will be supplied by a charge pump before going through the negative linear voltage regulator to minimize switching noise. The 4:1 analog multiplexer is used to switch between four pairs of analog channels from the input section of the preamplifier. One input takes the analog signal from the DAC post-output stage and three additional analog inputs are provided for the user to connect additional analog sources. The Maxim Integrated MAX4582 analog multiplexer was selected for this task owing to its low distortion and crosstalk specifications, which makes it suitable for audio signal routing. High isolation and low crosstalk are important selection criteria for analog multiplexers to maintain signal integrity in the preamplifier section and to prevent signal bleeding between adjacent channels. For a source selector, the multiplexer also has break-before-make switching characteristics which are important for clean transitions between the sources. The output level control of the preamplifier is controlled using the programmable gain amplifier which allows for volume control in 0.5 dB steps. The Texas Instruments PGA2311 was selected for its low distortion and low noise characteristics. It can operate from the existing proposed ±5-volt supply to the preamp board. The PGA2311 also features zero-crossing detection for glitch-free changes in the audio level as the gain change will only occur when the signal transits at the zero-crossing point. The PGA also contains a pair of non-inverting op-amp-based amplifiers at the output which provide adjustable gain and output drive. A pair of 2:1 multiplexers are used to route the output of the PGA to the physical outputs of the preamplifier board. The audio can be sent to a line level output for use with active, speakers, or an external power amplifier. Alternatively, the audio can also be sent to the headphone amplifier board. To minimize noise coupling to the outputs, the multiplexers switches its corresponding output port to the signal from the PGA if activated or shunts the output through a 10 kΩ resistor to ground if deactivated. For this application, the MAX4519, 2:1 dual-channel analog multiplexer from Maxim Integrated was selected. It offers matched on resistance and low on resistance between the two channels in the same package. It offers the usual low-crosstalk and low-distortion characteristic for Hi-Fi applications as well as a consistent impedance over the audible band for uncolored, flat frequency response. The output from each multiplexer passes through a pair of buffers to provide isolation from the upstream preamplifier stage and the downstream connected instruments. It also provides the necessary current drive for driving typical audio lines. The OPA1656 op-amp from Texas Instruments was selected for this purpose due to its low noise and low distortion specifications. It also exhibits good channel separation and low-input bias current. The line output buffer is a pair of non-inverting buffers using a pair of op-amps, powered from the provided ±5-volt rail on the board. For the headphone outputs, a set of inverting buffers were used since the gain stage of the headphone amplifier is also of an inverting nature. This ensures the same output phase polarity when referenced to the input source.

4. Measured Results

Figure 13 contains a photograph of the entire prototype which was measured in this section.

4.1. Combined DAC Post Output Stage

The combined DAC output stage will consist of the previously designed transimpedance amplifier and low-pass filter. Both stages will be coupled together and will be powered from the same ±8-volt dual-rail linear supply to fulfil the power supply requirements for the op-amps at the operating output level. The series of performance measurements were done on the DAC board. A digital source is provided to the input of the SPDIF receiver, and the analog output of the DAC is measured for several quantities. The digital bitstream originates from the Tektronix AM70 digital audio analyzer, which can generate digital audio data that represent an analog sinusoidal signal of varying frequencies and amplitudes. The digital audio signal is received and converted to the analog domain at the DAC board before it passes through the post stage. The frequency response of the DAC and its analog output stage was measured by generating digital audio signals that represent a full scale sinusoidal analog signal within the audible band at discrete points from 20 Hz to 20 kHz. For each point, the analog output of the DAC board is connected to the Keithley 2015 analyzing multi-meter to measure the RMS output. The findings of this test are presented in the graph in Figure 14.

The DAC board was then tested for total harmonic distortion for up to 2nd harmonic, up to 10th harmonic component, as well as THD+N. Test setup remains identical to that used for the frequency response test, with the exception that the Keithley 2015 is measuring the amount of THD present at the output. Three passes of the test were run to collect data for the three difference scenarios. The results are used to plot a series of graphs provided in Figure 15. The THD of the DAC remains under 0.1% across the audible band from the graph for measurements up to the 2nd and 10th harmonic component. It can be observed that the THD+N plot increases in value at higher frequencies due to the increased noise at the output. This trend was also noted from the measurements performed by Burr Brown [2]. It would be possible to obtain a better THD+N performance by minimizing noise sources by the careful routing of all signal and data lines. At 1 kHz, the recorded THD were 0.002% and 0.013% for up to the 2nd and 10th harmonic components.

Additional tests were conducted to determine the signal-to-noise ratio, crosstalk, and channel balance of the analog outputs. The test source for this test would be a digitally generated 1 kHz test tone at the full-scale digital level of 0 dBFS against digital silence. To measure the amount of crosstalk between the channels, the test tone was provided to only the left channel. The RMS voltage was measured at the left and right output to determine the amount of leakage from the active left channel to the silent right channel. The amount of DC offset at the output was determined by measuring the amount of DC voltage present at the outputs in the absence of a digital test tone. Channel balance can be found by presenting the 1 kHz test tone to both channels at a full-scale level and measuring the output at both channels for similarity. The data from the tests are presented in

Table 2. Static measurements for DAC board.

Parameter	Value
DC-Offset	0.000716 V
Channel Balance	±0.00915 dB
Output Level	2.1 Vrms
THD+N (1 kHz)	0.092%
THD (2nd Upper) (Ref to full scale) (1 kHz)	0.002%
THD (10th Upper) (Ref to full scale) (1 kHz)	0.013%
SNR	85.83 dB
Crosstalk	−78 dB
Frequency response	20 Hz–20 kHz (±0.118 dB)

.

The SNR and crosstalk test results perform variably with the measured results of 85.83 dB and −78 dB, respectively. The analog output of the DAC board has a full-scale analog level of 2.1 V_rms. This agrees with the calculated target full-scale output level.

4.2. Headphone Amplifier

For the tests conducted for the headphone amplifier, the circuits were powered from a ±17-volt desktop power supply. Load testing was performed by connecting the appropriate load resistors to the output of the amplifier and determining the maximum output power before clipping by measuring the output RMS voltage before visible distortion occurs to the waveforms. The recorded voltages and power output across the test loads are presented in

Table 3. Power output of headphone amplifier.

Output Power
Load (Ω)	Vrms	Pout (W)
32	8.14	2.07
50	9.12	1.66
100	10.05	1.01
200	10.82	0.585
400	11.52	0.332

.

The measurements for frequency response and THD tests were conducted with a Keithley 2015 distortion analyzing multi-meter under general purpose instrument bus (GPIB) automation with a National Instruments IEEE-488 PCI controller card. The host computer performs automated frequency sweeps to determine the distortion and magnitude of the input signal over the entire audible spectrum from 20 Hz to 20 kHz. Figure 16 contains the plot of the frequency response of the output of the headphone amplifier for an attached load of 32 Ω. The response of the amplifier is mostly flat for the entire audible band, with a variation of approximately ±0.01 dB. A mostly flat and linear frequency response is desirable for high performance audio components to maintain source signal integrity [3].

The THD plot for the headphone amplifier is shown in Figure 17. From the harmonic distortion plot up to the 2nd harmonic component, the data points remain under 0.02% for most of the spectrum. The harmonic distortion plots up to the 10th harmonic component remains at around 0.02% for the most part. The increase in amounts of distortion at lower frequencies could be due to instrument calibration and external sources of interference as the test setup is not exactly ideal. The low amounts of distortion and flat frequency response highlights the advantage of the parallel op-amp architecture for increased bandwidth linearity and reduced distortion and noise, with high output drive capability.

The headphone board was tested for signal-to-noise ratio, inter-channel crosstalk, and output channel matching as a set of static manual measurements using a 1 kHz sinusoidal test source at 2 V_rms. The signal-to-noise ratio test was conducted by sending a test signal at the full-scale level of 2 V_rms and measuring the output of the amplifier. The output level was measured again with the test signal disabled. Inter-channel crosstalk was measured by injecting the test signal into one channel and measuring the amplitude of the output for that channel and the adjacent channel. Channel-matching is performed to determine the difference in output levels between the two channels of the amplifier. The recorded information from the static tests is presented in

Table 4. Static measurements for headphone amplifier.

Parameter	Value
Channel Balance	±0.13051 dB
THD+N (1 kHz)	0.045552%
THD (2nd Upper) (Ref to full scale) (1 kHz)	0.000699%
THD (10th Upper) (Ref to full scale) (1 kHz)	0.01427%
SNR	85.94 dB
Crosstalk	−43.046 dB
Frequency response	20 Hz–20 kHz (±0.01 dB)
Gain levels (1 kHz @ 1 Vrms)	1X—0.839 Vrms (L), 0.83 Vrms(R) 2X—1.68 Vrms (L), 1.644 Vrms(R) 4X—3.36 Vrms (L), 3.24 Vrms(R) 6X—5.13 Vrms (L), 4.74 Vrms(R)

.

The higher crosstalk of −45 dB was noted due to the possibility for a signal to cross-couple with adjacent lines for the prototype circuit on breadboard. This parameter can be improved by carefully routing signal lines such that they do not run too close to each other on a printed circuit board. The time domain waveform for the various gain settings produced with a Tektronix TDS 794C oscilloscope with infinite display persistence is provided in Figure 18.

4.3. Preamplifier

The test and measurement procedure for the preamplifier Veroboard prototype was conducted in a similar fashion to the headphone amplifier board. The frequency response of the preamplifier board was measured by performing a sweep across the audible band with the test source connected to an input of the 4:1 multiplexer and the output measured from the line level output, terminated into a 10 kΩ resistor.

Figure 19 contains the response plot showing a variation of ±0.01 dB across the audible band. The frequency response was noted to be relatively flat throughout the audible band.

The distortion analysis setup is identical to that of the frequency response test, where the results are presented in Figure 20. The distortion analysis shows THD for up to the 2nd harmonic component to be less than 0.02% for most of the audible band and less than 0.04% for harmonic components up to the 10th harmonic component for most of the audible band. It was observed that the distortion rating was higher at the lower frequencies and that can also be attributed to the calibration of the oscillator or the non-ideal test setup. A series of static tests were carried out for the preamplifier board which covers crosstalk between channels and inputs, signal-to-noise ratio, and channel balance. The test signal is a 1 kHz test tone at 2 V_rms, generated from the analog oscillator in the Keithley 2015. The data recorded from the test are presented in

Table 5. Static measurements for preamplifier board.

Parameter	Value
THD (1 kHz) (2nd Upper) (Ref to full scale)	0.0066741%
THD (1 kHz) (10th Upper) (Ref to full scale)	0.034475%
SNR	87.23 dB
Crosstalk (between channels)	−75.8 dB
Crosstalk (between inputs)	−79.29 dB
Channel balance	±0 dB
Frequency response	20 Hz–20 kHz (±0.01 dB)

.

The only additional test performed in this section would be crosstalk between channels tests. For this test, the test source is provided to source channel 1 of the 4:1 input multiplexer and the output of the board is measured when the multiplexer is configured to pass signal from channel 2, with no signal present. It is important to note that channel 2 should be terminated in this case with another line input source, without any signal present at the output. This test gives the amount of signal leakage between the inputs of the 4:1 input multiplexer. The measured signal-to-noise ratio is 87.23 dB. The amount of crosstalk between the channels and inputs is −75.8 dB and −79.29 dB, respectively. Better performance measurements could be obtained by optimizing the test and measurement setup to minimize the influence of external sources of noise and interference. Using a modern audio analyzer with an integrated low-distortion analog oscillator and an integrated digital audio test source can decrease the amount of time to run a set of measurements with greater accuracy over a wider frequency range. Further work involves the integration of the design into a printed circuit board (PCB). The PCB has just been sent for fabrication as of the time of this writing.

5. Conclusions

In summary, our proposed work has introduced an advancement in the domain of high-fidelity audio technology for the implementation of a high-performance audio preamplifier with a digital-to-analog converter (DAC). The digital segment of the system could accommodate audio sources from Universal Serial Bus (USB), Bluetooth, and Sony-Philips Digital interface (SPDIF), thereby granting better flexibility. This achievement is highlighted by the low measured distortion values, with total harmonic distortion plus noise (THD+N) at a mere 0.03%. The system’s exceptional signal-to-noise ratio (SNR) of 87 dB further confirms its capacity to provide a robust audio experience comparable to industry benchmark. This work not only contributes to the theoretical operation of high-fidelity audio but, importantly, bridges the gap between theory and practical results. The measurement results presented are poised to influence and inspire future advancements in HiFi audio technology. Our proposed work represents a good milestone in the ongoing challenge surrounding the advancement of audio fidelity.