A 64-MHz 2.15-µW/MHz On-Chip Relaxation Oscillator with 130-ppm/°C Temperature Coefficient

Abstract

This paper presents a 2.15 µW/MHz at the frequency of 64 MHz relaxation oscillator with a dynamic range of frequency from 47.5 MHz to 80 MHz. To reduce the power consumption and improve energy efficiency, this work employs only one comparator and one capacitor to generate the output clock in comparison with conventional relaxation oscillator structures. A total of 50% ± 5% of the duty cycle is obtained for the output clock by implementing an auxiliary comparator. The proposed relaxation oscillator uses the output voltages of an external low-dropout (LDO) voltage and bandgap reference (BGR) for the required supply and reference voltages, respectively. Two current sources are implemented to provide the required currents for trimming the output frequency and driving the comparators. Measurement results indicate that the relaxation oscillator achieves a temperature coefficient (TC) of 130 ppm/°C over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz under a low-dropout (LDO) voltage of 1.2 V. The proposed relaxation oscillator is analyzed and fabricated in standard 90 nm complementary metal-oxide semiconductor (CMOS) process, and the die area is 130 µm × 90 µm.

1. Introduction

Clock generators are widely used in integrated circuit (IC) design to offer a reference clock from several hertz to tens of gigahertz frequency range. In a radio frequency (RF) transmitter (TX) chain, an up-mixer circuit shifts generated low-frequency (LF) data from a digital-to-analog converter (DAC) to RF and delivers it to a power amplifier (PA) for transmission [1]. On the other hand, at the first stage of a receiver (RX) chain, a low-noise amplifier (LNA) is located to amplify the received signal from the antenna. The signal is shifted from RF to LF through a down-mixer circuit and delivered to a base-band amplifier (BBA) and an analog-to-digital converter (ADC) [2,3]. Phase-locked loops (PLLs) are the most common architectures for generating an RF reference clock [1,4].

To generate LF and high frequency (HF) clocks, the relaxation oscillators are suitable candidates to realize the growing demand for on-chip, low-power, and low-cost clock generators for applications such as the Internet of Things (IoT), wearable devices, wireless network sensors, etc. Crystal oscillators offer ultralow phase noise performances. However, due to the high values of employed inductors and capacitors, the crystal oscillator has to be used as an external component, and it would be a costly product [5]. As a result, crystal oscillators can be replaced by low-cost, low area, and low-power relaxation oscillators for on-chip applications [6]. In Bluetooth low energy (BLE) applications, the potential inaccuracy of the oscillator causes the receiver to be activated for a guard time before the actual beacon. Thus, to ensure reliable reception when operating slave sensor nodes in connection modes, the high temperature accuracy of the clock generator is required, especially for low-duty cycle signals [7]. Nano-watt power consumption clock generators are proposed in [7,8,9]. Nevertheless, the target frequencies do not exceed tens of kilohertz. Although the reported works [10,11,12] provide high stable output frequency of tens of megahertz clock generators, the circuits consume huge amounts of power.

In [12], a relaxation oscillator with using frequency-error feedback loop in a 5 nm fin field-effect transistor (FinFET) process is proposed. However, the design consumes a large power consumption of 840 µW at the target frequency of 77 MHz. In [13], to minimize power consumption and sensitivity to temperature variation, simplified logic control circuits are used by employing an improved delay compensation technique. However, the structure and performance level of the design should be improved to accommodate higher frequencies. The reported oscillator in [14] uses matching between capacitors and transistors to suppress process and temperature variations. However, a high energy efficiency of 408 µW/MHz is achieved.

Supply voltage variations have effects on voltage swings and comparator bandwidth. On the other hand, current sources use reference voltages to provide a constant current for wide temperature variations. Therefore, the generated current could be changed by reference voltage variations, where these variations affect the behavior of comparators and the charge time of capacitors. A low dropout (LDO) can minimize supply voltage variations and the required reference voltages over a wide temperature variations could be offered by a bandgap reference (BGR) [15]. In this work, an external LDO and BGR are employed to provide the required voltages 1.2 V, 900 mV, respectively.

The proposed relaxation oscillator in this paper offers 2.15 µW/MHz of energy efficiency at 64 MHz by using a single comparator structure to generate the output clock in comparison with conventional structures [7,8,9,13,16]. The organization of this paper is as follows: Section 2 discusses the proposed relaxation oscillator; Section 3 presents the hysteresis comparator operation in circuit level; and Section 4 discusses the programmable current source. The experimental results are shown in Section 5.

2. Overall Structure of the Proposed Relaxation Oscillator

The proposed relaxation oscillator includes two hysteresis comparators (Comp.1 and Comp.2) and two current sources (Cur.Gen.1 and Cur.Gen.2), as indicated in Figure 1.

Comp.1 and Comp.2 are implemented to generate the output frequency and compensate for the duty cycle, respectively. Cur.Gen.1 provides a programmable DC current to charge the capacitor (C). Cur.Gen.2 is employed to offer the required current to drive Comp.1 and Comp.2.

In the design of relaxation oscillators, employing two or more comparators to generate the output clock could increase the power consumption. Moreover, the mismatch between comparators and capacitors could be increased at the layout level when the number of them is more than one. Therefore, to improve the energy efficiency and minimize the mismatch in this work, only one comparator (Comp.1) and one capacitor (C) are employed to generate clock frequency in comparison to conventional structures [7,8,9,13,16].

Figure 2 illustrates the timing diagram of the positive input and output of Comp.1, Node.1 and Node.2, respectively, when the negative input of Comp.1 is connected to the reference voltage of $V_{\mathrm{REF}1}$.

As emphasized in Figure 2, the output voltage of Comp.1 would be described in two scenarios. (1) Whereas the voltage level of the positive input of a non-inverting comparator is 0 V, the output of the comparator follows its positive input; hence, the voltage of Node.2 is GND. In this scenario, when the output voltage of Comp.1 is GND, the transistors MN0 and MN1 operate as open circuit switches; therefore, the capacitor (C) is charged by $I_2=I_0$ through MP0 till its voltage meets the sum of $V_{\mathrm{REF}1}$ and the up threshold voltage of Comp.1 ($V_{\mathrm{HYS}1+}$), as shown in Figure 1. The capacitor (C) would be charged with a linear slope by an ideal current source. However, due to the output impedance of Cur.Gen.1, the slope of $V_{\mathrm{c}}$ is not linear, as shown in Figure 2. The charge time of the capacitor (C) is written by following expressions:

$$I=C\frac{dV}{dt}$$

(1)

$$t_{\mathrm{ch}}=\frac{C}{I}\left(V_{\mathrm{c}}\right)$$

(2)

where

$$V_{\mathrm{c}}=V_{\mathrm{REF}1}+V_{\mathrm{HYS}1+}$$

(3)

(2) In the second scenario, when the voltage level of the capacitor (C) (Node.1) is equal or greater than $V_{\mathrm{REF}1}+V_{\mathrm{HYS}1+}$, the output voltage of Comp.1 is switched to VDD. On this transition, the transistor MP0 operates as an open circuit switch and the transistors MN0 and MN1 are in triode region. The transistor MN0 discharges the stored charge on the capacitor (C). The current of the transistor MN0 can be expressed by the following equation:

$$I_{\mathrm{disch}}=-\frac{V_{\mathrm{C}}}{R_{\mathrm{ON},\mathrm{MN}0}}{e}^{-\frac{t}{\tau }}$$

(4)

where $R_{\mathrm{ON},\mathrm{MN}0}$ and $\tau$ are given by the following expressions, respectively:

$$R_{\mathrm{ON},M\mathrm{N}0}=\frac{1}{{\mu }_{\mathrm{n}}{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{\mathrm{MN}0}\left(V_{\mathrm{GS},\mathrm{MN}0}-V_{\mathrm{TH},\mathrm{n}}\right)}$$

(5)

$$\tau =R_{\mathrm{ON},\mathrm{MN}0}\times C$$

(6)

thus, the discharge time could be given by:

$$t_{\mathrm{disch}}=5\times \tau$$

(7)

To satisfy Kirchhoff’s current low (KCL), during the discharge time, the transistor MN1 operates in the triode region and $I_0$ is connected the ground via the transistor MN1 ($I_1=I_0$). The capacitor (C) is discharging and the output voltage of Comp.1 switches to GND when the voltage level at the Node.1 is equal or less than $V_{\mathrm{REF}1}$ minus the down threshold voltage of Comp.1 ($V_{\mathrm{HYS}1-}$). Furthermore, as shown in Figure 2, the switching delay of Comp.1 and the transistors MN0 and MP0 generate a non-negligible delay ($t_{\mathrm{d}}$) that must be taken into account. Because both transistors MN0 and MP0 are in the off region during the delay ($t_{\mathrm{d}}$), the capacitor (C) does not charge immediately. The capacitor (C) resumes charging when the transistors MN0 and MP0 operate in cut-off and triode regions, respectively. Thereby, the period (T) of the oscillator can be defined by the following expression:

$$T=\frac{C}{I}\left(V_{\mathrm{REF}1}+V_{\mathrm{HYS}1+}\right)+5\left(R_{\mathrm{ON},\mathrm{MN}0}\times C\right)+t_{\mathrm{d}}$$

(8)

then:

$$f=\frac{1}{T}$$

(9)

In Equation (8), $C$,$V_{\mathrm{REF}1}$, $R_{\mathrm{ON},\mathrm{MN}0}$, and $t_{\mathrm{d}}$ have constant values. Hence, the operating frequency of the oscillator could be reconfigurable by employing a programmable current source to generate $I$.

As indicated in Figure 2, the frequency of the oscillator is defined by Comp.1, nonetheless, the duty cycle of the generated clock could not reach 50%, due to the fast discharge of the capacitor (C). Therefore, an auxiliary comparator (Comp.2) is employed to compensate for the required duty cycle of the output clock. It is noteworthy that Comp.2 has no contribution to the charge and discharge of the capacitor (C). Thus, the auxiliary comparator (Comp.2) does not change the period (T).

Figure 3 shows the timing diagram of the positive input and output of Comp.2, Node.1, and OSC_CKL, respectively. The operation of Comp.2 is the same as that of Comp.1, where the reference voltage of Comp.2 ($V_{\mathrm{REF}2}$) is lower than the reference of Comp.1 ($V_{\mathrm{REF}1}$) for duty cycle compensation, as stated in Figure 3. Because the signal at Node.1 is independent of the output of Comp.2, by selecting a lower reference voltage ($V_{\mathrm{REF}2}$) for Comp.2, the duty cycle could be compensated. The operation of Comp.2 follows two conditions: (1) When the voltage level of the positive is equal to or greater than $V_{\mathrm{REF}2}+V_{\mathrm{HYS}2+}$, the output of Comp.2 is VDD, and (2) while it is equal to or lower than $V_{\mathrm{REF}2}-V_{\mathrm{HYS}2-}$, the output voltage is 0 V. As shown in Figure 3, the duty cycle of the output clock could be reconfigurable by selecting different values of the reference voltage ($V_{\mathrm{REF}2}$), $V_{\mathrm{HYS}2+}$, and $V_{\mathrm{HYS}2-}$.

3. Hysteresis Comparator

A hysteresis comparator is one of the most common circuits for generating clocks in the LF and HF ranges. A comparator-based oscillators provide better temperature coefficient (TC) in comparison with an inverter-based oscillators due to the better temperature dependent behavior of comparators [17]. Different up ($V_{\mathrm{HYS}+}$) and down ($V_{\mathrm{HYS}-}$) threshold voltages can be provided by a hysteresis comparator. The loop characteristics of the output voltage of a non-inverting comparator is indicated in Figure 2. A non-inverting comparator operates as follows: when the voltage level of the positive input ($V_{\mathrm{IN}}$) is lower than voltage of the negative input minus the different down threshold voltage ($V_{\mathrm{INB}}-V_{\mathrm{HYS}-}$), the output voltage is GND, and it is VDD when the voltage of the positive input is greater than the sum of the negative input and down threshold voltage ($V_{\mathrm{INB}}+V_{\mathrm{HYS}+}$) [18,19], as illustrated in Figure 4. Therefore, when the negative input is connected to a reference voltage ($V_{\mathrm{REF}}$), the output voltage of the non-inverting hysteresis comparator would be reported as follows:

$$\{\begin{array}{c}{V}_{\mathrm{I}N}<V_{\mathrm{REF}}-V_{\mathrm{HYS}-}; V_{\mathrm{OUT}}=GND\\ V_{\mathrm{IN}}>V_{\mathrm{REF}}+V_{\mathrm{HYS}+}; V_{\mathrm{OUT}}=VDD\end{array}$$

(10)

Figure 5 indicates the schematic of the employed hysteresis comparator in this work. $a$ is defined by the size ratios of transistors MP2 and MP3, where it is greater than 1 and generates the $V_{\mathrm{HYS}+}$. On the other hand, $b$ is greater than 1 as well; it is described by the size ratio of transistors MP4 and MP5 to create $V_{\mathrm{HYS}-}$. Thereby, the values of $V_{\mathrm{HYS}+}$ and $V_{\mathrm{HYS}-}$ can be calculated [18,19]:

$$V_{\mathrm{HYS}+}=\sqrt{\frac{2I_{\mathrm{bias}}}{\mu C_{\mathrm{ox}}{\left(\raisebox{1ex}{$W$}\!\left/ \!\raisebox{-1ex}{$L$}\right.\right)}_{\mathrm{MN}4,5}}}\times \frac{\sqrt{a}-1}{\sqrt{a+1}}$$

(11)

$$V_{\mathrm{HYS}-}=\sqrt{\frac{2I_{\mathrm{bias}}}{\mu C_{\mathrm{ox}}{\left(\raisebox{1ex}{$W$}\!\left/ \!\raisebox{-1ex}{$L$}\right.\right)}_{\mathrm{MN}4,5}}}\times \frac{\sqrt{b}-1}{\sqrt{b+1}}$$

(12)

where ${\left(W/L\right)}_{\mathrm{MN}4,5}$ is the size of transistors $M{N}_4$ and $M{N}_5$. When the input voltage remains within the up ($V_{\mathrm{HYS}+}$) and down ($V_{\mathrm{HYS}-}$) threshold voltages, the output retains memory of its state, as stated in Figure 4. It is worth noting that the voltage level at the input has to exceed the up ($V_{\mathrm{HYS}+}$) threshold voltage to switch the output voltage from GND to VDD. In the other case, the voltage level of the input has to be driven below the down ($V_{\mathrm{HYS}-}$) threshold voltage to switch the output voltage from VDD to GND.

4. Programmable Current Source

As discussed in the overall architecture section, the value of the capacitor (C) has a direct effect on the period (T) and frequency of the oscillator. Moreover, in the SoC design, parasitic capacitors due to metals and transistors are inevitable, although the parasitic capacitors can be minimized in layout. Nevertheless, the minimized parasitic capacitors should be extracted and added to the capacitor (C). Figure 6 indicates the structure of the programmable current source which is implemented to eliminate variable parasitic capacitors due to the operation of transistors in ON or OFF regions. The current of $I_0$ is controllable by 5-bit TRIM<4:0>. The current source provides a reconfigurable of DC current from 9.6 µA to 18.4 µA for the lowest and highest operation by 32 steps with 275 nA resolution to control the frequency. Therefore, the current of $I_0$ can is given by the following expression:

$$I_0=2\times I_{\mathrm{REF}}+N\times {I_0}^{\prime }$$

(13)

5. Experimental Results

The proposed fully integrated relaxation oscillator is analyzed and implemented in a 90 nm complementary metal-oxide semiconductor (CMOS) process with an active area of 0.0117 ${\mathrm{mm}}^2$. Figure 7a illustrates the location of Cur.Gen.1, Cur.Gen.2, Comp.1, Comp.2, and the capacitor (C) in the top layout of the implemented relaxation oscillator. Figure 7b shows the device under test (DUT) for measurement. The required supply and reference voltages are offered by external LDO and BGR, respectively, to measure the output clock of the oscillator. The relaxation oscillator consumes 115 µA of current at the frequency of 64 MHz. The post-layout simulation results of the internal (Node.1 and Node.2) and output clock signals of the oscillator are depicted in Figure 8. The duty cycle of 47% is achieved in the presented paper by employing the auxiliary comparator. Monte-Carlo simulation presents an estimation of the behavior of the circuit for process corner variations. Figure 9 illustrates the simulated Monte-Carlo results of the proposed relaxation oscillator for global and local mismatch process errors, where the standard derivation of 2.56 MHz is obtained for 100 samples. Figure 10a indicates measurement results of the oscillator where an overall dynamic range of 32.5 MHz from 47.5 MHz to 80 MHz with a resolution of 1 MHz is achieved. Measurement results illustrates a TC of 130 ppm/°C is obtained over a wide temperature range from −25 °C to 135 °C at the frequency of 64 MHz, as depicted in Figure 10b.

Although there are a variety of figures of merit (FoMs) to compare the performances of oscillators, the suggested FoM in [20] generally includes all important parameters of an oscillator, such as frequency-to-power ratio, temperature range ($\Delta T$), feature size of technology ($L_{\min }$), TC, and occupied area. Therefore, the FoM could be written using the following equations [20]:

$$\mathrm{FoM}=10\log \left(\frac{f_{\mathrm{osc}}\left(\mathrm{Hz}\right)\times \Delta T\times L_{\min }^2\left(\mathrm{nm}\right)}{P\left(W\right)\times TC\times A\left({\mathrm{mm}}^2\right)}\right)$$

(14)

Table 1. State-of-the-art performance summary and comparison.

Parameter	This Work †	[12] †	[13] †	[16] †	[17] †	[20] †	[21] ‡
Tech. (nm)	90	5	180	180	180	130	180
Approach	Relaxation oscillator	Relaxation oscillator	Relaxation oscillator	Switched capacitor	Inverter-based RC	Relaxation oscillator	CDS-like
Supply (V)	1.2	1.2	1.1–2	1.2	1.8	2.5	1.8
Freq. (MHz)	64	77	1.02	13.4	18.13	1	10
Power (µW)	138	840	5.72	157.8	245.7	428	91.44
Energy Efficiency (µW/MHz)	2.15	10.9	5.6	11.77	13.55	428	9.14
Temp. Range (°C)	−25–135	−40–125	−40–125	−20–100	N.A.	25–200	N.A.
Temp. Coeff. (ppm/°C)	130	36.36	59	193.15	N.A.	108	20.8
Area (mm2)	0.0117	0.0077	0.0513 *	0.039 *	0.056	0.007	N.A.
FoM (dB)	175.96	151.3	175	166.4	N.A.	160	N.A.

^† Measurement results, ^‡ Post-layout simulation results, * Estimated area occupation from die photo.

reports the performance summary of the proposed relaxation oscillator and compares it with other state-of-the-art designs. As indicated in Table 1, the oscillator presented in this work has a superior energy efficiency of 2.15 µW/MHz and a FoM of 175.96 dB in comparison with other similar works. The relaxation oscillator in [12] reports a higher operating frequency clock with a lower TC in a smaller occupied area. Nonetheless, the huge power consumption degrades the energy efficiency and FoM performances significantly in comparison to other oscillators. The oscillator reported in [13] consumes less power and offers a better TC; however, due to the lower operating frequency, the energy efficiency performance and FoM are degraded.

The relaxation oscillator in [20] provides an output clock frequency for high-temperature applications up to 200 °C with the smallest occupied area in comparison with other oscillators in Table 1. However, the oscillator dissipates a huge amount of power and offers the worst energy efficiency performance in comparison with other works. The CDS-like oscillator in [21] presents a superior TC of 20.8 ppm/°C in comparison with other works. Nevertheless, the post-layout simulation results show a greater amount of energy efficiency in comparison with the proposed oscillator in this paper and [12,13].

The operation frequency and power consumption define the energy efficiency performance of an oscillator. Moreover, both power consumption and operating frequency have the largest contributions to FoM performance. Consequently, a structure with a high operation frequency and low power consumption could provide better energy efficiency and FoM performances. Energy efficiency and FoM performances are significantly improved by using a single comparator to generate the output clock.

6. Conclusions

In this article, the fully integrated relaxation oscillator is analyzed and implemented in 90 nm CMOS process with a die area of 130 µm × 90 µm. The energy efficiency of 2.15 µW/MHz is obtained to generate the output clock of 64 MHz, whereas the TC of 130 ppm/°C is achieved for a wide temperature range from −25 °C to 135 °C. The superior energy efficiency and FoM performances are achieved by using a single comparator structure to generate the output clock. According to the measurement results, the oscillator offers a dynamic frequency range of 47.5 MHz to 80 MHz with a resolution of 1 MHz by 32 steps. Moreover, the duty cycle of the output clock is compensated for 50% ± 5% by employing an auxiliary comparator.