A Fast Interface Circuit for the Measurement of 10 Ω to 1 GΩ Resistance

Abstract

In this work, an interface circuit applied to resistive gas or chemical sensors is proposed. The interface circuit includes a detection front-end, a single-end to differential circuit, a successive approximation analog-to-digital converter (SAR ADC), and some reference auxiliary circuits. In detection front-end circuits, mirrored currents in a current mirror usually differ by several orders of magnitude. In order to ensure that the current mirror can be copied accurately, this work uses a negative feedback structure consisting of an operational amplifier and an NMOS tube to ensure that the ${\mathrm{V}}_{\mathrm{DS}}$ of the current mirroring tube remains consistent. Simulation results show that the replication error of the current mirror is 0.015%. The proposed interface circuit has a detection range of 10 $\Omega$ to 1 G$\Omega$ with a relative error of 0.55%. The current multiplication or divided technique allows the interface circuit to have a high sampling frequency of up to 10 kHz. The proposed circuit is based on a 180 nm CMOS process with a chip area of 0.308 ${\mathrm{mm}}^2$ (723 $\mathsf{\mu }$m ∗ 426 $\mathsf{\mu }$m). The power consumption of the whole interface circuit is 3.66 mW when the power supply voltage is 1.8 V.

1. Introduction

Gas or chemical sensors are used in a wide range of applications for the detection of hazardous gases [1,2,3]. For example, ${\mathrm{H}}^2$, CO, NO, ${\mathrm{NO}}_2$, and ${\mathrm{CH}}_4$ are often used in industry or new energy vehicles. ${\mathrm{H}}^2$ and ${\mathrm{CH}}_4$ are prone to explosions. CO and ${\mathrm{NO}}_2$ are extremely dangerous to humans and can even lead to death. Usually these gas sensors have a large variation in resistance when detecting gases, sometimes by several orders of magnitude [4,5,6,7,8]. Therefore, an interface circuit with a fast response time needs to be designed, and it needs to be able to measure a relatively large range of resistance variations [9,10,11,12,13].

Some common methods of measuring a wide range of resistances are shown in [14,15,16,17,18,19,20,21,22,23,24,25,26,27]. Reference [16] presents a resistance to frequency (RTF) circuit. The circuit consists of operational amplifiers, diodes, capacitors, and resistors. The advantage of this circuit is its simple construction and high measurement accuracy of 0.1%. However, the measurement range is only 950–2950 $\Omega$, and the measurement time takes 0.1241 s. Reference [17] proposes a method using a fixed current flowing through the measured resistance. The resistance of a resistor can be obtained by measuring the voltage difference across the resistor. The proposed method has a power consumption of 32 µW and a measurement speed of 1.83 kHz. However, the measurement range is limited to 10 K$\Omega$ to 9 M$\Omega$, and the relative error of the measurement is 1.32%. Reference [18] presents a circuit structure for measuring a wide range of resistances by means of an inverter, comparator, and integrator. It has a measurement range from 1 $\Omega$ to 500 M$\Omega$ (from 4.11 MHz to 145 Hz), and the measurement accuracy is less than 1%. As for the RTF method, its advantage is that its structure is simple because the digital output can be determined without an ADC [25,26,27]. However, this method often requires a relatively long measurement time when measuring a relatively large resistance, and it requires a subsequent processing circuit capable of processing a relatively high-speed digital processing circuit when detecting a small resistance.

References [22,23,24] propose a method for the measurement of a wide range of resistances using a current mirror and a capacitor. The method converts resistance into current by applying a fixed voltage across the resistor. The current is copied through a current mirror, and the copied current flows into a capacitor. By measuring the voltage across this capacitor, the resistance value can be obtained. Due to the copy error of the current mirror and the limited gain of the operational amplifier, it is difficult to maintain a measurement error of less than 1% with a resistance variation range of ${10}^8$ [24]. If we want to measure a resistance with a range of ${10}^8$ variations and require an error of less than 1%, then we need a 34-bit ADC (${\log }_2\left({10}^{10}\right)$ = 33.2). This is very difficult. In this work, by dividing the measurement range into three sections and measuring them separately, the difficulty of the ADC design is reduced. At the time of measurement, an error measurement of less than one thousandth can be determined through a 10-bit ADC. In this work, a high gain rail-to-rail operational amplifier is also designed to enable high gain at different reference voltages and reduce the error caused by the limited gain of the operational amplifier. Similarly, a high precision current mirror can also reduce the measurement error of the resistor.

The rest of the paper is organized as follows: Section 2 presents the overall architectural design and error analysis. Section 3 describes the specific implementation of the main circuit. Section 4 shows the results of the simulation. Finally, conclusions are given in Section 5.

2. Solutions for the Interface Circuits

2.1. The Overall Structure

Figure 1 shows the overall architectural design of the proposed circuit. The design as a whole consists of a detection front-end, a single-ended to differential circuit, an analogue-to-digital conversion circuit (ADC), and external PC or FPGA.

The conversion of resistance ${\mathrm{R}}_{\mathrm{S}}$ into current ${\mathrm{I}}_{\mathrm{S}}$ is achieved through a negative feedback structure consisting of an NM tube and an operational amplifier in the detection front-end. The current ${\mathrm{I}}_{\mathrm{S}}$ changes the current into $\frac{\mathrm{n}}{\mathrm{m}}{\mathrm{I}}_{\mathrm{S}}$ through the P-MOS current mirror, and charges the capacitor ${\mathrm{C}}_{\mathrm{S}}$ with the obtained current $\frac{\mathrm{n}}{\mathrm{m}}{\mathrm{I}}_{\mathrm{S}}$, where m is the number of ${\mathrm{PM}}_1$ pipes, and n is the number of ${\mathrm{PM}}_2$ pipes when MODE = 001. The values of m and n in other modes are similar. In this way, the resistance ${\mathrm{R}}_{\mathrm{S}}$ value to be measured is converted into a time-dependent voltage value. The obtained voltage is then given to the single-ended to differential circuit. The main purpose of the single-ended to differential circuit is to convert the single-ended signal from the detection front-end into a differential signal. It also amplifies this signal and increases its driving capability. Finally, the obtained analog signal is converted into a digital signal through a 10 bit SAR ADC. In this paper, a redundant design is used in order to increase the sampling rate and the number of valid bits of the ADC. The data after quantization by the ADC can be processed by an external FPGA or PC and the control signal fed back to the P-MOS mirror.

2.2. Detection of the Front-End

Figure 2 shows the circuit diagram of the detection front-end. A measurement range of ${10}^8$ is achieved by a reasonable setting of m, n, and the reference voltage. For example, when the resistance value is small, such as ${\mathrm{R}}_{\mathrm{S}}$ = 100 $\Omega$, we can set m = 100, n = 1, and ${\mathrm{V}}_{\mathrm{REF}}$ = 10 mV. To improve the accuracy and speed of the measured resistance value, an internal integrated capacitor design solution is used. The capacitance value ${\mathrm{C}}_{\mathrm{S}}$ is 50 pF. The maximum time required for measurement over the entire detection range is 100 $\mathsf{\mu }$s. Details are shown in

Table 1. Detection of front-end mode settings.

MODE	m	n	${\mathbf{V}}_{\mathbf{REF}}$ (mV)	$\mathbf{MIN}{\mathbf{R}}_{\mathbf{S}}$ ($\mathbf{\Omega }$)	$\mathbf{MAX}{\mathbf{R}}_{\mathbf{S}}$ ($\mathbf{\Omega }$)	$\mathbf{MAX}\mathbf{TIME}$ ($\mathsf{\mu }$s)
001	100	1	10	10	1 k	100
010	1	1	100	1 k	1 M	100
100	1	100	1000	1 M	1 G	100

.

A high gain operational amplifier ensures that the voltage applied to ${\mathrm{R}}_{\mathrm{S}}$ remains constant. In order to have an effective accuracy of 0.1%, Equation (1) gives the required gain of the operational amplifier. The corresponding small signal model is shown in Figure 3. According to the calculations, the gain of this design is greater than 60 dB, where ${\mathrm{g}}_{\mathrm{NM}}$ is the trans-conductance of the NM tube, ${\mathrm{A}}_{\mathrm{o}}$ is the open loop gain of the operational amplifier, and ${\mathrm{V}}_{\mathrm{RS}}$ is the terminal voltage of the resistor ${\mathrm{R}}_{\mathrm{S}}$ to be measured.

$$\frac{V_{RS}}{V_{REF}}=\frac{g_{NM}{R}_S{A}_o}{1+g_{NM}{R}_S{A}_o}$$

(1)

2.3. Single-Ended to Differential Circuits

Figure 4 shows the schematic diagram for single-ended to differential (STD) conversion. To minimize the effect on the input signal, the input is connected directly to the gate. To reduce the effect of ADC kickback noise, a strong drive capability is required for the single-ended to differential circuit. The operational amplifier in this design has a swing rate of 7 V/$\mathsf{\mu }$s. This allows the output signal can recover within a 1/2 ADC quantization cycle.

The relationship between the input signal and the output signal is shown in Equation (2), where ${\mathrm{R}}_1$ is equal to ${\mathrm{R}}_2$. Assuming that the slope of the output signal is $\beta$, it can be derived that the magnitude of the measured resistance can be represented by Equation (3).

$$V_{OP}-V_{ON}=2V_{CM}-2V_{IN}$$

(2)

$$R_S=-\frac{2n{V}_{REF}}{km{C}_S}$$

(3)

2.4. System Error Analysis

The main errors in the system circuit are the system random noise, the misalignment error of operational amplifiers, and the mismatch error of the tube in the current mirror. The error of the detection front-end is mainly composed of the offset error of the operational amplifier and the mismatch error of the current mirror tube, both of which are fixed. We use $\Delta n$ and $\Delta V_{REF}$ to represent the errors caused by the current mirror tube and the op-amp, respectively. Figure 5 shows a single-ended to differential (STD) circuit with offset and noise, where ${\mathrm{V}}_{\mathrm{O}1}$ and ${\mathrm{V}}_{\mathrm{O}2}$ are the fixed misalignment of the two op-amps, and ${\mathrm{V}}_{\mathrm{O}3}$ is the equivalent to the white noise of the system to the output.

Equation (4) is the relationship between output and input when noise and system mismatch are considered. It can be seen that ${\mathrm{V}}_{\mathrm{O}1}$ and ${\mathrm{V}}_{\mathrm{O}2}$ do not affect the slope of the output voltage. The error caused by ${\mathrm{V}}_{\mathrm{O}3}$ can be eliminated by subsequent mean filtering. Therefore, in the single-ended to differential circuit, the error is mainly related to the mismatch $\Delta R$ of the resistors ${\mathrm{R}}_1$ and ${\mathrm{R}}_2$. Equation (5) shows the resistance ${\mathrm{R}}_{\mathrm{S}}$ values obtained after considering noise and mismatch. Since $\Delta R$, $\Delta n$, and $\Delta V_{REF}$ exhibit a fixed proportional deviation relative to ${\mathrm{R}}_1$/${\mathrm{R}}_2$, $\mathrm{n}$, and ${\mathrm{V}}_{\mathrm{REF}}$, they can be represented by a unified coefficient $\beta$.

$$V_{OP}-V_{ON}=((V_{CM}+V_{O1})-(V_{IN}+V_{O2}))(2+\Delta R)+V_{O3}$$

(4)

$$R_S=-\frac{(2+\Delta R)(n+\Delta n)(V_{REF}+\Delta V_{REF})}{km{C}_S}=-\beta \frac{2n{V}_{REF}}{km{C}_S}$$

(5)

For the non-linearity of the operational amplifier in the detection front-end, since the operational amplifier is a closed loop and the loop has a finite gain, the size of the NM tube can be reasonably designed to ensure that the operational amplifier works in the linear region. For the non-linearity of the operational amplifier in the single-ended to differential circuit, there will be large non-linearity when the output is near VDD or VSS. In the subsequent FPGA or PC processing, the non-linearity influence of the operational amplifier can be reduced by reasonably selecting the output range.

3. Circuit Implementation

Figure 1 shows the framework of the overall circuit design. Some of the main circuit design details are presented in this section. This part mainly includes a high-gain rail-to-rail operational amplifier design, a high-precision current mirror design, and a 10-bit asynchronous SAR ADC design. Considering the influence of random noise to be eliminated later, multiple measurements will be made on one ${\mathrm{R}}_{\mathrm{S}}$. It is required that the ADC can work at a higher frequency. Therefore, in this work, the design of an asynchronous SAR ADC is adopted.

3.1. Rail-To-Rail Operational Amplifiers

In order for the operational amplifier in the detection front-end to operate properly at different ${\mathrm{V}}_{\mathrm{REF}}$ and have the same gain, the operational amplifier needs to be designed rail to rail. Figure 6 shows the circuit diagram of the proposed rail-to-rail operational amplifier. The input stage is a folded common source and common gate structure with complementary differential pairs. An additional current supplement channel ensures that the operational amplifier can maintain the same gain over different common-mode input ranges. The output stage uses a feedback class AB output structure to achieve the full swing output voltage. To ensure the operational amplifier stability, the Miller compensation capacitor ${\mathrm{C}}_{\mathrm{C}}$ is added.

Equation (6) gives the expression for the trans-conductance at the input when the common-mode voltage is half of VDD. Equation (7) gives the expression when the common-mode voltage is close to VSS. When the common-mode voltage is close to VDD, the expression for transconductance is similar to that when the common-mode voltage is close to VSS (Equation (8)), where ${\mathrm{I}}_1$ and ${\mathrm{I}}_2$ are the sum of the currents flowing through input tubes ${\mathrm{NM}}_5$ and ${\mathrm{NM}}_6$ and the sum of the currents flowing through ${\mathrm{PM}}_5$ and ${\mathrm{PM}}_6$, respectively. ${\mathrm{g}}_{\mathrm{m}}$, ${\mathrm{g}}_{\mathrm{mn}}$, and ${\mathrm{g}}_{\mathrm{mp}}$ are the total input transconductance, the transductance of input tubes ${\mathrm{NM}}_5$ and ${\mathrm{NM}}_6$, and the transductance of input tubes ${\mathrm{PM}}_5$ and ${\mathrm{PM}}_6$, respectively. W and L are the width and length of the input tube. If the transconductance of the input tube is the same in both cases, ${\mathrm{I}}_2$ in Equation (7) should be four times the corresponding ${\mathrm{I}}_2$ in Equation (6). In this design, this is achieved by a 1:3 current mirror. When the common-mode voltage is low, the input transistors ${\mathrm{NM}}_5$ and ${\mathrm{NM}}_6$ are turned off, and the current flowing through ${\mathrm{NM}}_4$ will be the same as the current flowing through ${\mathrm{PM}}_2$. Since ${\mathrm{PM}}_2$ and ${\mathrm{PM}}_1$ form a current mirror, the current flowing through ${\mathrm{PM}}_1$ is three times that of ${\mathrm{PM}}_4$. At this time, the current ${\mathrm{I}}_2$ is the sum of the currents flowing through ${\mathrm{PM}}_1$ and ${\mathrm{PM}}_4$, which is 4 times that in the case of Equation (6). In order to determine the self-bias of ${\mathrm{PM}}_7$, ${\mathrm{PM}}_8$, ${\mathrm{NM}}_7$, and ${\mathrm{NM}}_8$ as well as the drive bias of output tubes ${\mathrm{PM}}_{15}$ and ${\mathrm{NM}}_{15}$, ${\mathrm{PM}}_{11}$, ${\mathrm{PM}}_{12}$, ${\mathrm{NM}}_{11}$, and ${\mathrm{NM}}_{12}$ are added in the first stage of the operational amplifier [28].

$${\mathrm{g}}_{\mathrm{m}}={\mathrm{g}}_{\mathrm{mn}}+{\mathrm{g}}_{\mathrm{mp}}=\sqrt{{\mathrm{I}}_1{\mathsf{\mu }}_{\mathrm{n}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{n}}}+\sqrt{{\mathrm{I}}_2{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{p}}}$$

(6)

$${\mathrm{g}}_{\mathrm{m}}={\mathrm{g}}_{\mathrm{mp}}=\sqrt{{\mathrm{I}}_2{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{p}}}$$

(7)

$${\mathrm{g}}_{\mathrm{m}}={\mathrm{g}}_{\mathrm{mn}}=\sqrt{{\mathrm{I}}_1{\mathsf{\mu }}_{\mathrm{p}}{\mathrm{C}}_{\mathrm{ox}}{\left(\frac{\mathrm{W}}{\mathrm{L}}\right)}_{\mathrm{n}}}$$

(8)

Figure 7 shows the gain and phase margin simulation of the rail-to-rail operational amplifier. The simulation results show that the gain of the operational amplifier under different process angles exceeds 96.9 dB, and the phase margin exceeds 65 degrees. In the analysis of the second section, the open-loop gain of the operational amplifier is greater than 60 dB, so the designed rail-to-rail operational amplifier meets the requirements. The supply voltage of the operational amplifier is 1.8 V, and the load is 4 pF. The value of the Miller compensation capacitor ${\mathrm{C}}_{\mathrm{C}}$ is 1 pF.

The simulation results of the voltage error of ${\mathrm{V}}_{\mathrm{RS}}$ are shown in Figure 8. It can be concluded that, in the measurement range from 10 $\Omega$ to 1 G$\Omega$, the maximum value of the relative error of ${\mathrm{V}}_{\mathrm{RS}}$ at different process angles is less than 0.06%. The relative error is calculated by Equation (9).

$$RelativeError=\frac{V_{RS}-\overline{V_{RS}}}{\overline{V_{RS}}}\ast 100\%$$

(9)

3.2. High Precision Current Mirror

The current mirror is realized through the PMOS tube. Equation (10) shows that the mismatch of the current is mainly affected by the threshold voltage mismatch and the channel modulation effect. Generally speaking, the larger the L of the MOS tube is, the smaller the mismatch caused by the threshold voltage is. Therefore, when the L value is large enough, the effect of threshold voltage mismatch can be ignored. The trench modulation effect is mainly affected by ${\mathrm{V}}_{\mathrm{DS}}$. Figure 9a shows a traditional high-precision current mirror, which has a limited ability to suppress different ${\mathrm{V}}_{\mathrm{DS}}$ values and reduces the range of the variation in ${\mathrm{V}}_1$. Figure 9b shows an improved high-precision current mirror with a folded common-source common-gate high-gain operational amplifier to make the ${\mathrm{V}}_{\mathrm{DS}}$ as consistent as possible. In the simulation results, the error value of ${\mathrm{V}}_{\mathrm{DS}}$ is less than 1 mv in the whole measurement range. The voltage ${\mathrm{V}}_3$ in the proposed improved current mirror can have a larger voltage variation range due to the lack of a PMOS transistor voltage drop. Due to the smaller parasitic gate capacitance, the response speed of the circuit is faster than the traditional high-precision current mirror [29,30].

$$\frac{I_2}{I_1}=\frac{W_2{L}_1}{W_1{L}_2}{\left(\frac{V_{GS}-V_{TH2}}{V_{GS}-V_{TH1}}\right)}^2\left(\frac{1+\lambda V_{DS2}}{1+\lambda V_{DS1}}\right)$$

(10)

Figure 10 shows the simulation results of the current mirror error at different process angles when the resistance value is 1 G$\Omega$ at an ff process angle, and the maximum error is 0.69%. In all other cases, the relative error is less than 0.015%. The relative error is calculated by Equation (11), where ${\mathrm{I}}_{\mathrm{RS}}$ is the current to be measured, and ${\mathrm{I}}_{\mathrm{M}}$ is the current generated by the current mirror.

$$RelativeError=\frac{\frac{n}{m}{I}_{RS}-I_M}{I_M}\ast 100\%$$

(11)

3.3. Asynchronous SAR ADC

In order to convert the output analog signal to a digital signal, an analog-to-digital converter (ADC) with 10-bit effective bits was designed. The system requires high speed and ADC accuracy, so the asynchronous SAR ADC architecture was used [31,32]. Figure 11a shows the design of the redundant part, and Figure 11b illustrates the control relationship of the main parts of the SAR ADC in detail. An asynchronous clock module was used to generate the high-speed asynchronous clock required by the ADC. The ADC result output module was used to save and output the result of the comparator comparison. A switch control module generates switches to control the DAC based on the result of the comparison.

In the selection of the SAR ADC unit capacitance, the value of the unit capacitance needs to meet the requirements of random thermal noise and process mismatch. The corresponding minimum unit capacitance requirements are given in Equation (12) and (13), respectively. Generally speaking, the larger the capacitance, the greater the load on the entire circuit and the greater the power consumption. Therefore, the value of the unit capacitance cannot be too large. LSB is the minimum unit of ADC quantization, and N is the design number of bits of the ADC. KT is the thermal noise constant. ${\mathrm{C}}_0$ is the unit capacitance, and ${\sigma }_0$ is the standard deviation of the unit capacitance. In this design, considering the superior matching of MOM capacitors, the unit capacitance was generated by custom-made MOM capacitors. In this work, the selected unit capacitance ${\mathrm{C}}_0$ is 3 fF.

$$\frac{1}{2}\mathrm{LSB}>\sqrt{\frac{2\mathrm{KT}}{2^{(\mathrm{N}-1)}{\mathrm{C}}_0}}$$

(12)

$$\frac{{\sigma }_0}{C_0}<\frac{1}{3}{\left(\frac{1}{2}\right)}^{(1+\frac{3N}{4})}$$

(13)

During the quantization conversion process of the SAR ADC, the result of the SAR ADC quantization is wrong due to the possibility of miscalculation by the comparator. These cannot be remedied in a non-redundant ADC design, which reduces the number of valid ADC bits. A redundant design can somewhat minimize the loss of accuracy due to SAR ADC quantization errors. A redundant design also relaxes the requirements for the accuracy and bandwidth of reference voltage establishment, which in turn allows faster asynchronous clocks to be used.

Table 2. Redundant design solutions for SAR ADCs.

ADC Output	Actual Weighting	Redundant Range (LSB)	Weight Allocation Scheme
11	480	64	−32
10	256	32	+0
9	128	32	+16
8	72	16	+8
7	40	8	+0
6	20	8	+4
5	12	4	+0
4	6	4	+2
3	4	2	+0
2	2	2	+2
1	2	0	+0
0	1	0	+0

shows the binary-scaled recombination (BSR) algorithm used in this paper. A single quantization requires 12 quantization cycles with a maximum redundancy of 64 LSBs. BSR has the advantage of simple subsequent digital circuit processing and does not introduce detuning in the capacitor array.

Among the parts of the SAR ADC, the comparator consumes the most power. In this work, a fully dynamic comparator design was used to reduce the power consumption of the SAR ADC. The schematic diagram of the proposed fully dynamic comparator is shown in Figure 12. The proposed fully dynamic comparator also reduces the kickback noise during comparison. When CLK is low, the comparator is in the reset state, and N and P are pulled high. When CLK is high, the comparator is in the compare state. Since there is a difference between VIN and VIP voltages, the N and P point voltages drop at different rates. The latch latches the result of the comparison. The exact process of the voltage change is shown in Figure 13.

The dynamic simulation results of the proposed SAR ADC are shown in

Table 3. Simulation results of the ADC at different process angles.

	tt	ss	ff
technology (nm)	180
resolution (bit)	10
sampling rate (MS/s)	25
SFDR (dB)	69.59	70.98	70.37
SNR (dB)	53.18	53.27	53.22
ENOB (bits)	9.86	9.87	9.87

. With a sampling rate of 25 MS/s and a voltage of 1.8V, the effective number of bits of the SAR ADC at different process angles is 9.8. SFDR and SNR were 69.59 dB and 53.18 dB, respectively.

4. Simulation Results

Figure 14 shows the overall layout of the proposed interface circuit. Figure 15 shows the architectural diagram of the interface circuitry corresponding to the layout. Under the standard process of 180 nm, the area of the chip is 0.308 ${\mathrm{mm}}^2$ (723 $\mathsf{\mu }$m ∗ 426 $\mathsf{\mu }$m) (without a pad). The power dissipation for the analog output and digital output are 1.35 mW and 3.66 mW, respectively, in the case of a supply voltage of 1.8 V. The layout mainly includes the detection front-end, the single-ended to differential circuit, the ADC section, and the reference circuit. The reference circuit is added mainly to be able to provide a reference inside the chip to improve the stability of the system.

The external port of the chip is shown in Figure 16. Since the corresponding reference circuit has been provided inside the chip, it is only necessary to provide power pins, sensor pins to be measured, and output digital pins outside the chip.

The SAR ADC consumes the most power in the chip. The main power consumption of the SAR ADC is generated by the charging and discharging of the capacitor when the clock is flipped. Therefore, the power consumption can be reduced by controlling the clock of the ADC. As shown in Figure 1, CLK-ADC is the control clock of the SAR ADC. When CLK-S is high, the system is reset and the output is 0. CLK-ADC is always low, and the ADC does not operate. When CLK-S is low, the switch is disconnected, the capacitor CS starts to integrate, and the CLK-ADC clock starts to flip. The simulation results are shown in Figure 17. ADC-OUT is the result after conversion by the ideal DAC. The introduction of the CLK-ADC clock reduces the power consumption of the SAR ADC component by 20%.

Figure 18 shows the relative error values of the proposed interface circuit when measuring 10 $\Omega$ to 1 G$\Omega$ resistors. It can be seen that the relative error of the proposed circuit is less than 0.55% over the entire measurement range. The large error in measuring smaller resistances is mainly caused by the large deviation between the theoretical and actual values of the bias voltage ${\mathrm{V}}_{\mathrm{REF}}$. In the subsequent processing, this error can be reduced by imposing a fixed value to fix the adjustment. In the detection front-end, the power consumption is higher when the detection resistance ${\mathrm{R}}_{\mathrm{S}}$ is smaller. When the measured resistance ${\mathrm{R}}_{\mathrm{S}}$ value is 10 $\Omega$, the current flowing is 1 mA. If measured resistance ${\mathrm{R}}_{\mathrm{S}}$ value is 1 $\Omega$, the current flowing of 10 mA is required and the current mirror needs to occupy a large area. Usually for gas or chemical sensors, the resistance ${\mathrm{R}}_{\mathrm{S}}$ value is larger than 1 $\Omega$. The relative error is calculated by Equation (14), where ${\mathrm{R}}_{\mathrm{S}}$ is the actual resistance value, and ${\mathrm{R}}_{\mathrm{SM}}$ is the measured resistance value.

$$RelativeError=\frac{R_S-R_{SM}}{R_S}\ast 100\%$$

(14)

The power consumption of the proposed interface circuit is 3.66 mW at a 1.8 V supply. Figure 19 shows the power consumption occupied by each part separately. The SAR ADC consumes the most power with 58%. The power consumption of the detection front-end, the single-conversion differential circuit, and the reference circuit occupy 15%, 19% and 5%, respectively. The other parts are buffer circuits and clock circuits, which account for 3%. Figure 20 shows the power consumption percentage of each part of the SAR ADC. The dynamic comparator consumes the most power with a percentage of 46%. Asynchronous logic and DAC consume 27% and 6% of the power, respectively. The others are the clock circuit and buffer circuit, whose power consumption is 21%.

Table 4. Comparison with state-of-the-art works (with method types).

Paper	This Work	[5]	[13]	[22]	[10]	[18]	[27]	[12]
Year	2023	2011	2020	2007	2006	2019	2017	2010
Type	controlled integrator	integrator	RTC	Oscillator	RTC	RTC	PWM integrator	RTC
CMOS Process (nm)	180	350	PCB	350	PCB	180	180	PCB
area (mm${}^2$)	0.59	2.6505	NA	0.35	NA	0.996	0.64	NA
Supply voltage (V)	1.8	2.7	NA	3.3	5/12	1.8	1.8	NA
measurement range ($\Omega$)	10–1 G	500–1 M	4.5 k–5 k	1 k –1 G	4.7 k–3 G	1–500 M	80–2 M	10 k–100 G
Relative Error (%)	0.55	<3	NA	0.8	0.5	1	<1.5	<10
power consumption (mW)	1.35/3.66	NA/6.6	NA	NA/15	600	NA/35	1.8/NA	NA
Read-out time (ms)	0.1	NA	10	10000	2952	6.9	0.8	10

summarizes the performance of the proposed interface circuit compared with other advanced interface circuits. The proposed circuit can measure a larger dynamic range of resistance up to ${10}^8$ compared to other literature in the comparison, and the proposed circuit can measure a smaller minimum resistance down to 10 $\Omega$. In terms of relative error, the proposed circuit has a maximum error of 0.55% in the measurement range. In References [10,22,24], the readout time varies greatly when measuring different resistance values. When the resistance ${\mathrm{R}}_{\mathrm{S}}$ is small, the readout time is small, on the order of microseconds. When the resistance is very large, the measurement time can reach the second level. The proposed interface circuit has little variation in the measurement time when measuring different resistance values. The proposed interface circuit ensures a maximum measurement time of 0.1 ms through a three-stage design and internal integrated capacitors. Furthermore, in order to further reduce the noise error of the system and to reduce the relative error of the measured resistance, the average value of 128 measurements is taken in one measurement in the digital processing section.

5. Conclusions

Gas or chemical sensors have a wide range of applications. Most gas or chemical sensors show large changes in resistance during detection, often by several orders of magnitude. Gas sensors usually exist in an array, which can improve the accuracy of detecting the same gas or detect multiple different gases at the same time. Therefore, the interface circuit needs to have a relatively fast measurement speed. This work presents a fast interface circuit for measuring resistance values. In the design of the current mirror, the clamp effect of the operational amplifier can make the ${\mathrm{V}}_{\mathrm{DS}}$ of the current mirror consistent within the load range variation and ensure the replication accuracy of the current mirror. The influence of the system’s fixed deviation and white noise on the measurement results can be reduced by differencing the output digital values and averaging the values obtained multiple times. The interface circuit achieves a maximum measurement time of 0.1 ms in the resistance measurement range of 10–1 G$\Omega$, with a relative error of 0.55%. Compared with other detection methods, the proposed method has a larger measurement range and fast measurement speed. The interface circuit is implemented by a 180 nm process with a power consumption of 3.66 mW at a supply voltage of 1.8 V.