Investigation of Trap Density Effect in Gate-All-Around Field Effect Transistors Using the Finite Element Method

Abstract

Trap density refers to the density of electronic trap states within dielectric materials that can capture and release charge carriers (electrons or holes) in a semiconductor channel, affecting the transistor’s performance. This study aims to investigate the influence of trap density on the electrothermal behavior of nanowire gate-all-around GAAFET devices. The numerical solution of Poisson’s equations and continuity equations, coupled with the heat conduction model, has been used to predict the temperature inside the GAAFET device. The finite element method has been used to discretize the semiconductor equations. Investigations have been carried out on a number of physical and geometric parameters, such as oxide thickness, nanowire radius, and gate length. Their effects on output characteristics and device temperature have been discussed. A thinner oxide thickness, lower device radius, and longer channel length led to a higher current flow. Results also reveal that high trap densities can have significant impacts on the degradation of electronic devices, particularly in the context of semiconductor devices like transistors.

1. Introduction

In search of higher device performance and lower power consumption, new structures such as FinFETs [1] and Pi-gate [2], tri-gate [3], Omega-gated [4], and gate-all-around (GAA) MOSFETs [5] have been reported [6,7]. GAAFET structures are seen as the near-term future of integrated circuits as they provide highly electrostatic gate control [8]. GAAFET transistors have a gate-all-around structure, where the gate surrounds the semiconductor channel. This structure demonstrates an enhancement in gate control that reduces SCEs, with lower leakage currents and operational voltages [9,10,11]. This results in improved performance and reduced power consumption. A comparative electrothermal study of GAAFETs and FinFETs has been proposed by Zhao et al. [12]. A higher I_on current and a lower I_off current are obtained for the GAAFET structure at V_d = 0.7 V and V_d = 0.05 V. The electric properties, including transfer characteristics, output characteristics, gain, mobility roll-off, subthreshold slope, and drain-induced barrier lowering (DIBL), in GAAFET structures have been analyzed by Mohan et al. [13]. The selection of adequate gate material and architecture has been proposed by several authors to improve the device’s performance [14,15,16,17,18]. The various technology nodes and their limitations have been presented by Narula et al. [19] (

Table 1. Node issues and solutions of the different technologies.

Node	Best Device	Issue	Solution
<0.1 µm	Bulk MOSFET	SCE, low drive current	- Strained SiGe - Metal gate - High-k dielectric
0.1 µm–32 µm	SOI MOSFET	Power leakage current	- Ultra-thin body SOI MOSFET
32 µm–10 nm	FinFET	SCE are prominent	- Use of multi-gate material - Stacked oxide
<10 nm	GAA	Power, cost	- Vertically stacked GAA - Work function engineering - High–k dielectric

). A comparative study by Kumar et al. [20] reveals that the GS-GAA structure shows the most improved results. However, the thermal resistance of GAAFETs [21] compared with planar transistors [22,23] and FinFETs [24,25,26,27] shows that GAAFETs have significantly higher thermal resistance (Figure 1). This parameter has a direct influence on the device performance and overall functionality.

This effect is mainly due to the intensive scaling down of field-effect transistors. As a result, this higher thermal resistance could induce many issues that cause degradation of device performance, including a tunnel effect, increased power consumption, and excess heat production [28,29,30,31,32,33]. When the oxide SiO₂ is scaled down, gate current leakage occurs as a result of carriers being able to tunnel through the gate dielectric [34]. Therefore, since SiO₂ is inappropriate for nanodevices, the use of high-k materials is essential for overcoming the limitations of SiO₂, which faces challenges in maintaining sufficient gate control in modern nanoscale transistors. In our previous work [35], we have compared the behavior of several high-k materials such as HfO₂, ZrO₂,La₂O₃, and Al₂O₃. We have shown that Al₂O₃ as a substitute produces significant reductions in thermal effects and can be used as a potential candidate in transistor devices. While high-k materials offer advantages in improving device performance, they tend to have higher trap densities compared to SiO₂. The presence of traps in the dielectric can lead to charge trapping, affecting the overall charge control in the transistor channel. In fact, the traps are defined as energy levels in the bandgap of the semiconductor. These traps can capture and release charge carriers. This phenomenon can cause several reliability problems that affect the device’s electrical and thermal characteristics. When trapped carriers are later released back into the channel, it leads to a change in the device’s threshold voltage and electrical characteristics. For that reason, it is crucial to account for trap density and its effects in order to accurately model and simulate the electrothermal behavior of GAAFET devices.

Device designers and researchers often use advanced simulation techniques, which include trap models, to study the impact of traps on a device’s performance under different operating conditions [36,37,38,39]. The effects of interface trap charges (ITCs) on doping-less NW-based devices were addressed for the first time by Kumar et al. [40]. The proposed device performed better in the presence of positive ITCs. The influence of interface traps on the I–V characteristics of InAs-nanowire-FETs and MOSFETs has been investigated by Pala et al. [41]. They demonstrated that traps have a significant impact on subthreshold slopes and that even a single trap can deteriorate the subthreshold reverse-slope of an InAs nanowire.

The simulation of nanoscale devices is computationally intensive due to the fine mesh needed to accurately capture the intricacies of small-scale structures. Several mesh-free methods have been developed to solve physical and engineering problems [42,43,44,45,46]. The finite element method has gained extensive attention due to its ability to solve partial differential equations for difficult problems with irregular geometries [47,48]. This method is based on the discretization of partial differential equations (PDEs) [49], which describe space-and-time-dependent physical problems. The solution of the equation is an approach to the real solution. Previously, we analyzed the self-heating effect in GAAFETs [50] using the finite element method. The finite element discretization has been used to tackle the effect of Joule heating in a conductive-bridge random-access memory (CBRAM) for the single-phase-lag heat conduction model [51].

This paper aims to contribute to the investigation of the trap density effect on the electro-thermal behavior of GAAFETs. High-k dielectric Al₂O₃ has been used as the gate dielectric, and the finite element method has been used for modeling semiconductor equations, coupled with the heat conduction model. The device’s structure and the numerical method are developed in Section 2. The results are discussed in Section 3. In Section 4, the conclusions of this work are presented.

2. Device Structure and Simulation Approach

2.1. Device Structure and Flow Process

Figure 2a shows the entire 3D GAAFET structure. Between the two outer gates, a thin oxide layer Al₂O₃ surrounds the silicon channel region. The fabrication processes of the GAAFET structure are illustrated in Figure 2b. More details about the process flow is reported with [52]. A 2D axial-symmetry schematic cross-sectional view of the structure is seen in Figure 2c.

As the 3D structure presents an axial symmetry around the z-axis, a 2D axial-symmetry structure is considered in this work. The supply voltage to the device is 0.5 V and the oxide thickness is 2 nm. The source/drain doping concentration is 1 × 10¹⁷ cm⁻³, the channel doping is 1 × 10²⁰ cm⁻³, the device radius, R, is 5 nm, and the length of the gate, L_g, is 100 nm.

Table 2. Physical and thermal parameters.

Materials	λ (Wm−3K−1)	C (MJm−3K−1)	ε
Si	150	15	11.8
Al2O3	35	2.89	10

displays other physical and thermal parameters.

• For the semiconductor equations, as boundary conditions, a constant electrostatic potential equal to V_d is applied at the drain contact and a potential equal to V_G at the gate contact n = n₀, p = p₀, and φ = V₀ at the source and drain regions, and ∇n = ∇p = ∇φ = 0 at the other boundary sides.
• For the heat conduction equation, we suppose that the devices are completely isolated. The right side, as well as the top and bottom boundaries in the GAAFET, are assumed to be adiabatic (∇T = 0). A Dirichlet boundary condition (T₀ = 300 K) is adopted at the gate, implicitly assuming that the heat rapidly dissipates in metallic contacts.
• A symmetric boundary is used at the symmetry axis for the electrothermal simulation.

2.2. Model Description

Semiconductor equations are based on Poisson’s equation and the continuity equation of electrons and holes. The main equations are expressed as follows:

$${\nabla }^{2}V=-\frac{q}{\epsilon }\left(p-n+N_D^{+}-N_A^{-}\right)$$

(1)

$$\nabla .J_p+q\frac{\partial p}{\partial t}=-q{R}_p$$

(2)

$$\nabla .J_n-q\frac{\partial n}{\partial t}=q{R}_n$$

(3)

$$\mathrm{C}\frac{\partial T}{\partial t}=\nabla \left(\mathsf{\lambda }\nabla \mathrm{T}\right)+\mathrm{H}$$

(4)

where [V, J_n, J_p] are determined from auxiliary equations:

$$\overrightarrow{E}=-\nabla V$$

(5)

$${\overrightarrow{J}}_p=q(p{\overrightarrow{\nu }}_p-D_p\nabla p)$$

(6)

$${\overrightarrow{J}}_n=-q(n{\overrightarrow{\nu }}_n-D_n\nabla n)$$

(7)

$$H=\overrightarrow{J}·\overrightarrow{E}$$

(8)

The parameter descriptions are illustrated in

Table 3. Parameters description.

Parameters	Description
V	Voltage
q	Electron charge
Ε	Semiconductor permittivity
p	Hole concentration
n	Electron concentration
T	Temperature
C	Volumetric heat capacity
λ	Thermal conductivity
H	Heat source
Jn,p	Electron and hole current densities
Dn,p	Electron and hole diffusion coefficients
$\overrightarrow{\nu }$n,p	Electron and hole drift velocities

.

Spatial discretization of the semiconductor Equations (1)–(3) and heat conduction Equation (4) is carried out by the finite element method. The principle of the finite element method is to approximate an unknown to an expression with a shape function; an appropriate function interpolates the solution at the mesh nodes between the discrete values, and a function Ψ can be approximated by:

$$\psi \left(r,t\right)=\varphi \left(r\right){\times \Psi }_i\left(t\right)$$

(9)

where Ψi is the value of Ψ at the nodes i, and ϕ(r) is the line vector of the shape functions, which is given by:

$${\varphi }_{\mathrm{i}}\left(r\right)=\prod _{j\ne i}\frac{r-r_j}{r_i-r_j}$$

(10)

The disruption of the function is defined by:

$$\delta \psi \left(r\right)={\varphi }^T\left(r\right){\delta \psi }_i^T$$

(11)

where T is the transposed.

For a rectangular element with eight nodes, the desired function, ϕ, is interpolated by a quadratic polynomial (Figure 1), which depends on the variables x and y.

$$\Psi (x,y)={\mathrm{C}}_1+{\mathrm{C}}_{2}x+{\mathrm{C}}_{3}y+{\mathrm{C}}_4{x}^2+{\mathrm{C}}_{5}xy+{\mathrm{C}}_6{y}^2+{\mathrm{C}}_7{x}^{2}y+{\mathrm{C}}_{8}x{y}^2$$

(12)

$${\varphi }_1(x,y)=(1-x)(1-y)(1-2y-2x)$$

(13)

$${\varphi }_2(x,y)=(1-x)(1-y)(1-2y-2x)$$

(14)

In our case, the approximation of the function, Φ = [V, p, n, T], can be expanded in terms of the shape function into:

$$\Phi \left(r,t\right)=\sum _{\mathrm{i}=1}^{\mathrm{N}}{\Phi }_i\left(t\right){\varphi }_i\left(r\right)$$

(15)

We introduced a shape function, ϕ_j, in the disturbance of the unknown function Φ, expressed as follows:

$${\varphi }_j=\delta \Phi \left(t,r\right)=\sum _{\mathrm{i}=1}^{\mathrm{N}}{\left(\delta {\Phi }_i^e\left(t\right)\right)}^{T_r}{\left({\varphi }_i\left(r\right)\right)}^{T_r}$$

(16)

where T_r is the transpose matrix. The function distribution Φ(r) inside an element dΩ is an interpolation between its nodal.

The integral form is obtained by multiplying (1–3) by ϕ_j and integrating over Ω, the region occupied by the device. After applying the divergence theorem, we find:

$$\underset{\mathsf{\Omega }}{\int }\nabla {\varphi }_j\left[\epsilon \overrightarrow{\nabla }V\right]\partial \mathsf{\Omega }-\underset{\mathsf{\Omega }}{\int }{\varphi }_j\left[q\left(p-n+N_A-N_D\right)\right]\partial \mathsf{\Omega }=\underset{\mathsf{\Gamma }}{\int }{\varphi }_j\left[\epsilon \overrightarrow{\nabla }V\right]\partial \mathsf{\Gamma }$$

(17)

$$\underset{\mathsf{\Omega }}{\int }{\varphi }_j\left[\frac{\partial p}{\partial t}\right]\partial \mathsf{\Omega }+\underset{\mathsf{\Omega }}{\int }{\nabla \varphi }_j\left[D_p\overrightarrow{\nabla }p-p\overrightarrow{{\mathsf{\nu }}_p}\right]\partial \mathsf{\Omega }+\underset{\mathsf{\Omega }}{\int }{\varphi }_j\left[R_p\right]\partial \mathsf{\Omega }=\underset{\mathsf{\Gamma }}{\int }{\varphi }_j\left[D_p\overrightarrow{\nabla }p-p\overrightarrow{{\mathsf{\nu }}_p}\right]\partial \mathsf{\Gamma }$$

(18)

$$\underset{\mathsf{\Omega }}{\int }{\varphi }_j\left[\frac{\partial n}{\partial t}\right]\partial \mathsf{\Omega }-\underset{\mathsf{\Omega }}{\int }{\nabla \varphi }_j\left[D_n\overrightarrow{\nabla }n+n\overrightarrow{{\mathsf{\nu }}_{\mathrm{n}}}\right]\partial \mathsf{\Omega }+\underset{\mathsf{\Omega }}{\int }{\varphi }_j\left[R_n\right]\partial \mathsf{\Omega }=-\underset{\mathsf{\Gamma }}{\int }{\varphi }_j\left[D_n\overrightarrow{\nabla }n+n\overrightarrow{{\mathsf{\nu }}_n}\right]\partial \mathsf{\Gamma }$$

(19)

The left terms of Equations (17)–(19) represent the boundary conditions which make the integrals over Γ vanish. After development, using Equation (4), the system of Equation (1) can be written as:

$$\underset{\mathsf{\Omega }}{\int }\nabla {\mathsf{\varphi }}_{\mathrm{j}}\left[\mathsf{\epsilon }\overrightarrow{\nabla }\left(\sum _{\mathrm{i}=1}^{\mathrm{N}}{\mathrm{V}}_{\mathrm{i}}\left(\mathrm{t}\right){\mathsf{\varphi }}_{\mathrm{i}}\left(\mathrm{r}\right)\right)\right]\partial \mathsf{\Omega }-\underset{\mathsf{\Omega }}{\int }{\mathsf{\varphi }}_{\mathrm{j}}\left[\mathrm{q}\left(\left(\sum _{\mathrm{i}=1}^{\mathrm{N}}{\mathrm{p}}_{\mathrm{i}}\left(\mathrm{t}\right){\mathsf{\varphi }}_{\mathrm{i}}\left(\mathrm{r}\right)\right)-\left(\sum _{\mathrm{i}=1}^{\mathrm{N}}{\mathrm{n}}_{\mathrm{i}}\left(\mathrm{t}\right){\mathsf{\varphi }}_{\mathrm{i}}\left(\mathrm{r}\right)\right)+{\mathrm{N}}_{\mathrm{A}}-{\mathrm{N}}_{\mathrm{D}}\right)\right]\partial \mathsf{\Omega }=\underset{\mathsf{\Gamma }}{\int }{\mathsf{\varphi }}_{\mathrm{j}}\left[\mathsf{\epsilon }\overrightarrow{\nabla }\left(\sum _{\mathrm{i}=1}^{\mathrm{N}}{\mathrm{V}}_{\mathrm{i}}\left(\mathrm{t}\right){\mathsf{\varphi }}_{\mathrm{i}}\left(\mathrm{r}\right)\right)\right]\partial \mathsf{\Gamma }$$

(20)

Similar developments of Equations (2) and (3) give the following equation:

$$\sum _{\mathrm{i}=1}^{\mathrm{N}}\mathsf{\alpha }{\mathrm{M}}_{\mathrm{i}\mathrm{j}}{\dot{\mathsf{\Phi }}}_{\mathrm{i}}+\left(\mathsf{\beta }{\mathrm{K}}_{\mathrm{i}\mathrm{j}}+\mathsf{\gamma }{\mathrm{L}}_{\mathrm{i}\mathrm{j}}\right){\mathsf{\Phi }}_{\mathrm{i}}+{\mathrm{F}}_{\mathrm{j}}=0$$

(21)

where:

$$M_{ij}=\underset{\mathsf{\Omega }}{\int }{\varphi }_i{\varphi }_j\partial \mathsf{\Omega }$$

(22)

$$L_{ij}=\underset{\mathsf{\Omega }}{\int }{\varphi }_i{\nabla \varphi }_j\partial \mathsf{\Omega }$$

(23)

$$K_{ij}=\underset{\mathsf{\Omega }}{\int }{\nabla \varphi }_i{\nabla \varphi }_j\partial \mathsf{\Omega }$$

(24)

$$F_j=\underset{\mathsf{\Gamma }}{\int }{\delta }_{\Phi }{\varphi }_j\partial \mathsf{\Gamma }$$

(25)

$$\alpha =\left(\begin{array}{c}0\\ 1\\ 1\\ C\end{array}\right),\beta =\left(\begin{array}{c}0\\ D_p\\ -D_n\\ \lambda \end{array}\right),\gamma =\left(\begin{array}{c}0\\ -1\\ -1\\ 0\end{array}\right), and {\delta }_{\Phi }=\left(\begin{array}{c}q/\epsilon (N_D-N_A)\\ R\\ R\\ -H\end{array}\right)$$

(26)

After assembling the elementary matrices, we obtain the global matrix form:

$$\left[\mathrm{M}\right]\alpha \dot{\mathsf{\Phi }}+\left(\beta \left[K\right]+\gamma \left[L\right]\right)\mathsf{\Phi }+\left[F\right]=0$$

(27)

where Φ is the vector of an unknown nodal transportable quantity, M is the damping matrix, (β[K] + γ[L]) is the stiffness matrix, and F is the external flux vector.

The discretization of the ordinary differential equation gives:

$${\Phi }_{n+1}={\Phi }_{n-1}-\frac{2\Delta t}{\alpha M}\left[\left(\beta \left[K\right]+\gamma \left[L\right]\right){\Phi }_n+\left[F\right]\right]$$

(28)

2.3. Simulation Setup

As nanoscale devices often exhibit size-dependent behavior, it is essential to understand and accurately model size effects to predict device performance. The FEM consists of dividing the domain of interest into smaller elements (mesh) with particular attention to interfaces and contacts in order to approximate the behavior of the device. The FEM assumes that:

• The physical domain is continuous and can be represented by a finite number of elements.
• A linear relationship between stresses, strains, and displacements exists.
• The material properties are isotropic and homogeneous.

However, there could be some limitations to the application of FEM at the nanoscale. Among these, we mention the extremely small size of the structures, which requires a very fine mesh grid to capture the details. This could lead to computationally expensive models in terms of computational resources and calculation time. In such cases, careful consideration and mesh refinement are necessary. Therefore, finding a trade-off between computational time and accuracy is required for simulation problems. In our study, we use an adequate mesh, more refined at the interfaces and contacts. In addition, FEM is not ideal for accounting for quantum behaviors and often requires specialized methods based on quantum mechanics. Furthermore, FEM can face challenges in correctly dealing with boundary and interface properties that can be difficult to model accurately. In this study, the mesh has been refined so that it will be close to the positions of the atoms, meaning that the oxide–semiconductor interface is assumed to be smooth and that we do not hold the interface roughness. A linear shape function is adopted for potential, electron, and hole densities, with a relative tolerance of 10⁻⁶ as convergence criteria [53,54].

The numerical resolution of the electrothermal model follows the following steps:

i.

The Poisson equation and the continuity equations are solved iteratively, with convergence achieved.

ii.

The heat conduction equation is solved using a 300 K initial temperature assumption for the device to determine the temperature profile.

The parts of (i) and (ii) are solved iteratively to reach the convergent solution.

For ensuring the accuracy and reliability of the simulations, we have compared our numerical simulation using the finite element method with existing experimental data from the literature, reported in [55,56]. Figure 3a depicts the log scale drain current versus the gate voltage at V_d = 1 V. Hafnium dioxide (HfO₂) is considered as the gate dielectric; the other parameters are shown in the figure. Figure 3b exhibits the drain current versus the drain voltage at V_G = 0.6 V. The simulation was considered for a cylindrical GAAFET structure having a channel length of 180 and a diameter of 5 nm for a gate voltage of 0.6 V. Figure 4 illustrates a good agreement in output characteristics.

3. Results and Discussion

Figure 5 depicts the output characteristics of the GAAFET in linear and logarithmic views at V_d = 0.5 V. The results are evaluated for different high-k dielectric materials with and without trap density. The drain current is enhanced with higher-k dielectric materials (ZrO₂). This improvement in the device characteristics for higher permittivity is due to better electrostatic control of the channel region, which can both enhance I_ON at higher gate biases and reduce I_OFF at low gate voltages. It is observed from this figure that the oxide SiO₂ causes one order of reduction in I_OFF and about 350 µA enhancement of drive current at V_D =0.5 V and V_G = 1.5 V compared to Al₂O₃. The effect of trap density is more significant for dielectric materials with lower permittivity. In the following, the investigation is carried out on the GAAFET with Al₂O₃ due to its improvement in drain current compared to SiO₂.

In this section, we propose to investigate the effect of the trap density on the electric characteristics of the GAAFET device. Figure 6 shows the electric potential along the channel at the central cross-section of the channel for different values of N_t. The results are simulated for a constant drain value, V_d =1 V, and gate voltages V_G = 1.5 V. The relevant results show that the electric potential decreases with an increase in surface trap concentrations. The electric potential profile is similar along the channel and is higher near the drain region.

The output characteristic of the GAAFET is illustrated in Figure 7 with different trap density values at V_d = 0.5 V. It is clear from the figure that the higher drain current is obtained with a higher trap density, and the effect of the trap density is more intensive, especially for a higher value of the gate voltage. Furthermore, it can be observed that as the trap density ratio increases, the turn-on voltage decreases. Similar results are proven in [57].

Figure 8a shows the threshold voltage of the GAAFET as a function of the trap density for different drain currents, V_d. As can be seen from the figure, the threshold voltage versus the trap density is almost linear with trap density. These traps cause shifts in the device’s performance. Over time, the shifts in threshold voltage can result in device degradation and reduced reliability. Furthermore, continuous capture and release of charge carriers can cause physical damage and defects in the channel and the gate oxide, leading to a decrease in the device’s performance over time. Figure 8b depicts the transductance versus the gate voltage for different values of N_t. It is noticeable that a higher transductance value means a faster transistor. Results reveal that a higher g_m is obtained for N_t = 0 m⁻². It can also be noted that the value is illustrated for V_G = 1 V.

Figure 9 shows the I_on/I_off ratio in the left axis and the subthreshold slop in the right axis at V_d = 0.5 V. A higher on/off-state current ratio is provided for a lower trap density. A higher I_on/I_off ratio indicates a larger difference between the current levels when the transistor is in the on-state and off-state, so the transistor can switch more efficiently. The sub-threshold slope in (mV/decade) is an important parameter that indicates how the drain current changes with the gate-source voltage when the transistor operates in the subthreshold region. A lower subthreshold slope is desirable because it indicates that the transistor can be turned off and on more efficiently with smaller gate voltage changes. In such cases, to achieve the best possible subthreshold slope performance in GAAFET transistors, it is important to minimize the trap density, as shown in the figure.

Figure 10 shows the effect of trap density on the log scale output characteristics I_d-V_G of the GAAFET. This study is carried out for different geometric parameters such as the oxide thickness, the radius, and the gate length of the device. Figure 10a shows that the drain current varies with the gate voltage for different trap density values of N_t = 0, 10¹⁶ m⁻² and 5 × 10¹⁶ m⁻². It is clear from the figure that the drain current is higher in the case where the trap density is not taken into account. For V_G = 0, the drain current is 10⁻¹¹, 2 × 10⁻⁷, and 10⁻⁶ A and for N_t = 5 × 10¹⁶, 10¹⁶, and 0 m⁻², respectively. Figure 10b depicts the impact of the trap density on the drain current with different oxide thickness values. Results indicate that, especially at higher gate voltages, the drain current is higher with a lower oxide thickness. Likewise, it is apparent that the trap density reduces the drain current, in particular at lower gate voltages for the same oxide thickness. Similarly, the radius effect on the output characteristics of GAAFET devices is illustrated in Figure 10c. The lower radius gives a higher drain current. Figure 10d shows how the log scale I_d-V_G behaves with different gate lengths. When channel length increases, the drain current of the GAAFET decreases. This behavior is associated with the impact of short channel effects. The simulation’s results agree with those previously reported by [34].

Although the electrical study shows that reducing oxide thickness can enhance gate control and raise the on-state current of the transistor, shorter gate lengths can amplify short channel effects. They also increase the gate leakage current, which increases the device’s off-state power consumption and causes reliability issues. In what follows, we propose to investigate the effect of trap density on the thermal behavior of the device.

Figure 11 shows the temperature distribution in a 3D GAAFET structure for V_G = 1 V, V_d = 2 V without trap density. It is noted from the figure that the maximum temperature, T_max = 324 K, is localized near the drain region at the center of the device. The temperature decreases at the drain zone, where it is about 310 K. It is seen that the temperature significantly decreases from the hot spot (T = T_max) to the source region. On the source side, the temperature is equal to T₀ = 300 K.

To study the impact of the trap density, the temperature distribution in the GAAFET structure is evaluated for the different gate voltages N_t = 10¹⁶ m⁻² and N_t = 5 × 10¹⁶ m⁻². Figure 12 shows the surface distribution of the temperature for V_d = 2 V. Relevant results indicate that for a lower value of V_g (V_g = 0.5 V), the maximum temperature decreases from 311 K for N_t = 10¹⁶ m⁻² to 303 K for N_t = 5 × 10¹⁶ m⁻², and for V_G = 1 V, the decrease is about 5 K between the two values of trap density. For a high value of V_G (V_G = 1.5), the maximum temperature increases from 323 K to 325 K. Additional to these results, as it can be seen from the figure, the temperature distribution is not uniform for the different values, especially in the drain region. For that reason, the temperature profile along the z-axis, from the source to the drain side, is investigated and presented in Figure 13. As can be seen, the effect of the trap density is more noticeable in the hot spot region, where the temperature is at maximum. On the other hand, the results are evaluated along the symmetric axis of the GAAFET structure (R = 0) and at the oxide–semiconductor interface (R = 5 nm). For a constant value of N_t, (the dashed line in the figure), the temperature is more significant at the center of the device than at the oxide–semiconductor interface. The heat dissipation is evacuated forward into the drain region.

The impact of reducing oxide thickness and gate length on the device temperature is illustrated in Figure 14. The temperature profile along the z-axis is evaluated at V_g = 0.5 V and V_d = 1 V for L_g = 100 nm (a) and for L_g = 50 nm (b) with different oxide thicknesses. While reduced oxide thickness and gate length can enhance performance, they can also lead to increased device temperature. The results revealed that reducing oxide thickness results in higher standby temperature and, therefore, power consumption. This trade-off becomes more pronounced at smaller scales. For t_ox = 1 nm, the maximum temperature increases from 323.17 K to 350.24 K when L_g decreases from 100 nm to 50 nm. The temperature increase is about 16 K for t_ox = 2 nm.

The heat flux and temperature profile, in the middle of the structure (r = 2 nm) along the channel from the source side to the drain, are presented in Figure 15. Obtained results are evaluated at V_g = 0.8 V and V_d = 1 V. The profiles are presented for r = 0.5 nm, near the symmetry axis, where the hot spot is confined. The peak temperature is T_max = 324 K and the maximum heat flux is about 2.2 × 10²⁰ Wm⁻³. We observe that the hot spot is localized, particularly at the channel and drain contact.

Figure 16 shows the effect of the trap density on the temperature rise profile versus the drain voltage V_d. The outcomes are shown when V_d ranges from 0 to 1.8 V and V_g is 0.5 V. The temperature rise is found to increase quadratically with drain voltage according to the results. Without taking the trap density into account, the maximum temperature rise is noted for higher drain voltage values. For a constant drain voltage, the temperature rise becomes smaller as the trap density increases.

4. Conclusions

GAAFETs have the potential to be used for various applications due to their unique advantages over traditional MOSFETs and FinFETs. The electrothermal behavior of GAAFETs has been analyzed in this work. This study demonstrates how the trap density can affect the electrical responses and thermal behavior of GAAFETs. The numerical simulation has been investigated in a 2D axis-symmetry structure, the finite element method has been used in the discretization of the semiconductor equations, and the impact of the trap density on the output characteristics has been discussed. Moreover, the effect of the geometric parameters is investigated, taking into account the trap density on the output characteristics of the GAAFET. It has been shown that reducing the oxide thickness can improve gate control and increase the transistor’s on-state current. However, it also increases the gate leakage current, which increases the power consumption of the device in the off state. On the other hand, shorter gate lengths can increase short channel effects, reducing control over the channel and leading to potential reliability issues. Following that, the thermal behavior was analyzed. The results reveal that the electrical and thermal responses of transistors are significantly influenced by trap density. An enhancement of the output characteristics in the device is obtained using lower geometric dimensions such as oxide thickness, gate length, and device radius. In summary, comprehending and controlling trap density will enable researchers to produce more efficient, dependable, and high-performance GAAFET transistors in the future.