Next Article in Journal
Cascading and Ensemble Techniques in Deep Learning
Previous Article in Journal
Spatial Modeling of Air Pollution Using Data Fusion
 
 
Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
Journals
Electronics
Volume 12
Issue 15
10.3390/electronics12153352
electronics-logo
Submit to this Journal Review for this Journal Propose a Special Issue
► Article Menu

Article Menu

share Share announcement Help format_quote Cite question_answer Discuss in SciProfiles thumb_up
...
Endorse textsms
...
Comment
first_page
settings
Order Article Reprints
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Communication

185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design

by
Ruibing Dong
1,2 and
Chengwu You
1,2,*
1
GBA Branch of Aerospace Information Research Institute, Chinese Academy of Sciences, Guangzhou 510700, China
2
Guangdong Provincial Key Laboratory of Terahertz Quantum Electromagnetics, Guangzhou 510700, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(15), 3352; https://doi.org/10.3390/electronics12153352
Submission received: 3 July 2023 / Revised: 31 July 2023 / Accepted: 3 August 2023 / Published: 5 August 2023
Browse Figures
Versions Notes

Abstract

:
This paper presents a 220 GHz × 2 amplifier–doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency fmax for the NMOS transistor produced by this manufacturing process was 290 GHz. The saturation output power of the six-stage driver amplifier at 110 GHz was 11.5 dBm. The transistor of the frequency doubler consisted of a single-row interleaved Poly-Diffusion Contact balancing structure. Theoretically, the single-row interleaved Poly-Diffusion Contact balancing structure was able to effectively avoid parasitic components. The simulated results demonstrate that the presented structure achieves a higher output than the conventional designs. Based on these measured results, the presented amplifier–doubler chain provides a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. Based on the comparison with other reported results, the presented amplifier–doubler chain provides the highest output power among reported frequency doublers fabricated in CMOS technology.

1. Introduction

The 220 GHz band is a frequency band of the millimeter wave [1]. This frequency band is not yet fully developed, and the spectrum resources are very rich. Moreover, this band has many advantages that electromagnetic waves in other frequency bands do not. The first one is the long transmission distance [2,3]. The 220 GHz band is a high-frequency band, so it is able to propagate over longer distances and is suitable for indoor communications [4,5] and urban canyons [6,7]. The second is the large bandwidth. The 220 GHz band has a large bandwidth, so it can support high-speed data transmission [8,9,10,11,12]. The third one is strong penetration [13,14]. Millimeter waves can penetrate walls and other obstacles: another reason for their suitability for indoor communications and communications in urban canyon environments. The fourth is that it is not easy to disturb them. Due to its shorter wavelength, the 220 GHz band has less interference compared to other frequency bands. These characteristics make the 220 GHz band a very useful frequency band, which is widely used in wireless communication [15,16], radar [17,18], satellite communication [19], and other fields [20].
Currently, the main approach to generating electromagnetic waves at the 220 GHz band is to obtain the local oscillator signal by oscillating at a low frequency and then multiply the frequency by the desired frequency band. This means that the frequency doubling circuit is crucial for generating the 220 GHz band signal.
The earliest frequency multiplier designs used in the 220 GHz band are mainly based on III–V family semiconductors [21]. This is due to the high insulation of group III–V substrates. Therefore, the High-Electron-Mobility Transistor high-electron-mobility Transistor (HEMT) and Heterojunction Bipolar Transistor (HBT) based on the III–V group materials are used as the substrates’ transistor can achieve low insertion loss [22,23], and the passive devices fabricated under the III–V group process have a good quality factor [24]. In recent years, with the increasing cut-off frequency of silicon-based processes, more and more reports have been reported of implementing a 220 GHz frequency multiplier using silicon [25,26]. Among silicon-based processes, the CMOS process is the most commercially valuable [27,28]. It has the advantages of low noise, high reliability, fast response, low power consumption, functionality, and economy. These advantages have led to an increasing number of studies focusing on the design of the frequency multiplier in the CMOS processes. In 2016, Navneet Sharma et al. demonstrated a 160–310 GHz frequency doubler for rotational spectroscopy with a driver amplifier in a 65 nm bulk CMOS process [29]. At 0-dBm input power, the measured output power (Pout) varied from 3 to −8 dBm. In 2021, Akifumi Kasamatsu et al. implemented a ×9 frequency multiplier chain with a 3-dB bandwidth of 213–233 GHz in a 40 nm bulk CMOS. The chain realized a 4.1 dBm peak output power without using power combining [30].
In this paper, an amplifier–doubler chain including an integrated 110 GHz rat race balancer, a driving amplifier (DA), and an active doubler with an output frequency covering 185–215 GHz was designed. The 110 GHz Rat race balancer converted the single-ended signal to a differential signal with low insertion losses. The drive amplifier (DA) used a sixth-order pseudo-differential structure to ensure sufficient power input to the frequency doubler. The structure of the frequency doubler used a single-row interleaved Poly-Diffusion Contact balancing structure to replace the traditional two-separated transistors’ topology, which reduced the parasitic components of the frequency doubler. According to the results of the measurement, the output power of the frequency doubler reached 7.9 dBm.

2. Circuit Design

As shown in Figure 1, the presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency fmax of the NMOS transistor by this manufacturing process was 290 GHz. The supply voltages of VDD and VB were set to 0.9 V and 0.75 V, respectively.
At the input port of the designed amplifier–doubler chain, the single-ended signal was converted to a differential by an integrated 110 GHz rat race balun. The topology of the DA was given by the pseudo-difference structure, and the topology of the doubler was given by the push–push structure.

2.1. 110 GHz Balun and Driver Amplifier (DA)

Providing equally distributed in-phase and inverted-phase RF signals, rat race balun is a popular microwave passive component. It is used in many RF circuits [31]. Physical dimensions [32], frequency bandwidth [33], and insertion loss [34] are key indicators of balun’s performance.
In this design, the rat race balun, which converts the signal from a single end to a differential form, was made of thick copper layers at the top of the chip. In this way, the insertion loss could be effectively reduced.
As shown in Figure 2, the rat-race balun consists of three λ/4 transmission lines and a ¾λ transmission line. The performance of the rat-race balun with respect to the magnitude and phase imbalance was simulated, and the simulated results are shown in Figure 3. As shown in Figure 3, the S21 and S31 were about −4.4 dB and −4.8 dB, respectively, at 110 GHz for the rat-race balun.
The design of the drive amplifier was similar to the design of the low-power amplifier. However, the signal amplified by the drive amplifier should be ensured to be as distortion-free as possible.
According to Figure 1, the circuit used to amplify the power level of the 110 GHz signal was a six-stage DA. The DA was designed as a pseudo-difference structure. This structure is characterized by the fact that the capacitance Cgd between the gate and drain of the transistor can be compensated by the capacitance of the cross-coupling. As shown in Figure 4, the final stage of DA consisted of four NMOS transistors. The input signal at this stage was uniformly distributed to feed the gates of the NMOS transistors. The drains of the transistors were connected at the center, while the source was directly connected to the ground.
The output power versus the frequency of the six-stage DA was simulated with an input power level of −10 dBm, and the simulated results are shown in Figure 5. According to Figure 5, the DA gain became saturated at the 110 GHz frequency point. The saturation output power at 110 GHz was 11.5 dBm. Figure 5 shows that if the input power level of the DA was no less than −10 dBm, the power transmitted from the DA end to the frequency doubler could be up to 11.5 dBm.

2.2. 220 GHz Frequency Doubler

As shown in Figure 1, the frequency doubler is a balanced structure that was constructed using NMOS transistors. Due to the nonlinearity of the NMOS transistors, the signal input from the DA into the NMOS transistor excited the high-order harmonics. The output matching network was used to extract the second harmonics among the high-order harmonics, achieving the frequency doubling function.
In the design of the frequency doubler layout, the transistor consists of a single-row of staggered distribution. As shown in Figure 6a, the single row interleaving distribution meant that the policies of two transistors were interleaved, and the diffusion contact used as the ground or output port was placed between two policies. These diffusion contacts were reused by both transistors.
As can be seen from Figure 6, this design had two advantages over the regular two-line design. First, the length of the metal connection line between the ground and output ports was effectively reduced, which effectively reduced the parasitic components. Second, the area of the layout became more compact because the number of diffusion contacts was halved. The above discussion shows that the single-row interleaving distribution design can achieve more efficient parasitic parameters and a greater compact layout.
The output power of a frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure and a conventional structure at 220 GHz was simulated with different input power levels and different bias voltages. In the simulations, considering the absence of the transistor model in the cadence virtuoso with the structure, as shown in Figure 6b, the parallel connections of multiple single-gate ideal transistors were used equivalent to the single-row interleaving distribution structures. The simulated results of the power contours for different bias voltages are compared in Figure 7. According to Figure 7, the output power of a frequency doubler with the single-row interleaved Poly-Diffusion Contact balancing structure was able to reach a maximum of 7.8 dBm with a drive power of 11.5 dBm and a gate bias voltage Vgs of 0 V, while the output power of a frequency doubler with a conventional structure could only reach a maximum of 6.8 dBm with a drive power of 11 dBm and a gate bias voltage Vgs of 0 V.
Figure 8 illustrates the simulated output power versus the input power at 220 GHz with a bias voltage of 0 V for two frequency doublers with different structures. As can be seen from Figure 8, the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure can obtain a higher output power than the doubler with a conventional two-line structure when the power of the input doubler exceeds 7 dBm. In addition, the peak output power of the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure was 1 dB higher than that of the frequency doubler with a conventional two-line structure. In short, when the DA provided sufficient power, the frequency doubler with a single-row interleaved Poly-Diffusion Contact balancing structure could obtain higher output power than the frequency doubler with a conventional two-line structure. The difference in the peak output power between the two kinds of frequency doublers exceeded 1 dB. This comparison demonstrates that the presented structure can effectively reduce the parasitic components and achieve higher output power.
For a gate bias voltage Vgs of 0 V, Figure 9 shows the load pull diagram for a drive power of 11.5 dBm. As can be seen from Figure 9, the output power reached a maximum of 7.8 dBm. The topology of the output impedance matching network was L-C-L.

3. Measurement

Figure 10 shows a microphotograph of the presented amplifier–doubler chain. According to Figure 10, the total area of the chip, including the pads, was 795 × 1000 μm2. Measurements of the chip were performed on the wafer. The input port was probed using a Cascade Infinity WR 8 waveguide probe. The input signal generated by the commercial frequency multiplier module was injected into the chip, and the output power was measured by a VDI Erickson PM5 power meter with a waveguide taper. Two different measurement setups were used in the measurement since 220 GHz was the boundary of the WR3 and WR5 waveguides which needed to be probed with Cascade Infinity WR3 and WR5 waveguide probes, respectively.
The results of the measurement are shown in Figure 11. According to Figure 11, the presented amplifier–doubler chain reached its peak output power of 7.9 dBm at 200 GHz, and the 3 dB bandwidth was 30 GHz (from 185 GHz to 215 GHz).
Table 1 shows the performance of this frequency doubler compared to state-of-the-art frequency doublers. According to Table 1, the presented amplifier–doubler chain provided the highest peak output power of the reported frequency doublers when fabricated in CMOS technology. A frequency doubler fabricated in SiGe technology obtained a larger peak output power than the presented frequency doubler; however, the chip area of a frequency doubler fabricated in SiGe technology was 2.5 times that of the presented frequency doubler, and the DC power consumption of the frequency doubler fabricated in SiGe technology was more than three times as high as that the presented in the frequency doubler.

4. Conclusions

In this paper, an amplifier–doubler chain is presented. The presented amplifier–doubler chain consists of a rat-race balun, a sixth-stage DA, and a frequency doubler. The frequency doubler was designed with a single-row staggered distribution structure, which effectively reduced the parasitic component. According to the measurements, the presented amplifier–doubler chain provided a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. The DC-RF efficiency was 1.87%.
In summary, the presented amplifier–doubler chain provided the highest output power in CMOS technology at 200 GHz. The presented amplifier–doubler chain could be applied to such fields as THz imaging, radar, sensing, biomedicine, and ultra-fast communications.

Author Contributions

Conceptualization, R.D.; methodology, R.D.; software, R.D. and C.Y.; validation, R.D. and C.Y.; formal analysis, R.D. and C.Y.; investigation, R.D. and C.Y.; resources, R.D.; data curation, R.D. and C.Y.; writing—original draft preparation, C.Y.; writing—review and editing, R.D. and C.Y.; visualization, R.D. and C.Y.; supervision, R.D.; project administration, R.D.; funding acquisition, R.D. All authors have read and agreed to the published version of the manuscript.

Funding

The National Natural Science Foundation of China, 61988102. The Key Research and Development Program of Guangdong Province, China, 2019B090917007. The Science and Technology Planning Project of Guangdong Province, China, 2019B090909011.

Data Availability Statement

Data underlying the results presented in this paper are not publicly available at this time but may be obtained from the authors upon reasonable request.

Acknowledgments

The authors thanks Yang Xing, Yu-wen Chai and Hui-xiong Duan for their helpful discussion.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Marcus, M.; Pattan, B. Millimeter wave propagation: Spectrum management implications. IEEE Microw. Mag. 2005, 6, 54–62. [Google Scholar] [CrossRef] [Green Version]
  2. Zhongbo, Z.; Weidong, H.; Sheng, L.; Wei, S.; Caixia, W.; Wanzhao, C.; Xiaojun, L.; Li, L. A 220 GHz Mono-pulse Beam Adaptive Self-Tracking Antenna for Long Distance Communication Applications. In Proceedings of the 2022 47th International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz), Delft, The Netherlands, 28 August–2 September 2022; pp. 1–2. [Google Scholar]
  3. Niu, Z.; Zhang, B.; Wang, J.; Liu, K.; Chen, Z.; Yang, K.; Zhou, Z.; Fan, Y.; Zhang, Y.; Ji, D.; et al. The research on 220 GHz multicarrier high-speed communication system. China Commun. 2020, 17, 131–139. [Google Scholar] [CrossRef]
  4. Shen, Y.; Wang, W.; Zhu, F.; Yang, K.; Li, W.; Lai, Z. Indoor 220 GHz Channel Measurements and Analysis. In Proceedings of the 2022 IEEE International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA), Changchun, China, 25–27 February 2022; pp. 1295–1298. [Google Scholar]
  5. Wang, Y.; Liu, Y.; Liao, X.; Shao, Y.; Yu, Z.; Wang, G.; Li, X. Measured Reflection and Transmission Properties of Building Materials for Indoor THz Communication. IEEE Antennas Wirel. Propag. Lett. 2023, 22, 1361–1365. [Google Scholar] [CrossRef]
  6. Abbasi, N.A.; Gomez-Ponce, J.; Kondaveti, R.; Shaikbepari, S.M.; Rao, S.; Abu-Surra, S.; Xu, G.; Zhang, C.; Molisch, A.F. THz Band Channel Measurements and Statistical Modeling for Urban D2D Environments. arXiv 2021, arXiv:arXiv:2112.01770. [Google Scholar]
  7. Bengtson, M.; Lyu, Y.; Fan, W. Long-range VNA-based channel sounder: Design and measurement validation at MmWave and sub-THz frequency bands. China Commun. 2022, 19, 47–59. [Google Scholar] [CrossRef]
  8. Niu, Z.; Zhang, B.; Dai, B.; Zhang, J.; Shen, F.; Hu, Y.; Fan, Y.; Zhang, Y. 220 GHz Multi Circuit Integrated Front End Based on Solid-State Circuits for High Speed Communication System. Chin. J. Electron. 2022, 31, 569–580. [Google Scholar] [CrossRef]
  9. Hadidian, B.; Khoeini, F.; Naghavi, S.M.H.; Cathelin, A.; Afshari, E. A 220 GHz Energy-Efficient High-Data-Rate Wireless ASK Transmitter Array. IEEE J. Solid-State Circuits 2022, 57, 1623–1634. [Google Scholar] [CrossRef]
  10. Feng, Y.; Zhang, B.; Liu, Y.; Niu, Z.; Dai, B.; Fan, Y.; Chen, X. A 200–225 GHz Manifold-Coupled Multiplexer Utilizing Metal Waveguides. IEEE Trans. Microw. Theory Tech. 2021, 69, 5327–5333. [Google Scholar] [CrossRef]
  11. Martens, J.; Roberts, T. Broadband 220 GHz network analysis: Structures and performance. In Proceedings of the 2020 94th ARFTG Microwave Measurement Symposium (ARFTG), San Antonio, TX, USA, 26–29 January 2020; pp. 1–5. [Google Scholar]
  12. Dahal, S.; Amiri, M.; Appel, J.W.; Bennett, C.L.; Corbett, L.; Datta, R.; Denis, K.; Essinger-Hileman, T.; Halpern, M.; Helson, K.; et al. The CLASS 150/220 GHz Polarimeter Array: Design, Assembly, and Characterization. J. Low Temp. Phys. 2020, 199, 289–297. [Google Scholar] [CrossRef] [Green Version]
  13. Zarrinkhat, F.; Lamberg, J.; Baggio, M.; Tamminen, A.; Ala-Laurinaho, J.; Khaled, E.E.M.; Rius, J.M.; Robert, J.R.; Taylor, Z. Experimental exploration of longitudinal modes in spherical shells at 220 GHz–330 GHz: Applications to corneal sensing. In Proceedings of the 2021 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC), Munich, Germany, 21–25 June 2021; p. 1. [Google Scholar]
  14. Tu, H.; Meng, X.; Sun, Z.; Chen, L.; Fang, C.; Zhu, Y.; Zhang, H.; Zhang, J.; Fang, C. A Fast 220-GHz Real Aperture 3-D Personnel Screening System With a Novel-Shaped Mirror Design. IEEE Trans. Terahertz Sci. Technol. 2019, 9, 253–261. [Google Scholar] [CrossRef]
  15. Feng, Y.; Zhang, B.; Zhi, C.; Liu, K.; Liu, W.; Shen, F.; Qiao, C.; Zhang, J.; Fan, Y.; Yang, X. A 20.8-Gbps dual-carrier wireless communication link in 220-GHz band. China Commun. 2021, 18, 210–220. [Google Scholar] [CrossRef]
  16. Antes, J.; Lopez-Diaz, D.; Tessmann, A.; Leuther, A.; Massler, H.; Zwick, T.; Ambacher, O.; Kallfass, I. MMIC based wireless data transmission of a 12. In 5 Gbit/s signal using a 220 GHz carrier. In Proceedings of the 2011 41st European Microwave Conference, Manchester, UK, 10–13 October 2011; pp. 238–241. [Google Scholar]
  17. Mostajeran, A.; Naghavi, S.M.; Emadi, M.; Samala, S.; Ginsburg, B.P.; Aseeri, M.; Afshari, E. A High-Resolution 220-GHz Ultra-Wideband Fully Integrated ISAR Imaging System. IEEE Trans. Microw. Theory Tech. 2019, 67, 429–442. [Google Scholar] [CrossRef]
  18. Abbasi, N.A.; Molisch, A.F.; Zhang, J.C. Measurement of Directionally Resolved Radar Cross Section of Human Body for 140 and 220 GHz Bands. In Proceedings of the 2020 IEEE Wireless Communications and Networking Conference Workshops (WCNCW), Seoul, Republic of Korea, 6–9 April 2020; pp. 1–4. [Google Scholar]
  19. Duan, W.; Song, R.; Lu, C. Research Progress of Terahertz Satellite-ground Communication. In Proceedings of the 2021 International Conference on Computer Communication and Artificial Intelligence (CCAI), Guangzhou, China, 7–9 May 2021; pp. 146–149. [Google Scholar]
  20. Voinigescu, S.P.; Shopov, S.; Bateman, J.; Farooq, H.; Hoffman, J.; Vasilakopoulos, K. Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon. Proc. IEEE 2017, 105, 1087–1104. [Google Scholar] [CrossRef]
  21. Wang, R.; Li, G.; Verma, J.; Sensale-Rodriguez, B.; Fang, T.; Guo, J.; Hu, Z.; Laboutin, O.; Cao, Y.; Johnson, W.; et al. 220-GHz Quaternary Barrier InAlGaN/AlN/GaN HEMTs. IEEE Electron Device Lett. 2011, 32, 1215–1217. [Google Scholar] [CrossRef]
  22. Hiraki, T.; Aihara, T.; Hasebe, K.; Takeda, K.; Fujii, T.; Kakitsuka, T.; Tsuchizawa, T.; Fukuda, H.; Matsuo, S. Heterogeneously integrated III–V/Si MOS capacitor Mach–Zehnder modulator. Nat. Photonics 2017, 11, 482–485. [Google Scholar] [CrossRef]
  23. Sarker, M.A.R.; Song, I. Design and Analysis of fT-Doubler-Based RF Amplifiers in SiGe HBT Technology. Electronics 2020, 9, 772. [Google Scholar] [CrossRef]
  24. Pottier, P.; Seassal, C.; Letartre, X.; Leclercq, J.L.; Viktorovitch, P.; Cassagne, D.; Jouanin, C. Triangular and hexagonal high Q-factor 2-D photonic bandgap cavities on III-V suspended membranes. J. Light. Technol. 1999, 17, 2058–2062. [Google Scholar] [CrossRef]
  25. Momeni, O.; Afshari, E. A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS. IEEE J. Solid-State Circuits 2011, 46, 2966–2976. [Google Scholar] [CrossRef]
  26. Öjefors, E.; Heinemann, B.; Pfeiffer, U.R. Active 220- and 325-GHz Frequency Multiplier Chains in an SiGe HBT Technology. IEEE Trans. Microw. Theory Tech. 2011, 59, 1311–1318. [Google Scholar] [CrossRef]
  27. Traiche, S.; Trabelsi, M.; Bououden, A.; Yagoub, M.C.E. Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain—Bulk Capacitor Modulation. Electronics 2023, 12, 2784. [Google Scholar] [CrossRef]
  28. Lee, S.; Lee, Y.; Shin, H. A 52-to-57 GHz CMOS Phase-Tunable Quadrature VCO Based on a Body Bias Control Technique. Electronics 2023, 12, 2679. [Google Scholar] [CrossRef]
  29. Sharma, N.; Choi, W.; Kenneth, K.O. 160–310 GHz frequency doubler in 65-nm CMOS with 3-dBm peak output power for rotational spectroscopy. In Proceedings of the 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, USA, 22–24 May 2016; pp. 186–189. [Google Scholar]
  30. Dong, R.; Hara, S.; Watanabe, I.; Tanoi, S.; Hagino, T.; Kasamatsu, A. A 213–233 GHz ×9 Frequency Multiplier Chain with 4.1 dBm Output Power in 40 nm Bulk CMOS. In Proceedings of the 2021 IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, USA, 7–25 June 2021; pp. 458–461. [Google Scholar]
  31. Aflaki, P.; Negra, R.; Ghannouchi, F.M. Enhanced architecture for microwave current-mode class-D amplifiers applied to the design of an S-band GaN-based power amplifier. IET Microw. Antennas Propag. 2009, 3, 997–1006. [Google Scholar] [CrossRef]
  32. Settaluri, R.K.; Sundberg, G.; Weisshaar, A.; Tripathi, V.K. Compact folded line rat-race hybrid couplers. IEEE Microw. Guid. Wave Lett. 2000, 10, 61–63. [Google Scholar] [CrossRef]
  33. Okabe, H.; Caloz, C.; Itoh, T. A compact enhanced-bandwidth hybrid ring using a left-handed transmission line section. In Proceedings of the IEEE MTT-S International Microwave Symposium Digest, Philadelphia, PA, USA, 8–13 June 2003; Volume 321, pp. 329–332. [Google Scholar]
  34. Ding, H.; Kwanhim, L.; Guoan, W.; Woods, W.H. On-chip millimeter wave Rat-race Hybrid and Marchand Balun in IBM 0.13 um BiCMOS technology. In Proceedings of the 2008 Asia-Pacific Microwave Conference, Hong Kong, China, 16–20 December 2008; pp. 1–4. [Google Scholar]
  35. Lin, H.C.; Rebeiz, G.M. A SiGe Multiplier Array With Output Power of 5–8 dBm at 200–230 GHz. IEEE Trans. Microw. Theory Tech. 2016, 64, 2050–2058. [Google Scholar] [CrossRef]
  36. Eissa, M.H.; Malignaggi, A.; Kissinger, D. A 13.5-dBm 200–255-GHz 4-Way Power Amplifier and Frequency Source in 130-nm BiCMOS. IEEE Solid-State Circuits Lett. 2019, 2, 268–271. [Google Scholar] [CrossRef]
  37. Muralidharan, S.; Wu, K.; Hella, M. A 165–230 GHz SiGe amplifier-doubler chain with 5 dBm peak output power. In Proceedings of the 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, USA, 22–24 May 2016; pp. 302–305. [Google Scholar]
  38. Moon, B.T.; Yun, B.; Lee, S.G. A 237–263 GHz CMOS Frequency Doubler with 0.9 dBm Output Power and 2.87% Power Efficiency Based on Harmonic Matched Gmax-Core. In Proceedings of the 2022 IEEE/MTT-S International Microwave Symposium—IMS 2022, Denver, CO, USA, 19–24 June 2022; pp. 653–656. [Google Scholar]
Electronics 12 03352 g001
Figure 1. Diagram of the designed module of driver amplifier and frequency doubler.
Figure 1. Diagram of the designed module of driver amplifier and frequency doubler.
Electronics 12 03352 g001
Electronics 12 03352 g002
Figure 2. Schematic of the designed rat-race balun.
Figure 2. Schematic of the designed rat-race balun.
Electronics 12 03352 g002
Electronics 12 03352 g003
Figure 3. Simulated S-parameter of rat-race balun.
Figure 3. Simulated S-parameter of rat-race balun.
Electronics 12 03352 g003
Electronics 12 03352 g004
Figure 4. (a) Schematic and (b) Diagram of the final stage of the DA.
Figure 4. (a) Schematic and (b) Diagram of the final stage of the DA.
Electronics 12 03352 g004
Electronics 12 03352 g005
Figure 5. Simulated output power of the DA when input power was −10 dBm.
Figure 5. Simulated output power of the DA when input power was −10 dBm.
Electronics 12 03352 g005
Electronics 12 03352 g006
Figure 6. Schematic diagram of frequency doubler transistor design. (a) Regular two-line design; (b) Single-row interleaving distribution design.
Figure 6. Schematic diagram of frequency doubler transistor design. (a) Regular two-line design; (b) Single-row interleaving distribution design.
Electronics 12 03352 g006
Electronics 12 03352 g007
Figure 7. Simulated power contour of the frequency doubler for different input power levels and bias voltages at 220 GHz. (a) Single-row interleaving distribution design; (b) Conventional two-line design.
Figure 7. Simulated power contour of the frequency doubler for different input power levels and bias voltages at 220 GHz. (a) Single-row interleaving distribution design; (b) Conventional two-line design.
Electronics 12 03352 g007
Electronics 12 03352 g008
Figure 8. The relationship between the simulated output power and the input power of two kinds of frequency doublers with a different structure at 220 GHz when the bias voltage is set as 0 V. (a) Frequency doubler uses a single-row interleaved Poly-Diffusion Contact balancing structure; (b) Frequency doubler uses conventional two-line structure.
Figure 8. The relationship between the simulated output power and the input power of two kinds of frequency doublers with a different structure at 220 GHz when the bias voltage is set as 0 V. (a) Frequency doubler uses a single-row interleaved Poly-Diffusion Contact balancing structure; (b) Frequency doubler uses conventional two-line structure.
Electronics 12 03352 g008
Electronics 12 03352 g009
Figure 9. The load pull diagram with a drive power of 11.5 dBm.
Figure 9. The load pull diagram with a drive power of 11.5 dBm.
Electronics 12 03352 g009
Electronics 12 03352 g010
Figure 10. The micrograph of the presented amplifier–doubler chain.
Figure 10. The micrograph of the presented amplifier–doubler chain.
Electronics 12 03352 g010
Electronics 12 03352 g011
Figure 11. Measurement results of presented amplifier–doubler chain.
Figure 11. Measurement results of presented amplifier–doubler chain.
Electronics 12 03352 g011
Table 1. Comparison with other reported designs in the literature.
Table 1. Comparison with other reported designs in the literature.
Tech.fmaxFreq
[GHz]		Last Multiplier TopologyMulti. FactorDC-RF
[%]		Peak Pout
[dBm]		Size
[mm2]		DC
[mW]
[35]90 nm
SiGe		350200–230DA + Mult.20.2383.632700
[36]130 nm
SiGe		500200–255DA + Mult. + PA81.6012 *2.15990
[37]130 nm
SiGe		250165–230DA + Mult.20.875.2NA380
[29]65 nm
CMOS		NA160–310DA + Mult.22.8530.7170
[30]40 nm
CMOS		290213–233DA + Mult. + PA91.394.11.7185
[38]65 nm
CMOS		NA237–263Mult.22.870.90.07137
This work40 nm
CMOS		290185–215DA + Mult.22.07.90.78307
* 12 dBm w/o de-embedding the output balun and pad.
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Dong, R.; You, C. 185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design. Electronics 2023, 12, 3352. https://doi.org/10.3390/electronics12153352

AMA Style

Dong R, You C. 185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design. Electronics. 2023; 12(15):3352. https://doi.org/10.3390/electronics12153352

Chicago/Turabian Style

Dong, Ruibing, and Chengwu You. 2023. "185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design" Electronics 12, no. 15: 3352. https://doi.org/10.3390/electronics12153352

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop