Next Article in Journal
GGTr: An Innovative Framework for Accurate and Realistic Human Motion Prediction
Previous Article in Journal
An Enhancement Method in Few-Shot Scenarios for Intrusion Detection in Smart Home Environments
Previous Article in Special Issue
A Physics-Informed Recurrent Neural Network for RRAM Modeling
 
 
Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
Journals
Electronics
Volume 12
Issue 15
10.3390/electronics12153298
electronics-logo
Submit to this Journal Review for this Journal Propose a Special Issue
► Article Menu

Article Menu

share Share announcement Help format_quote Cite question_answer Discuss in SciProfiles thumb_up
...
Endorse textsms
...
Comment
first_page
settings
Order Article Reprints
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Review

Research Progress of Neural Synapses Based on Memristors

by
Yamin Li
1,2,
Kang Su
1,2,
Haoran Chen
1,2,
Xiaofeng Zou
1,2,
Changhong Wang
1,2,
Hongtao Man
1,2,
Kai Liu
1,2,
Xin Xi
1,2 and
Tuo Li
1,2,*
1
State Key Laboratory of High-End Server & Storage Technology, Inspur (Beijing), Electronic Information Industry Co., Ltd., Beijing 100089, China
2
Shandong Inspur Artificial Intelligence Research Institute Co., Ltd., Jinan 250101, China
*
Author to whom correspondence should be addressed.
Electronics 2023, 12(15), 3298; https://doi.org/10.3390/electronics12153298
Submission received: 26 June 2023 / Revised: 26 July 2023 / Accepted: 30 July 2023 / Published: 31 July 2023
(This article belongs to the Special Issue Memristor Devices and Semiconductor: Models, Developments and Applications)
Browse Figures
Review Reports Versions Notes

Abstract

:
The memristor, characterized by its nano-size, nonvolatility, and continuously adjustable resistance, is a promising candidate for constructing brain-inspired computing. It operates based on ion migration, enabling it to store and retrieve electrical charges. This paper reviews current research on synapses using digital and analog memristors. Synapses based on digital memristors have been utilized to construct positive, zero, and negative weights for artificial neural networks, while synapses based on analog memristors have demonstrated their ability to simulate the essential functions of neural synapses, such as short-term memory (STM), long-term memory (LTM), spike-timing-dependent plasticity (STDP), spike-rate-dependent plasticity (SRDP), and paired-pulse facilitation (PPF). Furthermore, synapses based on analog memristors have shown potential for performing advanced functions such as experiential learning, associative learning, and nonassociative learning. Finally, we highlight some challenges of building large-scale artificial neural networks using memristors.

1. Introduction

With the advent of artificial intelligence, big data, and the Internet of Things (IoT), data are growing exponentially, posing significant challenges to data storage and computation. In the traditional von Neumann architecture, the calculation and storage of data are separated. In the face of massive data, there are problems with memory walls [1,2,3]. The human brain can compute, store, and execute thousands of processes simultaneously with high efficiency and robustness [4]. The brain comprises neurons and synapses, interconnected to form a vast neural network that processes massive amounts of data with low power consumption. Understanding how the brain works can provide valuable insights for creating new structures and systems. Therefore, developing brain-inspired intelligent devices and constructing brain-inspired computing systems are critical to breaking through existing bottlenecks [5,6,7].
The memristor emerges naturally as the fourth fundamental electronic element after the resistor, capacitor, and inductor [8]. L. Chua first proposed the memristor concept in 1971 [9], and HP researchers produced the prototype device of a memristor in 2008 [10]. Subsequently, memristors have been developed based on the connection and fracture of conductive filaments, the oxidation–reduction reaction, the phase transition, and other resistive mechanisms [11,12,13]. Regarding physical structure, according to the number of memristor terminals, it can be divided into two-terminal memristors and three-terminal memristors. Compared with the two-terminal memristor, the three-terminal memristor has an additional modulation port, and the two-terminal memristor has a higher similarity with the biological synapse [14,15]. A memristor is an excellent option for creating neural synapses due to its high density (4F2; F is feature size) [16], nonvolatile nature, and compatibility with CMOS (complementary metal oxide semiconductor) during fabrication [17]. Memristor-based artificial synapses offer several advantages such as linear weight updating, stable resistance, fast running speed (<1 ns) [18], and low energy consumption (the most advanced consumption of each peak can be as low as few femtojoules or even sub-femtojoule [5]). Synapses in biological systems are responsible for transmitting weighted spikes from presynaptic neurons to postsynaptic neurons. The electrical characteristics of a memristor are highly similar to the physical attributes of neural synapses, and its working mechanism is based on ion migration. A single memristor can simulate the function of neural synapses while reducing chip area and power consumption compared to synapses composed of multiple transistors and capacitors [19]. A memristor can be categorized as digital or analog, depending on its resistance conversion mode. The digital memristor has abrupt resistance, while the analog memristor has gradual resistance. These two types can be used to construct digital and analog synapses.

2. Synapses Based on Digital Memristors

The HP Lab discovered a voltage–current curve consistent with the ideal memristor in the sandwich structure of Pt/TiO2/Pt (metal/insulation layer/metal), as shown in Figure 1a [10]. Since this breakthrough, researchers have developed two-terminal memristors with a similar structure by modifying the metal and insulating layer materials. The two-terminal memristor model is popular because of its versatility and simplicity [20]. Memristors can be categorized into digital and analog types based on the resistance conversion mode. The digital memristor’s resistance changes discreetly based on its voltage sweep. Two high- and low-resistance values correspond to the logical ‘0’ and ‘1’ states from a memory perspective, as shown in Figure 1b. The resistance change of a digital memristor has an apparent threshold. If the voltage is scanned forward and goes beyond the positive threshold, its resistance will change from high to low. On the other hand, if the voltage is scanned in reverse and goes beyond the negative threshold, its impedance will vary from low to high. However, the resistance remains unchanged if the voltage is applied between the two thresholds. This characteristic can be used to simulate the synapses of neural networks. Spikes can be transmitted from presynaptic neurons to postsynaptic neurons when there is low resistance, but transmission is prevented when there is high resistance. To create artificial neural networks through hardware, synapses are required to connect numerous neurons to perform complicated calculations [21]. Synapses must complete information transmission, and synaptic weights can be accurately stored and changed under specific circumstances [22]. A memristor has a memory function, particularly a digital one. The memristor’s resistance can be changed by applying a voltage beyond the threshold, similar to altering synaptic weights. When the voltage is below the threshold, the memristor’s resistance remains unchanged and is comparable to weight maintenance. The weight is stored in the memristor cross array. When the neuron gives the input, the output can be obtained according to Ohm’s and Kirchhoff’s laws, which genuinely realize the integration of memory and computation. In addition, the memristor’s nano-size and low-power computation are also the advantages of the synapse array. Digital memristor synaptic arrays can be constructed to meet the needs of large-scale integrated circuits [23]. A digital memristor is used to build a neural synapse array to realize the spiking neural networks (SNNs). The synapse weight in SNNs can be positive, negative, or zero. The synapse weight in Section 2.1 can only be positive and zero, while those in Section 2.2, Section 2.3 and Section 2.4 can be positive, negative, and zero.

2.1. One-Memristor Synapse

Simulating the synaptic function through 1M (one memristor) is the simplest connection method in the neural network. In Figure 2a, one end of the memristor is connected to the presynaptic neuron, while the other is connected to the postsynaptic neuron. The memristor determines the relationship between output and input, and the memristor’s resistance can be used as the weight in the neural network. The memristor’s resistance is related to the input voltage and the initial state. When the initial resistance is low or high, and the applied voltage is between the positive and negative thresholds, the synaptic weight remains at ‘1’ or ‘0’. Due to its small area, low power consumption, and high integration density, it is easy to construct large-scale synaptic arrays. However, when a single memristor is used as a synapse to build a synaptic cross array, as shown in Figure 2b, there is a sneak path problem. When reading/writing the resistance of a memristor and there are memristors with low resistance around, crosstalk will occur, limiting the accuracy of the reading/writing.

2.2. Two-Memristor-Two-Resistor Synapse

In the double-memristor synaptic circuit, a parallel or series topology junction is similar to a single-memristor synapse, which cannot gain negative weight. By adding two resistors to form a 2M2R (two-memristor-two-resistor) synaptic circuit, the weighted state of the synapse can be increased. Its connection mode is shown in Figure 3a. On each branch, a memristor and a resistor are connected in series. The voltage difference between points A and B is used as the output voltage.
When the input voltage Vin exceeding the threshold is loaded at the input end, the memristor’s resistance will change. When Vin is greater than the positive threshold voltage, the resistance of M1 will decrease, and M2 will increase; when Vin is less than the negative threshold voltage, the two memristors have opposite changes. According to the voltage division formula, the relationship between the output and the input voltage can be obtained as follows:
  V o u t = V A − V B = R 1 M 1 + R 1 − R 2 M 2 + R 2 V i n
We name the ratio of output to input g, which represents the synaptic weight of the circuit.
  g = R 1 M 1 + R 1 − R 2 M 2 + R 2 = R 1 M 2 − R 2 M 1 M 1 + R 1 M 2 + R 2
To simplify the model, if two resistance values are equal, the expression for synaptic weight is as follows:
    g = R 1   ( M 2 − M 1 )   M 1 + R 1   M 2 + R 2
From the expression, it can be seen that the synaptic weight is as follows:
  g   >   0         M 1   <   M 2 g   =   0         M 1   =   M 2 g   <   0         M 1   >   M 2
The formula shows that the 2M2R circuit can achieve positive, negative, and zero synaptic weights by cooperating with a differential circuit. Similarly, replacing M2 with a resistor can also achieve positive, negative, and zero synaptic weights [22].

2.3. Four-Memristor Synapse

The memristor bridge synaptic circuit (four-memristor, 4M) resembles the Wheatstone bridge [25]. Figure 3b shows that it comprises four identical memristors, using the difference between points A and B as the output voltage. The resistance of each memristor depends on its initial resistance and the input voltage. When the input voltage exceeds the threshold, the resistance of the memristor will change. When the input voltage exceeds the positive threshold, the resistance of M1 and M4 decreases, and the resistance of M2 and M3 increases. The input voltage is Vin, and the output voltage can be obtained by dividing the voltage formula as follows:
V o u t = V A − V B = M 2 M 1 + M 2 − M 4 M 3 + M 4 V i n
Similarly, using g to represent the synaptic weight, the value is:
g = M 2 M 3 − M 1 M 4   M 1 + M 2   M 3 + M 4
It can be seen from the formula of synaptic weight that when M2M3 > M1M4, the synaptic circuit can achieve positive weight; when M2M3 = M1M4, it can gain zero weight; and when M2M3 < M1M4, it can gain negative weight. Compared with the single synaptic circuit, the memristor bridge circuit increases the number of memristors. Still, this synaptic structure can more fully simulate the weight and is more suitable for memristor neural networks. Compared with the 2M2R circuit, it also has four components. However, the memristor is smaller than the resistor, making it ideal for reducing the chip area and suitable for large-scale integration.

2.4. Other Digital Synaptic Structures

Chen et al. designed a synaptic circuit composed of three memristors and two transistors [26], as shown in Figure 4. The input voltage is Vin, and the output Vout is the voltage difference between A and B. The threshold voltage of the transistor is VT. When V1 > VT and V2 ≥ VT, transistors T1 is on, and T2 is off. At this time, the output voltage is shown in expression (7):
  V o u t = V A − V B = V i n − M 3 M 2 + M 3 V i n = M 2 M 2 + M 3 V i n
When V1 ≤ VT and V2 < VT, transistor T2 is on and T1 is off. At this time, the output voltage is shown in expression (8):
  V o u t = V A − V B = M 1 M 2 + M 1 V i n − V i n = − M 2 M 2 + M 1 V i n
When V1 > VT, V2 < VT (or V1 ≤ VT, V2 ≥ VT), transistors T1 and T2 are both in the on (or off) state, and Vout = 0. Therefore, synaptic weight g can be expressed as expression (9):
g = M 2 M 2 + M 3     V 1 > V T , V 2   ≥   V T         0   V 1 > V T , V 2 < V T   o r   V 1   ≤   V T , V 2   ≥   V T   − M 2 M 2 + M 1     V 1   ≤   V T , V 2   < V T
From the expression of the synapse, it can be seen that this circuit can realize the setting of synaptic weights to positive, negative, and zero. In addition, a neuron based on a memristor is designed. Based on this neuron and synapse, a compact neural network is built. When the random weight change (RWC) algorithm is applied to this network, it results in faster training speed and fewer training errors than traditional RWC.

2.5. Summary of Synaptic Circuit Based on Digital Memristors

Digital synaptic circuits mainly use the nonvolatility and resistance variability of the memristor. It focuses on achieving the completeness of weight symbols (positive, negative, and zero weights) and maximizing linear variation. When using the memristor to construct digital synapses, the biological function of simulating neural synapses cannot be realized. Still, the weight is directly stored in the memristor, realizing the integration of storage and computation, reducing data handling, and improving computing efficiency. According to the variable resistance characteristics of the memristor, the weight value can be changed without replacing the hardware equipment to implement the neural network’s reusability. In addition, the nano-size and low power consumption make it advantageous for building large-scale neural networks, which is conducive to the hardware integration and implementation of neural network models. It can significantly accelerate the neural network training and testing process with corresponding hardware.

3. Synapses Based on Analog Memristors

The resistance of the analog memristor is polymorphic, which can continuously change according to the input voltage and remember the altered resistance value, as shown in Figure 5a. Figure 5b compares the electronic synapses and biological synapses. From the electrical characteristics, the analog memristor is more similar to the features of the biological synapse. Structurally, the two terminal memristors’ top electrodes, the middle insulating layer, and the bottom electrodes correspond to the presynaptic membrane, synaptic cleft, and postsynaptic membrane of the biological synapses. Because the memristor’s size is at the nano-level, it is expected to achieve the same number of brain synapses on VLSI (very-large-scale integration) and build a bionic brain. From the perspective of the working mode, external stimuli affect the transmission capacity of both synapses and memristors. The transmission capacity of synapses can be changed by the flow of certain specific ions like Ca2+, Na+, and Cl− inside and outside the cell membrane. Meanwhile, the memristor is realized by the transport of oxygen or metal ions. Moreover, they have a particular frequency dependence on external stimuli. Neurons will show a refractory period for stimulation with too high a frequency. Similarly, if the memristor is stimulated with a high frequency, its hysteresis curve will become a single value curve, which causes the loss of its memory characteristics. Synapse circuits based on analog memristors are often built by one or several memristors. Then, the characteristics of biological synapses can be simulated, mainly including STDP, SRDP, PPF, and other synaptic plasticity. Experience learning and nonassociation/association learning circuits are also built based on these characteristics. When using analog memristors to realize brain-inspired neural computing systems, it is necessary to make the functions of artificial synapses highly consistent with that of actual brain synapses. In Section 3.1, we discuss the basic functions of brain synapses that can be replicated by artificial synapses, while Section 3.2, Section 3.3 and Section 3.4 cover advanced functions.

3.1. Basic Synaptic Characteristics of Analog Memristor

Brain-inspired computing is expected to completely change traditional architecture and lead a new generation of powerful computing. A memristor is considered a potential solution for synapses [28]. The memristor has a natural synaptic-like performance, especially for multi-resistance analog memristors with adjustable weight. It can simulate the brain’s information processing methods for computation, achieving synaptic-like performance such as STM to LTM, STDP, SRDP, and PPF [29,30,31,32,33].

3.1.1. Short-Term Memory to Long-Term Memory

Human memory is divided into short-term memory (STM) and long-term memory (LTM) [34]. Correspondingly, synaptic behavior can be divided into long-term plasticity (LTP) and short-term plasticity (STP) [35]. LTP is believed to be related to learning and memory functions. In contrast, STP is often closely related to the critical computational operations of spatiotemporal information processing in biological systems [36]. STP is a short-term enhancement of neuronal connectivity, generally lasting for a few minutes or less. LTP permanently enhances neuronal connectivity, usually lasting several hours or years [37]. The main principle of implementing STP in devices is establishing an unstable conductive state under voltage conditions and restoring the original stable state after a relaxation process. Like biological memory, forgetting is a natural part of all memories, and the memristor’s weight decreases as a result [38]. However, the transformation from STM to LTM can be achieved through training, thus extending the forgetting time, as shown in Figure 6a. This characteristic is one of the fundamental characteristics of synaptic-like devices [39]. Rahmani et al. designed a double-layer material AIZS/Cs3Cu2Cl5-based memristor and showed the transition from STM to LTM under the repeated same pulse input [34]. Figure 6b shows that when 10 pulses are applied continuously, the increased current gradually decays once the voltage pulse is removed, showing STM characteristics. When 30 pulses are used, the current increases to a higher level and tends to be stable, as illustrated in Figure 6c. Comparing the conductance at the initial stimulus, final stimulus, and 60 s after removing stimulation by different pulse numbers, the attenuation of conductance is slight by 30 pulses, thus realizing the transition from STM to LTM, as shown in Figure 6d. Memristors based on lignin [27], WOx [40], Ag2S [41], NiO [42,43], and TiOx [44] also simulated the characteristics of the transition from STM to LTM.

3.1.2. Spike-Timing-Dependent Plasticity

STDP is a typical case of long-term plasticity [45]. STDP is a mechanism that regulates the synaptic intensity through the relative time difference between pre- and postsynaptic pulses. It is the theoretical basis for learning, information storage, and the development and perfection of neuronal circuits during brain development [46]. It is considered one of the primary learning rules of unsupervised learning. The specific rules are that if the presynaptic pulse arrives earlier than the postsynaptic pulse, the synapse triggers LTP, increasing synaptic weight and improving signal transmission efficiency between the pre- and postsynaptic neurons. Otherwise, it will lead to LTD. The effect of enhancement and suppression is related to the time difference between the arrival of the front and back pulses—the smaller the time difference, the more pronounced the enhancement/suppression effect [47]. To follow STDP, the memristor synapse should meet the requirements of conductance gradient and rapid response to a single spike [48]. The analog conductance state with linear and symmetric LTP/LTD is especially essential in reasoning and training hardware accelerators. Formula (10) is the expression of weight change in the memristor.
Δ ω   = A + exp − Δ t τ + ,     Δ t > 0 A − exp Δ t τ − ,     Δ t < 0  
where A+, A−, τ+, and τ—are constants. ∆t = tpost − tpre, where tpost and tpost are the time constants for pre- and postsynaptic firings, respectively.
In general, the STDP rule can be realized by applying overlapping pulses at both ends of the memristor. The effective pulse is the difference between the pulses received at both ends. The overlap method can convert the pulse timing information into the pulse amplitude information. When the presynaptic pulse arrives earlier than the postsynaptic pulse, the positive part of the practical pulse amplitude is more significant, making the synapse produce LTP. However, when the presynaptic pulse arrives later than the postsynaptic pulse, the negative part of the practical pulse amplitude is more significant, which can make the synapse produce LTD. The shorter the interval between the arrival of two pulses, the larger the adequate pulse amplitude and the more significant the change in synaptic weight caused. Li et al. designed a synapse based on a sulfur memristor, which can achieve the STDP rule, as shown in Figure 7 [49]. In addition, the STDP rule has been observed in memristors based on CuCrO2 [50], Al2O3/TiO2−x [51], WO3 [52], and TaOx [53].
However, the non-overlapping method can be used for the second-order memristor to implement the STDP rule. The change in the conductivity of the second-order memristor depends on the first variable and the second variable. In neurobiology, the relative time information between pulses is naturally embedded and not dependent on external factors. For example, through the natural decay of Ca2+, neurons respond to changes in synaptic response intensity, providing an internal time mechanism [54]. The non-overlapping method is more similar to the working mode of actual biological synapses. For example, different synaptic functions can be achieved by utilizing the internal oxygen holes in the oxide memristor at different time scales. Or, the change in local temperature can be used too. The second variable usually turns into transient dynamics, such as the dynamic decay after excitation, similar to the dynamics of calcium ions in biological synapses. Kim et al. proposed a Ta2O5-based second-order memristor whose conductive channel width can determine the device’s conductivity. In contrast, the device’s local temperature can adjust the ions’ mobility in the oxide. The first pulse is followed by the second, which can alter the local temperature. Temperature affects ions’ mobility, leading to conductivity changes [55]. The second-order memristor models based on different materials have been discovered successively, such as TiO2:Ag [56], WO3−x [57], SrTiO3 [58], and InGaZnO [59].

3.1.3. Spike-Rate-Dependent Plasticity

SRDP is a mechanism that changes synaptic plasticity by applying pulse series [60]. In biological learning, time and frequency are the main encoding methods for information. The stimulation mode of pulse series, which is generated by multiple connected neurons, is more commonly used than single or paired spikes. In synaptic devices, activity is not only related to time but also to frequency. SRDP relies on the Bienenstock Cooper Munro (BCM) rule as its higher-order function. According to the BCM rule, LTP will be generated when the frequency exceeds the threshold. When the frequency is lower than the threshold, LTD is caused. The threshold is a historical activity value related to previous synaptic activity. In addition, the difference between the frequency of presynaptic and postsynaptic pulses can also determine the size and direction of the weight change [49]. Figure 8a shows the synaptic weight shift with the number of pulses and pulse interval in a Cu2+-doped KNbO3 memristor [61]. Boppidi et al. designed a CuCrO2-based memristor. The measured conductance is 120 mS and 75 mS at 1 MHz and 200 kHz, respectively. And it can be maintained for 1000 s, exhibiting LTP and LTD characteristics. The conductivity change rate increases as the difference in input frequency between presynaptic and postsynaptic increases [50]. In addition, changes in synaptic weight depend on historical states in the SRDP rule. The same stimulus may cause opposite changes in synaptic weight, as shown in Figure 8b [62]. Synaptic weight increases when subjected to stimulation below 25 Hz but decreases with stimulation at 7 Hz. However, with continuous administration of 2 Hz inspiration, the synaptic weight increases again when subjected to 7 Hz stimulation.

3.1.4. Paired-Pulse Facilitation

PPF is one of the typical manifestations of STP. The human brain’s STP or STM can generally last from a few seconds to a few minutes. In biology, when two pulses are applied to the synapse, the response current caused by the second pulse will be greater than the first. The smaller the interval between the two pulses, the stronger the enhancement effect. Figure 9a reproduces the PPF phenomenon on guinea pig hippocampal cells [63]. The PPF effect is due to the first peak causing residual calcium ions in presynaptic neurons, which are released when the second peak arrives. This leads to an increase in the overall calcium concentration and the production of EPSC (empirical postsynaptic current). The strength of the effect decreases as the time between the two peaks elongates due to the exponential decay of residual calcium ions. Li et al. observed the PPF phenomenon on the CeO2/Nb−SrTiO3 memristor [62], as shown in Figure 9b. The change in synaptic weight is reflected through conductance, and a longer time interval will lead to a minor conductance change. PPF also be observed in La:HfO2 [64], tungsten oxide [57], Zinc Oxide/Poly (3-hexylthiophene) [65], AlOx/HfOx [66], SiNx [67], and Pt/HfO2/TaOx/TiN [68] based memristor.

3.2. Learning Experience

Psychologist Hermann Ebbinghaus’s research on human memory shows that we can turn STM into LTM by strengthening the stimuli. The first learning can be attained with less time or repetition during the second stimulus. This phenomenon is called the learning experience [64,69,70]. The synaptic weight in devices increases as the number of pulses increases. However, without external input, the conductivity decreases spontaneously, causing the weight to drop. Nevertheless, it does not decay to the initial state, like human memory follows a forgetting curve [71]. Then, by stimulating again during the decay process with less stimulation, the synaptic weight can be restored to a high level and increase the low memory level. It requires far fewer pulses to reach the high memory level after repeated learning and forgetting. This phenomenon is similar to the experience-based knowledge of biological systems, where memory recovery requires less stimulation over time [32]. Zhao et al. designed a photoelectric memristor based on a zinc oxide/poly (3-hexylthiophene) heterojunction, simulating the learning experience process of the human brain through three cycles of learning and forgetting [65]. After stimulation with 100 continuous light pulses (100 ms, 5 Hz, 1.14 Wcm−2), synaptic weight gradually increases and spontaneously decays for 100 s, reaching an intermediate state. In the second and third stages of learning, it only takes 16 and 7 pulses to restore the synaptic weight to the level achieved in the first stage, as shown in Figure 10. Additionally, the rate of attenuation is slower. Both electrical and optical pulse stimulation can make the synapse show a learning experience process. The type of stimulation used depends on the physical mechanism of the device’s high- and low-impedance changes. In addition, the p+-Si/n-ZnO heterostructure [72], Pt/BiFeO3/SrRuO3-based ferroelectric second-order [73], sponge-like double-layer porous oxide [74], and p-NiO/n-ZnO heterostructure memristor [75] both can simulate the experiential learning process of biological brains. Other teams also conduct mathematical modeling and analysis of this process [76].

3.3. Associative Learning

Associative learning is a standard method of self-learning in biological organisms. It allows the nervous system to simultaneously remember the connection between two events [77,78]. Reconstructing associative memory at the behavioral level is of great significance. A method similar to the brain’s self-learning neural morphological system can be designed [79]. Pavlov’s classically conditioned reflex is a typical example of associative learning. In the experiment of Pavlov’s dogs, food as the unconditioned stimulus (US) will cause dogs to drool. Before training, the bell rings, as the conditioned stimulus (CS) cannot make dogs drool [80]. In an experiment, dogs learn to associate the sound of a bell with food by being fed after the bell rings. With repeated training, the dogs drool at the sound of the bell. This process indicates that food and the bell have established associative memory. Subsequently, only the bell ring without food, or the food is given first, and then the bell rings. After several training sessions, the bell no longer causes drooling again, indicating a loss of associative memory between the food and the bell [81]. Guo et al. designed a multi-value analog Sr0.97Ba0.03TiO3−x (SBT) memristor with threshold characteristics. Based on the memristor, a Pavlov associative memory circuit is built. The memristor is the synaptic part, as shown in Figure 11a [82]. The pre-neuron creates the pre-spike, while the postsynaptic neuron triggers the post-spike. The subtracter then generates a control signal called Vout, which is used to regulate the weight of the memristor. There are three neurons involved in this process. The neurons A, B, and C represent the sounds of ringing, food, and a dog, respectively. If neuron A is stimulated independently, neuron C produces no signals. This means that the dog does not drool when it hears the bell. When presynaptic neuron B is stimulated, neuron C produces spike signals. That is, food as an unconditional stimulus can make the dog salivate. When neuron A is stimulated before neuron B, the synaptic weight between neuron A and neuron C increases, and the conductivity stabilizes at 0.0397 S; at this point, the associative memory of food and ringing tones is established. Afterward, when neuron A is stimulated alone, it can cause neuron C to generate spike signals. The schematic diagram of the process of establishing associative memory is shown in Figure 11b.
Numerous researchers have developed Pavlov circuits utilizing memristors. They have expanded the capabilities of these circuits after identifying their fundamental functions. For example, Sun et al. created a neural network circuit capable of time delay Pavlov associative memory [83]. They also designed a Pavlov associative memory circuit that can recognize multiple neurons [84]. Additionally, Shang et al. developed circuits that can execute the generalization and differentiation of Pavlovian associative memory [85]. In addition to Pavlovian associative courses, there are other associative circuits based on memristors. For example, Liao et al. designed emotional associative memory neural network circuits [86]. Shi et al. proposed online learning bidirectional associative memory network circuits [87]. Memristor-based associative circuits can simulate human associative memory learning behavior. It is significant for constructing neural networks for brain-inspired computing [88,89,90,91].

3.4. Nonassociative Learning

Nonassociative learning is distinct from associative learning. It does not necessitate a particular link between stimuli and response, also called simple learning [92]. In biology, nonassociative learning is crucial in how organisms respond to stimuli. It is divided into habituation and sensitivity and plays an essential role in evolutionary adaptation. Habituality can help organisms reduce their response to useless repetitive stimuli and filter out useless information; Sensitivity can gradually increase in response to strong and harmful reaction used to enhance helpful information. Habituality and sensitivity can last several days or weeks, depending on the stimulus pattern. The schematic diagram of nonassociative memory construction is shown in Figure 12a. Zhao et al. simulated nonassociative learning through a zinc oxide nanowire memristor without any other peripheral control circuit [93]. The memristor showed habituation and sensitization behavior under electrical and light stimulation. The memristor showed habituation under continuous 6 V pulse stimulation and sensitization under −3 V pulse stimulation. At the same time, ultraviolet light can sensitize the memristor. Different UV light intensities can lead to varying degrees of sensitization. Hong et al. designed a memory circuit to achieve nonassociative learning [94]. This circuit includes a synaptic module (Figure 12b), a neuron module, and a feedback module. It can generate an output signal with biological nonassociative learning characteristics, and its amplitude varies with the features of the input signal. Habituation behavior is generated under continuous weak stimuli below 30 mV, while sensitization behavior is generated under harmful stimuli above 30 mV. Sun et al. designed a memristor circuit to implement nonassociative learning under different emotions [95]. Nonassociative learning can improve the efficiency of neural network circuits in information processing and reduce the computational load of the circuit.

3.5. Summary of Synapses Based on Analog Memristors

The analog memristor has several stable resistance, and the change in the resistance is related to the amplitude and frequency of the pulse. The analog memristor behaves like a natural synapse and can be used alone or with other electronic elements to create synaptic circuits. Various properties of biological synapses, including basic characteristics and advanced learning and memory skills, can be simulated. Memristors based on multiple materials can simulate one or more attributes of neural synapses. Table 1 summarizes the biological factors that significant memristors can replicate. Neuromorphic computing can simulate the operation of human brains and can be physically realized by memristive arrays. What is more, the memristor’s conductance at each cross-point of the array can be mapped to the analog weight of neural networks, such as CNNs (convolutional neural networks), DNNs (deep neural networks), and RNNs (recurrent neural networks). Scientists aim to create an artificial neural network by replicating the brain’s intricate learning process. This breakthrough technology will overcome current limitations in computing and storage and use memristors to develop a brain-inspired chip that can perform natural brain-like computations.

4. Discussion

Using memristors to achieve in-memory computing and brain-inspired neuromorphic computing systems remains challenging. Building circuits and systems for new types of computing requires reliable and efficient memristors and arrays. The memristor is the cornerstone of the whole system and plays a vital role in overall performance improvement. New memory devices such as resistive random access memory (ReRAM), phase change memory (PCM) [11,97], ferroelectric field-effect transistor (FET) [98,99], and magnetoresistive random-access memory (MRAM) [100,101] can be used to build synapses. Each device has its advantages and disadvantages. Depending on the specific application requirements, one type of device may outperform others. Taking MRAM as an example, it boasts a theoretically permanent lifespan, but it faces challenges related to low switch ratio and large size. On the other hand, the ReRAM offers compatibility with CMOS technology, low power consumption, and analog conductivity modulation. Its most significant advantage is its resemblance to biological synapses on the physical level, making it one of the best choices for constructing neural synapses. However, some issues need to be addressed [102]. Research on memristors is primarily in the scientific research stage, and further large-scale industrialization is necessary. The main challenges faced are discussed.

4.1. Uniformity and Consistency

Different memristor devices exhibit significant differences in conductivity, switching speed, reliability, and other characteristics. Poor uniformity in synaptic circuits can cause performance degradation and instability issues. It is essential to enhance the manufacturing process and ensure better uniformity of instruments. One way to improve the consistency of material properties is to optimize the film deposition and annealing process. Another approach is to utilize adaptive learning algorithms to address performance variations caused by device non-uniformity. Moreover, designing synaptic circuit structures with greater fault tolerance and robustness can also enhance performance.

4.2. Stability and Reliability

Inconsistent resistance values during programming and reading can lead to unreliable data storage. This will affect the accuracy of synaptic weight transmission and hinder its application in analog neuromorphic systems. Factors such as the relaxation effect, diffusion/recombination of the oxygen vacancies, and formation/rupture of multiple weak conductive filaments can all lead to unstable resistance. Numerous researchers have addressed this issue from the perspectives of devices, arrays, systems, algorithms, and more. Studies have found that using Ta/HfO2 hybrid devices with Ta (O) conductive channels in HfO2 substrates can provide stable conductivity states. To further improve stability, movable ions with high activation energy can reduce drift and interference in conductivity states [103]. More solutions are shown in Table 2.

4.3. Large-Scale Integration

Building a large-scale neural network requires the integration of a high-density memristor array. Each neuron is connected to an average of 10,000 neurons in the human brain. Therefore, achieving such a significant connection requires a variety of rows and columns involving device size, interconnection, power consumption, and heat dissipation. Creating new integration technologies, such as 3D integration technology, is crucial to improve the performance and number of devices. Furthermore, effective power management and cooling solutions must be developed to increase device density and reduce interconnect latency. The sneak path determines whether the memristor 3D crossbar can usually work, and the sneak path of adjacent units interferes with the programming and reading of the memristor. Existing solutions include using a self-rectifying memristor to build a 3D crossbar or adding unidirectional conductive electronic components (diode, selector, and transistor) to limit the sneak current. In addition, IR drop also affects the performance of 3D crossbars, adversely affecting high operating voltage and power consumption [110]. Therefore, minimizing the length of connecting lines and impedance is equally essential as impedance. The 3D crossbar is a widely researched topic for creating large-scale neural networks that mimic the brain’s computing. Table 3 shows the current development status of the 3D crossbar.

4.4. Endurance

The practical large-scale application of the memristor is affected by its endurance, which is worse than that of traditional CMOS devices. Based on existing literature, the endurance of a memristor depends on its material, ranging from 10 to 1 × 106 cycles, with exceptional performance achieving up to 1 × 109 cycles [116]. For instance, Huang et al. reported the anisotropic resistive switching in quasi-two-dimensional (2D) κ-(BEDT-TTF)2Cu[N (CN)2]Cl electronic memristors with an endurance of 1.24 × 104 cycles [117]. Kumar et al. analyzed micrometer-scale titanium niobium oxide prototype memristors, exhibiting high endurance with over a million cycles [118]. Yang et al. outlined criteria to consider when selecting materials for high endurance and reported the Ta oxide memristor with an endurance of 1.2 × 1010 cycles [119]. Apart from materials and processes, electrical stress created by interfacing peripheral circuits also impacts endurance. Strukov developed a model that relates the tradeoff between endurance and writing time in nonvolatile memories [120]. Ravi and Prabaharan proposed a new technique by designing a fault-tolerant adaptable write scheme that can adapt based on the behavior and switching faults [121]. In the domain of neuromorphic computing, memristors offer high-density and low-power synaptic storage for SNN using hardware crossbar arrays. Titirsha proposed a new method to enhance lifetime by considering the endurance differences in each crossbar when mapping machine learning tasks [122]. This ensures that synapses with greater activation are always placed on memristors with greater endurance and vice versa, thereby enhancing the SNN’s overall endurance.

4.5. Fundamentals of Biological Theory

Further, we can explore the principle and mechanism of biological neural systems and apply this knowledge to the design and optimization of memristor synaptic circuits. For example, biological neurons’ and synapses’ complex dynamic behavior can be simulated to achieve more prosperous computational functions and higher energy efficiency. As the understanding of the working mechanism of the brain gradually deepens, brain-inspired computing can be realized at a deeper level.

5. Outlook

The memristor can realize the dynamics in biological neural networks and has excellent potential for efficient neural morphology computing. Therefore, it has attracted extensive research from material scientists, electronic engineers, physicists, and computational scientists. Currently, most hardware approaches to neuromorphic artificial intelligence rely on first-order memristors to simulate biological functions. While low-level memristors can simulate primitive low-level biological complexity, higher-order memristors can more faithfully simulate neuronal and synaptic functions. Presently, there have been some reports on the use of second-order or third-order memristors to build neural networks. This higher-order memristor neural network can leverage the inherent characteristics of the equipment to achieve more complex higher-order biological factors without requiring complex circuits. As a result, it promotes the progress of extraordinarily compact and powerful neural morphological computing [123,124]. Synapses are the most essential part of morphological neural networks, and we focus on using memristors in synapse research. Memristors can be categorized as digital or analog synapses based on resistance values. The functions they can achieve are introduced. Finally, the problems and challenges are summarized. As technology advances, we can expect solutions to various issues to arise gradually. Synapses based on memristors for neural morphology computing have excellent potential for multiple applications.

Author Contributions

Conceptualization, Y.L. and T.L.; methodology, K.S.; formal analysis, H.C.; investigation, X.Z.; resources, T.L.; data curation, C.W.; writing—original draft preparation, Y.L.; writing—review and editing, H.M.; visualization, K.L.; supervision, H.C.; project administration, X.X.; funding acquisition, T.L. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Key R&D Plan of Shandong Province, grant number 2021SFGC0801.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Zhang, Y.; Wang, Z.; Zhu, J.; Yang, Y.; Rao, M.; Song, W.; Zhuo, Y.; Zhang, X.; Cui, M.; Shen, L.; et al. Brain-Inspired Computing with Memristors: Challenges in Devices, Circuits, and Systems. Appl. Phys. Rev. 2020, 7, 011308. [Google Scholar] [CrossRef]
  2. Shan, X.-Y.; Wang, Z.-Q.; Xie, J.; Zheng, J.-H.; Xu, H.-Y.; Liu, Y.-C. Recent progress in optoelectronic memristive devices for in-sensor computing. Acta Phys. Sin. 2022, 71, 148701. [Google Scholar] [CrossRef]
  3. Wen, X.-Y.; Wang, Y.-S.; He, Y.-H.; Miao, X.-S. Memristive brain-like computing. Acta Phys. Sin. 2022, 71, 140501. [Google Scholar] [CrossRef]
  4. Xia, Q.; Yang, J.J. Memristive Crossbar Arrays for Brain-Inspired Computing. Nat. Mater. 2019, 18, 309–323. [Google Scholar] [CrossRef] [PubMed]
  5. Zhang, Y.; He, W.; Wu, Y.; Huang, K.; Shen, Y.; Su, J.; Wang, Y.; Zhang, Z.; Ji, X.; Li, G.; et al. Highly Compact Artificial Memristive Neuron with Low Energy Consumption. Small 2018, 14, e1802188. [Google Scholar] [CrossRef]
  6. Jiang, W.; Li, J.; Liu, H.; Qian, X.; Ge, Y.; Wang, L.; Duan, S. Memristor-Based Multi-Synaptic Spiking Neuron Circuit for Spiking Neural Network. Chin. Phys. B 2022, 31, 040702. [Google Scholar] [CrossRef]
  7. Xu, C.; Wang, C.; Sun, Y.; Hong, Q.; Deng, Q.; Chen, H. Memristor-Based Neural Network Circuit with Weighted Sum Simultaneous Perturbation Training and Its Applications. Neurocomputing 2021, 462, 581–590. [Google Scholar] [CrossRef]
  8. Chen, L.; Zhou, W.; Li, C.; Huang, J. Forgetting Memristors and Memristor Bridge Synapses with Long- and Short-Term Memories. Neurocomputing 2021, 456, 126–135. [Google Scholar] [CrossRef]
  9. Chua, L. Memristor-The Missing Circuit Element. IEEE Trans. Circuit Theory 1971, 18, 507–519. [Google Scholar] [CrossRef]
  10. Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The Missing Memristor Found. Nature 2008, 453, 80–83. [Google Scholar] [CrossRef]
  11. Pantazi, A.; Woźniak, S.; Tuma, T.; Eleftheriou, E. All-Memristive Neuromorphic Computing with Level-Tuned Neurons. Nanotechnology 2016, 27, 355205. [Google Scholar] [CrossRef]
  12. Wang, Z.; Joshi, S.; Savel’ev, S.; Song, W.; Midya, R.; Li, Y.; Rao, M.; Yan, P.; Asapu, S.; Zhuo, Y.; et al. Fully Memristive Neural Networks for Pattern Classification with Unsupervised Learning. Nat. Electron. 2018, 1, 137–145. [Google Scholar] [CrossRef] [Green Version]
  13. Zhang, X.; Liu, S.; Zhao, X.; Wu, F.; Wu, Q.; Wang, W.; Cao, R.; Fang, Y.; Lv, H.; Long, S.; et al. Emulating Short-Term and Long-Term Plasticity of Bio-Synapse Based on Cu/a-Si/Pt Memristor. IEEE Electron Device Lett. 2017, 38, 1208–1211. [Google Scholar] [CrossRef]
  14. John, R.A.; Liu, F.; Chien, N.A.; Kulkarni, M.R.; Zhu, C.; Fu, Q.; Basu, A.; Liu, Z.; Mathews, N. Synergistic Gating of Electro-Iono-Photoactive 2D Chalcogenide Neuristors: Coexistence of Hebbian and Homeostatic Synaptic Metaplasticity. Adv. Mater. 2018, 30, 1800220. [Google Scholar] [CrossRef]
  15. John, R.A.; Acharya, J.; Zhu, C.; Surendran, A.; Bose, S.K.; Chaturvedi, A.; Tiwari, N.; Gao, Y.; He, Y.; Zhang, K.K.; et al. Optogenetics Inspired Transition Metal Dichalcogenide Neuristors for In-Memory Deep Recurrent Neural Networks. Nat. Commun. 2020, 11, 3211. [Google Scholar] [CrossRef]
  16. Choi, B.J.; Torrezan, A.C.; Strachan, J.P.; Kotula, P.G.; Lohn, A.J.; Marinella, M.J.; Li, Z.; Williams, R.S.; Yang, J.J. High-Speed and Low-Energy Nitride Memristors. Adv. Funct. Mater. 2016, 26, 5290–5296. [Google Scholar] [CrossRef] [Green Version]
  17. Feali, M.S.; Ahmadi, A.; Hayati, M. Implementation of Adaptive Neuron Based on Memristor and Memcapacitor Emulators. Neurocomputing 2018, 309, 157–167. [Google Scholar] [CrossRef]
  18. Wang, W.; Laudato, M.; Ambrosi, E.; Bricalli, A.; Covi, E.; Lin, Y.-H.; Ielmini, D. Volatile Resistive Switching Memory Based on Ag Ion Drift/Diffusion Part I: Numerical Modeling. IEEE Trans. Electron Devices 2019, 66, 3795–3801. [Google Scholar] [CrossRef]
  19. Zhao, Y.; Pei, Y.; Zhang, Z.; Li, X.; Wang, J.; Yan, L.; He, H.; Zhou, Z.; Zhao, J.; Chen, J.; et al. Memristor Based on α-In2Se3 for Emulating Biological Synaptic Plasticity and Learning Behavior. Sci. China Mater. 2022, 65, 1631–1638. [Google Scholar] [CrossRef]
  20. Liu, Y.; Lin, Y.; Wang, Z.; Xu, H. Key Laboratory for UV Light-Emitting Materials and Technology, Oxide-based memristive neuromorphic synaptic devices. Acta Phys. Sin. 2019, 68, 168504. [Google Scholar] [CrossRef]
  21. Sun, J.; Han, J.; Wang, Y. Memristor-Based Neural Network Circuit of Memory with Emotional Homeostasis. IEEE Trans. Nanotechnol. 2022, 21, 204–212. [Google Scholar] [CrossRef]
  22. Huang, W.; Hang, P.; Yang, D.; Yu, X.; Li, X. Self-Rectifying-Based Memristors for Neuromorphic Computing. Sci. Bull. 2022, 67, 1213–1216. [Google Scholar] [CrossRef] [PubMed]
  23. Tuma, T.; Le Gallo, M.; Sebastian, A.; Eleftheriou, E. Detecting Correlations Using Phase-Change Neurons and Synapses. IEEE Electron Device Lett. 2016, 37, 1238–1241. [Google Scholar] [CrossRef]
  24. Stewart, D.R.; Ohlberg, D.A.A.; Beck, P.A.; Chen, Y.; Williams, R.S.; Jeppesen, J.O.; Nielsen, K.A.; Stoddart, J.F. Molecule-Independent Electrical Switching in Pt/Organic Monolayer/Ti Devices. Nano Lett. 2004, 4, 133–136. [Google Scholar] [CrossRef]
  25. Wang, R.; Mu, Z.; Sun, H.; Wang, Y. Dual-Mode Memristor Synaptic Circuit Design and Application in Image Processing. Front. Phys. 2021, 9, 690944. [Google Scholar] [CrossRef]
  26. Chen, J.; Duan, S.; Dong, Z.; Wang, L. Spintronic Memristor Synapse and Its RWC Learning Algorithm. IET Circuits Devices Syst. 2018, 12, 579–588. [Google Scholar] [CrossRef]
  27. Park, Y.; Lee, J.S. Artificial Synapses with Short- and Long-Term Memory for Spiking Neural Networks Based on Renewable Materials. ACS Nano 2017, 11, 8962–8969. [Google Scholar] [CrossRef]
  28. Covi, E.; Brivio, S.; Serb, A.; Prodromakis, T.; Fanciulli, M.; Spiga, S. Analog Memristive Synapse in Spiking Networks Implementing Unsupervised Learning. Front. Neurosci. 2016, 10, 482. [Google Scholar] [CrossRef] [Green Version]
  29. Hu, L.; Han, W.; Wang, H. Resistive Switching and Synaptic Learning Performance of a TiO2 Thin Film Based Device Prepared by Sol–Gel and Spin Coating Techniques. Nanotechnology 2020, 31, 155202. [Google Scholar] [CrossRef]
  30. Li, R.; Dong, Y.; Qian, F.; Xie, Y.; Chen, X.; Zhang, Q.; Yue, Z.; Gu, M. CsPbBr3/Graphene Nanowall Artificial Optoelectronic Synapses for Controllable Perceptual Learning. PhotoniX 2023, 4, 4. [Google Scholar] [CrossRef]
  31. Kumar, N.; Patel, M.; Nguyen, T.T.; Bhatnagar, P.; Kim, J. All-Oxide-Based and Metallic Electrode-Free Artificial Synapses for Transparent Neuromorphic Computing. Mater. Today Chem. 2022, 23, 100681. [Google Scholar] [CrossRef]
  32. Xu, X.; Xu, W.; Wei, B.; Hu, F. Memristor-Based Neural Network Circuit of Delay and Simultaneous Conditioning. IEEE Access 2021, 9, 148933–148947. [Google Scholar] [CrossRef]
  33. Zhang, X.; Long, K. Improved Learning Experience Memristor Model and Application as Neural Network Synapse. IEEE Access 2019, 7, 15262–15271. [Google Scholar] [CrossRef]
  34. He, N.; Ye, F.; Liu, J.; Sun, T.; Wang, X.; Hou, W.; Shao, W.; Wan, X.; Tong, Y.; Xu, F.; et al. Multifunctional Ag–In–Zn–S/Cs3Cu2Cl5-Based Memristors with Coexistence of Non-Volatile Memory and Volatile Threshold Switching Behaviors for Neuroinspired Computing. Adv. Elect. Mater. 2023, 9, 2201038. [Google Scholar] [CrossRef]
  35. Srinivasan, G.; Sengupta, A.; Roy, K. Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning. Sci. Rep. 2016, 6, 29545. [Google Scholar] [CrossRef] [Green Version]
  36. Abbott, L.F.; Regehr, W.G. Synaptic Computation. Nature 2004, 431, 796–803. [Google Scholar] [CrossRef]
  37. Rahmani, M.K.; Ismail, M.; Mahata, C.; Kim, S. Effect of Interlayer on Resistive Switching Properties of SnO2-Based Memristor for Synaptic Application. Results Phys. 2020, 18, 103325. [Google Scholar] [CrossRef]
  38. Shao, N.; Zhang, S.; Shao, S. China Mathematical model of memristor with sensory memory. Acta Phys. Sin. 2019, 68, 018501. [Google Scholar] [CrossRef]
  39. Wang, K.; Dai, S.; Zhao, Y.; Wang, Y.; Liu, C.; Huang, J. Light-Stimulated Synaptic Transistors Fabricated by a Facile Solution Process Based on Inorganic Perovskite Quantum Dots and Organic Semiconductors. Small 2019, 15, 1900010. [Google Scholar] [CrossRef]
  40. Chang, T.; Jo, S.H.; Lu, W. Short-Term Memory to Long-Term Memory Transition in a Nanoscale Memristor. ACS Nano 2011, 5, 7669–7676. [Google Scholar] [CrossRef]
  41. Ohno, T.; Hasegawa, T.; Tsuruoka, T.; Terabe, K.; Gimzewski, J.K.; Aono, M. Short-Term Plasticity and Long-Term Potentiation Mimicked in Single Inorganic Synapses. Nat. Mater. 2011, 10, 591–595. [Google Scholar] [CrossRef] [PubMed]
  42. Li, Y.; Chu, J.; Duan, W.; Cai, G.; Fan, X.; Wang, X.; Wang, G.; Pei, Y. Analog and Digital Bipolar Resistive Switching in Solution-Combustion-Processed NiO Memristor. ACS Appl. Mater. Interfaces 2018, 10, 24598–24606. [Google Scholar] [CrossRef] [PubMed]
  43. Yun, S.; Mahata, C.; Kim, M.H.; Kim, S. Artificial Synapse Characteristics of a ZnO-Based Memristor with a Short-Term Memory Effect. Appl. Surf. Sci. 2022, 579, 152164. [Google Scholar] [CrossRef]
  44. Hasina, D.; Mandal, A.; Basu, N.; Srivastava, S.K.; Mitra, A.; Som, T. Realization of Short- and Long-Term Memories at Nanoscale and Their Temporal Evolution in Two-Terminal Memristive Synapses. Appl. Surf. Sci. 2023, 611, 155563. [Google Scholar] [CrossRef]
  45. Kuzum, D.; Jeyasingh, R.G.D.; Lee, B.; Wong, H.-S.P. Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing. Nano Lett. 2012, 12, 2179–2186. [Google Scholar] [CrossRef]
  46. Lin, Y.; Zeng, T.; Xu, H.; Wang, Z.; Zhao, X.; Liu, W.; Ma, J.; Liu, Y. Transferable and Flexible Artificial Memristive Synapse Based on WOx Schottky Junction on Arbitrary Substrates. Adv. Electron. Mater. 2018, 4, 1800373. [Google Scholar] [CrossRef]
  47. Bi, G.; Poo, M. Synaptic Modifications in Cultured Hippocampal Neurons: Dependence on Spike Timing, Synaptic Strength, and Postsynaptic Cell Type. J. Neurosci. 1998, 18, 10464–10472. [Google Scholar] [CrossRef] [Green Version]
  48. Jo, S.H.; Chang, T.; Ebong, I.; Bhadviya, B.B.; Mazumder, P.; Lu, W. Nanoscale Memristor Device as Synapse in Neuromorphic Systems. Nano Lett. 2010, 10, 1297–1301. [Google Scholar] [CrossRef]
  49. Li, Y.; Zhong, Y.; Zhang, J.; Xu, L.; Wang, Q.; Sun, H.; Tong, H.; Cheng, X.; Miao, X. Activity-Dependent Synaptic Plasticity of a Chalcogenide Electronic Synapse for Neuromorphic Systems. Sci. Rep. 2014, 4, 4906. [Google Scholar] [CrossRef] [Green Version]
  50. Boppidi, P.K.R.; Suresh, B.; Zhussupbekova, A.; Biswas, P.; Mullarkey, D.; Raj, P.M.P.; Shvets, I.V.; Kundu, S. Efficient Resistive Switching and Spike Rate Dependent Plasticity in a New CuCrO2 Memristor for Plausible Neuromorphic Systems. IEEE Trans. Electron. Devices 2020, 67, 3451–3458. [Google Scholar] [CrossRef]
  51. Prezioso, M.; Merrikh Bayat, F.; Hoskins, B.; Likharev, K.; Strukov, D. Self-Adaptive Spike-Time-Dependent Plasticity of Metal-Oxide Memristors. Sci. Rep. 2016, 6, 21311. [Google Scholar] [CrossRef] [Green Version]
  52. Tan, Z.H.; Yang, R.; Terabe, K.; Yin, X.B.; Zhang, X.D.; Guo, X. Synaptic Metaplasticity Realized in Oxide Memristive Devices. Adv. Mater. 2016, 28, 377–384. [Google Scholar] [CrossRef]
  53. Wang, Z.; Yin, M.; Zhang, T.; Cai, Y.; Wang, Y.; Yang, Y.; Huang, R. Engineering Incremental Resistive Switching in TaOx Based Memristors for Brain-Inspired Computing. Nanoscale 2016, 8, 14015–14022. [Google Scholar] [CrossRef]
  54. Graupner, M.; Brunel, N. Calcium-Based Plasticity Model Explains Sensitivity of Synaptic Changes to Spike Pattern, Rate, and Dendritic Location. Proc. Natl. Acad. Sci. USA 2012, 109, 3991–3996. [Google Scholar] [CrossRef]
  55. Kim, S.; Du, C.; Sheridan, P.; Ma, W.; Choi, S.; Lu, W.D. Experimental Demonstration of a Second-Order Memristor and Its Ability to Biorealistically Implement Synaptic Plasticity. Nano Lett. 2015, 15, 2203–2211. [Google Scholar] [CrossRef]
  56. Yan, X.; Zhao, J.; Liu, S.; Zhou, Z.; Liu, Q.; Chen, J.; Liu, X.Y. Memristor with Ag-Cluster-Doped TiO2 Films as Artificial Synapse for Neuroinspired Computing. Adv. Funct. Mater. 2018, 28, 1705320. [Google Scholar] [CrossRef]
  57. Du, C.; Ma, W.; Chang, T.; Sheridan, P.; Lu, W.D. Biorealistic Implementation of Synaptic Functions with Oxide Memristors through Internal Ionic Dynamics. Adv. Funct. Mater. 2015, 25, 4290–4299. [Google Scholar] [CrossRef]
  58. Wang, Z.; Joshi, S.; Savel’ev, S.E.; Jiang, H.; Midya, R.; Lin, P.; Hu, M.; Ge, N.; Strachan, J.P.; Li, Z.; et al. Memristors with Diffusive Dynamics as Synaptic Emulators for Neuromorphic Computing. Nat. Mater 2017, 16, 101–108. [Google Scholar] [CrossRef] [Green Version]
  59. Wang, Z.Q.; Xu, H.Y.; Li, X.H.; Yu, H.; Liu, Y.C.; Zhu, X.J. Synaptic Learning and Memory Functions Achieved Using Oxygen Ion Migration/Diffusion in an Amorphous InGaZnO Memristor. Adv. Funct. Mater. 2012, 22, 2759–2765. [Google Scholar] [CrossRef]
  60. Ren, Z.Y.; Zhu, L.Q.; Guo, Y.B.; Long, T.Y.; Yu, F.; Xiao, H.; Lu, H.L. Threshold-Tunable, Spike-Rate-Dependent Plasticity Originating from Interfacial Proton Gating for Pattern Learning and Memory. ACS Appl. Mater. Interfaces 2020, 12, 7833–7839. [Google Scholar] [CrossRef]
  61. Park, S.M.; Hwang, H.G.; Woo, J.U.; Lee, W.H.; Chae, S.J.; Nahm, S. Improvement of Conductance Modulation Linearity in a Cu2+-Doped KNbO3 Memristor through the Increase of the Number of Oxygen Vacancies. ACS Appl. Mater. Interfaces 2020, 12, 1069–1077. [Google Scholar] [CrossRef]
  62. Li, H.; Geng, S.; Liu, T.; Cao, M.; Su, J. Synaptic and Gradual Conductance Switching Behaviors in CeO2/Nb–SrTiO3 Heterojunction Memristors for Electrocardiogram Signal Recognition. ACS Appl. Mater. Interfaces 2023, 15, 5456–5465. [Google Scholar] [CrossRef] [PubMed]
  63. Salin, P.A.; Scanziani, M.; Malenka, R.C.; Nicoll, R.A. Distinct Short-Term Plasticity at Two Excitatory Synapses in the Hippocampus. Proc. Natl. Acad. Sci. USA 1996, 93, 13304–13309. [Google Scholar] [CrossRef] [PubMed]
  64. Niu, J.; Fang, Z.; Liu, G.; Zhao, Z.; Yan, X. Multilevel State Ferroelectric La:HfO2-Based Memristors and Their Implementations in Associative Learning Circuit and Face Recognition. Sci. China Mater. 2023, 66, 1148–1156. [Google Scholar] [CrossRef]
  65. Zhao, P.; Ji, R.; Lao, J.; Jiang, C.; Tian, B.; Luo, C.; Lin, H.; Peng, H.; Duan, C.-G. Multifunctional Two-Terminal Optoelectronic Synapse Based on Zinc Oxide/Poly(3-Hexylthiophene) Heterojunction for Neuromorphic Computing. ACS Appl. Polym. Mater. 2022, 4, 5688–5695. [Google Scholar] [CrossRef]
  66. Qi, M.; Fu, T.; Yang, H.; Tao, Y.; Li, C.; Xiu, X. Reliable Analog Resistive Switching Behaviors Achieved Using Memristive Devices in AlOx/HfOx Bilayer Structure for Neuromorphic Systems. Semicond. Sci. Technol. 2022, 37, 035018. [Google Scholar] [CrossRef]
  67. Choi, J.; Kim, S. Coexistence of Long-Term Memory and Short-Term Memory in an SiNx-Based Memristor. Phys. Status Solidi RRL 2020, 14, 2000357. [Google Scholar] [CrossRef]
  68. Ryu, H.; Kim, S. Self-Rectifying Resistive Switching and Short-Term Memory Characteristics in Pt/HfO2/TaOx/TiN Artificial Synaptic Device. Nanomaterials 2020, 10, 2159. [Google Scholar] [CrossRef]
  69. Chen, L.; He, Z.; Li, C.; Wen, S.; Chen, Y. Revisiting Memristor Properties. Int. J. Bifurc. Chaos 2020, 30, 2050172. [Google Scholar] [CrossRef]
  70. Lei, P.; Duan, H.; Qin, L.; Wei, X.; Tao, R.; Wang, Z.; Guo, F.; Song, M.; Jie, W.; Hao, J. High-Performance Memristor Based on 2D Layered BiOI Nanosheet for Low-Power Artificial Optoelectronic Synapses. Adv. Funct. Mater. 2022, 32, 2201276. [Google Scholar] [CrossRef]
  71. Ebbinghaus, H. Memory: A Contribution to Experimental Psychology. Ann. Neurosci. 2013, 20, 155–156. [Google Scholar] [CrossRef]
  72. Song, W.; Yu, H.; Li, X.; Fang, R.; Zhu, W.; Zhang, L. Electric-Controlled Resistive Switching and Different Synaptic Behaviors in P+-Si/n-ZnO Heterojunction Memristor. IEEE Trans. Electron Devices 2023, 70, 1648–1652. [Google Scholar] [CrossRef]
  73. Li, W.; Fan, Z.; Huang, Q.; Rao, J.; Cui, B.; Chen, Z.; Lin, Z.; Yan, X.; Tian, G.; Tao, R.; et al. Polarization-Dominated Internal Timing Mechanism in a Ferroelectric Second-Order Memristor. Phys. Rev. Appl. 2023, 19, 014054. [Google Scholar] [CrossRef]
  74. Gao, Q.; Huang, A.; Zhang, J.; Ji, Y.; Zhang, J.; Chen, X.; Geng, X.; Hu, Q.; Wang, M.; Xiao, Z.; et al. Artificial Synapses with a Sponge-like Double-Layer Porous Oxide Memristor. NPG Asia Mater. 2021, 13, 3. [Google Scholar] [CrossRef]
  75. Xiao, C.; Xu, B.; Si, J.; Di, Z.; Zhao, L.; Liu, R.; Lv, Q.; Wang, L.; Zhang, L. Wide Waveband Light Detection and Storage Device for Visual Memory. Phys. Status Solidi A 2022, 219, 2100881. [Google Scholar] [CrossRef]
  76. Shao, N.; Zhang, S.B.; Shao, S.Y. Analysis of memristor model with learning-experience behavior. Acta Phys. Sin. 2019, 68, 198502. [Google Scholar] [CrossRef]
  77. An, H.; An, Q.; Yi, Y. Realizing Behavior Level Associative Memory Learning Through Three-Dimensional Memristor-Based Neuromorphic Circuits. IEEE Trans. Emerg. Top. Comput. Intell. 2021, 5, 668–678. [Google Scholar] [CrossRef]
  78. Chen, Y.; Li, L.; Wang, N.; Wang, H.; Yang, Z.; Long, D. Memory Association Circuit Based on Memristor for Neural Networks. AIP Adv. 2023, 13, 025220. [Google Scholar] [CrossRef]
  79. Du, S.; Deng, Q.; Hong, Q.; Li, J.; Liu, H.; Wang, C. A Memristor-Based Circuit Design and Implementation for Blocking on Pavlov Associative Memory. Neural Comput. Appl. 2022, 34, 14745–14761. [Google Scholar] [CrossRef]
  80. Li, Z.; Yi, Z. A Memristor-Based Associative Memory Circuit Considering Synaptic Crosstalk. Electron. Lett. 2022, 58, 539–541. [Google Scholar] [CrossRef]
  81. Sun, J.; Han, J.; Liu, P.; Wang, Y. Memristor-Based Neural Network Circuit of Pavlov Associative Memory with Dual Mode Switching. AEU—Int. J. Electron. Commun. 2021, 129, 153552. [Google Scholar] [CrossRef]
  82. Guo, M.; Zhu, Y.; Liu, R.; Zhao, K.; Dou, G. An Associative Memory Circuit Based on Physical Memristors. Neurocomputing 2022, 472, 12–23. [Google Scholar] [CrossRef]
  83. Sun, J.; Han, G.; Zeng, Z.; Wang, Y. Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory with Time Delay and Variable Learning Rate. IEEE Trans. Cybern. 2019, 50, 2935–2945. [Google Scholar] [CrossRef]
  84. Sun, J.; Wang, Y.; Liu, P.; Wen, S.; Wang, Y. Memristor-Based Neural Network Circuit with Multimode Generalization and Differentiation on Pavlov Associative Memory. IEEE Trans. Cybern. 2022, 53, 3351–3362. [Google Scholar] [CrossRef]
  85. Shang, M.; Wang, X. A Memristor-Based Circuit Design for Generalization and Differentiation on Pavlov Associative Memory. Neurocomputing 2020, 389, 18–26. [Google Scholar] [CrossRef]
  86. Liao, M.; Wang, C.; Sun, Y.; Lin, H.; Xu, C. Memristor-Based Affective Associative Memory Neural Network Circuit with Emotional Gradual Processes. Neural Comput. Appl. 2022, 34, 13667–13682. [Google Scholar] [CrossRef]
  87. Shi, J.; Zeng, Z. Design of In-Situ Learning Bidirectional Associative Memory Neural Network Circuit with Memristor Synapse. IEEE Trans. Emerg. Top. Comput. Intell. 2021, 5, 743–754. [Google Scholar] [CrossRef]
  88. Wang, C.; Xu, C.; Sun, J.; Deng, Q. A Memristor-Based Associative Memory Neural Network Circuit with Emotion Effect. Neural Comput. Appl. 2023, 35, 10929–10944. [Google Scholar] [CrossRef]
  89. Wang, L.; Zou, H. A New Emotion Model of Associative Memory Neural Network Based on Memristor. Neurocomputing 2020, 410, 83–92. [Google Scholar] [CrossRef]
  90. Wang, Y.; Wang, G.; Shen, Y.; Iu, H.H.C. A Memristor Neural Network Using Synaptic Plasticity and Its Associative Memory. Circuits Syst. Signal Process. 2020, 39, 3496–3511. [Google Scholar] [CrossRef]
  91. Wang, S.; Dong, B.; Fu, Y.; He, Y.; Miao, X. A Memristor-Based Neural Network Design for Associative Learning. In Proceedings of the 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Chengdu, China, 9–12 March 2021; IEEE: Chengdu, China, 2021; pp. 1–3. [Google Scholar]
  92. Yang, X.; Fang, Y.; Yu, Z.; Wang, Z.; Zhang, T.; Yin, M.; Lin, M.; Yang, Y.; Cai, Y.; Huang, R. Nonassociative Learning Implementation by a Single Memristor-Based Multi-Terminal Synaptic Device. Nanoscale 2016, 8, 18897–18904. [Google Scholar] [CrossRef] [PubMed]
  93. Zhao, B.; Xiao, M.; Shen, D.; Zhou, Y.N. Heterogeneous Stimuli Induced Nonassociative Learning Behavior in ZnO Nanowire Memristor. Nanotechnology 2020, 31, 125201. [Google Scholar] [CrossRef] [PubMed]
  94. Hong, Q.; Yan, R.; Wang, C.; Sun, J. Memristive Circuit Implementation of Biological Nonassociative Learning Mechanism and Its Applications. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 1036–1050. [Google Scholar] [CrossRef] [PubMed]
  95. Sun, J.; Zhao, L.; Wen, S.; Wang, Y. Memristive Circuit Design of Nonassociative Learning under Different Emotional Stimuli. Electronics 2022, 11, 3851. [Google Scholar] [CrossRef]
  96. Pei, Y.; Zhou, Z.; Chen, A.P.; Chen, J.; Yan, X. A Carbon-Based Memristor Design for Associative Learning Activities and Neuromorphic Computing. Nanoscale 2020, 12, 13531–13539. [Google Scholar] [CrossRef]
  97. Tuma, T.; Pantazi, A.; Le Gallo, M.; Sebastian, A.; Eleftheriou, E. Stochastic Phase-Change Neurons. Nat. Nanotechnol. 2016, 11, 693–699. [Google Scholar] [CrossRef]
  98. Kaneko, Y.; Nishitani, Y.; Ueda, M. Ferroelectric Artificial Synapses for Recognition of a Multishaded Image. IEEE Trans. Electron Devices 2014, 61, 2827–2833. [Google Scholar] [CrossRef]
  99. Nishitani, Y.; Kaneko, Y.; Ueda, M.; Morie, T.; Fujii, E. Three-Terminal Ferroelectric Synapse Device with Concurrent Learning Function for Artificial Neural Networks. J. Appl. Phys. 2012, 111, 124108. [Google Scholar] [CrossRef]
  100. Lequeux, S.; Sampaio, J.; Cros, V.; Yakushiji, K.; Fukushima, A.; Matsumoto, R.; Kubota, H.; Yuasa, S.; Grollier, J. A Magnetic Synapse: Multilevel Spin-Torque Memristor with Perpendicular Anisotropy. Sci. Rep. 2016, 6, 31510. [Google Scholar] [CrossRef] [Green Version]
  101. Rzeszut, P.; Chȩciński, J.; Brzozowski, I.; Ziȩtek, S.; Skowroński, W.; Stobiecki, T. Multi-State MRAM Cells for Hardware Neuromorphic Computing. Sci. Rep. 2022, 12, 7178. [Google Scholar] [CrossRef]
  102. Upadhyay, N.K.; Jiang, H.; Wang, Z.; Asapu, S.; Xia, Q.; Joshua Yang, J. Emerging Memory Devices for Neuromorphic Computing. Adv. Mater. Technol. 2019, 4, 1800589. [Google Scholar] [CrossRef] [Green Version]
  103. Jiang, H.; Han, L.; Lin, P.; Wang, Z.; Jang, M.H.; Wu, Q.; Barnell, M.; Yang, J.J.; Xin, H.L.; Xia, Q. Sub-10 Nm Ta Channel Responsible for Superior Performance of a HfO2 Memristor. Sci. Rep. 2016, 6, 28525. [Google Scholar] [CrossRef] [Green Version]
  104. Wu, W.; Wu, H.; Gao, B.; Deng, N.; Yu, S.; Qian, H. Improving Analog Switching in HfOx-Based Resistive Memory with a Thermal Enhanced Layer. IEEE Electron Device Lett. 2017, 38, 1019–1022. [Google Scholar] [CrossRef]
  105. Xi, Y.; Tang, J.; Gao, B.; Xu, F.; Li, X.; Lu, Y.; Qian, H.; Wu, H. The Impact of Thermal Enhance Layers on the Relaxation Effect in Analog RRAM. IEEE Trans. Electron Devices 2022, 69, 4254–4258. [Google Scholar] [CrossRef]
  106. Feng, Y.; Huang, P.; Zhao, Y.; Shan, Y.; Zhang, Y.; Zhou, Z.; Liu, L.; Liu, X.; Kang, J. Improvement of State Stability in Multi-Level Resistive Random-Access Memory (RRAM) Array for Neuromorphic Computing. IEEE Electron Device Lett. 2021, 42, 1168–1171. [Google Scholar] [CrossRef]
  107. Lin, Y.H.; Wang, C.H.; Lee, M.H.; Lee, D.Y.; Lin, Y.Y.; Lee, F.M.; Lung, H.L.; Wang, K.C.; Tseng, T.Y.; Lu, C.Y. Performance Impacts of Analog ReRAM Non-Ideality on Neuromorphic Computing. IEEE Trans. Electron Devices 2019, 66, 1289–1295. [Google Scholar] [CrossRef]
  108. Yu, Z.; Wang, Z.; Kang, J.; Fang, Y.; Chen, Y.; Cai, Y.; Huang, R. Early-Stage Fluctuation in Low-Power Analog Resistive Memory: Impacts on Neural Network and Mitigation Approach. IEEE Electron Device Lett. 2020, 41, 940–943. [Google Scholar] [CrossRef]
  109. Milo, V.; Glukhov, A.; Pérez, E.; Zambelli, C.; Lepri, N.; Mahadevaiah, M.K.; Quesada, E.P.-B.; Olivo, P.; Wenger, C.; Ielmini, D. Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits. IEEE Trans. Electron Devices 2021, 68, 3832–3837. [Google Scholar] [CrossRef]
  110. Seok, J.Y.; Song, S.J.; Yoon, J.H.; Yoon, K.J.; Park, T.H.; Kwon, D.E.; Lim, H.; Kim, G.H.; Jeong, D.S.; Hwang, C.S. A Review of Three-Dimensional Resistive Switching Cross-Bar Array Memories from the Integration and Materials Property Points of View. Adv. Funct. Mater. 2014, 24, 5316–5339. [Google Scholar] [CrossRef]
  111. Wang, I.T.; Chang, C.C.; Chiu, L.W.; Chou, T.; Hou, T.H. 3D Ta/TaOx/TiO2/Ti Synaptic Array and Linearity Tuning of Weight Update for Hardware Neural Network Applications. Nanotechnology 2016, 27, 365204. [Google Scholar] [CrossRef] [Green Version]
  112. Adam, G.C.; Hoskins, B.D.; Prezioso, M.; Merrikh-Bayat, F.; Chakrabarti, B.; Strukov, D.B. 3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications. IEEE Trans. Electron Devices 2017, 64, 312–318. [Google Scholar] [CrossRef]
  113. Li, C.; Han, L.; Jiang, H.; Jang, M.H.; Lin, P.; Wu, Q.; Barnell, M.; Yang, J.J.; Xin, H.L.; Xia, Q. Three-Dimensional Crossbar Arrays of Self-Rectifying Si/SiO2/Si Memristors. Nat. Commun. 2017, 8, 15666. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  114. Wang, T.Y.; Meng, J.L.; Rao, M.Y.; He, Z.Y.; Chen, L.; Zhu, H.; Sun, Q.Q.; Ding, S.J.; Bao, W.Z.; Zhou, P.; et al. Three-Dimensional Nanoscale Flexible Memristor Networks with Ultralow Power for Information Transmission and Processing Application. Nano Lett. 2020, 20, 4111–4120. [Google Scholar] [CrossRef] [PubMed]
  115. Huo, Q.; Song, R.; Lei, D.; Luo, Q.; Wu, Z.; Wu, Z.; Zhao, X.; Zhang, F.; Li, L.; Liu, M. Demonstration of 3D Convolution Kernel Function Based on 8-Layer 3D Vertical Resistive Random Access Memory. IEEE Electron Device Lett. 2020, 41, 497–500. [Google Scholar] [CrossRef]
  116. Wei, Z.; Takagi, T.; Kanzawa, Y.; Katoh, Y.; Ninomiya, T.; Kawai, K.; Muraoka, S.; Mitani, S.; Katayama, K.; Fujii, S.; et al. Demonstration of High-Density ReRAM Ensuring 10-Year Retention at 85 °C Based on a Newly Developed Reliability Model. In Proceedings of the 2011 International Electron Devices Meeting, Washington, DC, USA, 5–7 December 2011; IEEE: Washington, DC, USA, 2011; pp. 31.4.1–31.4.4. [Google Scholar]
  117. Huang, Y.; Hu, Y.; Ren, S. Low-Power Anisotropic Molecular Electronic Memristors. Appl. Mater. Today 2022, 29, 101569. [Google Scholar] [CrossRef]
  118. Kumar, S.; Davila, N.; Wang, Z.; Huang, X.; Strachan, J.P.; Vine, D.; Kilcoyne, A.L.D.; Nishi, Y.; Williams, R.S. Spatially Uniform Resistance Switching of Low Current, High Endurance Titanium-Niobium-Oxide Memristors. Nanoscale 2017, 9, 1793–1798. [Google Scholar] [CrossRef] [Green Version]
  119. Yang, J.J.; Zhang, M.X.; Strachan, J.P.; Miao, F.; Pickett, M.D.; Kelley, R.D.; Medeiros-Ribeiro, G.; Williams, R.S. High Switching Endurance in TaOx Memristive Devices. Appl. Phys. Lett. 2010, 97, 232102. [Google Scholar] [CrossRef] [Green Version]
  120. Strukov, D.B. Endurance-Write-Speed Tradeoffs in Nonvolatile Memories. Appl. Phys. A Mater. Sci. Process. 2016, 122, 302. [Google Scholar] [CrossRef] [Green Version]
  121. Ravi, V.; Prabaharan, S.R.S. Fault Tolerant Adaptive Write Schemes for Improving Endurance and Reliability of Memristor Memories. AEU Int. J. Electron. Commun. 2018, 94, 392–406. [Google Scholar] [CrossRef]
  122. Titirsha, T.; Song, S.; Das, A.; Krichmar, J.; Dutt, N.; Kandasamy, N.; Catthoor, F. Endurance-Aware Mapping of Spiking Neural Networks to Neuromorphic Hardware. IEEE Trans. Parallel Distrib. Syst. 2022, 33, 288–301. [Google Scholar] [CrossRef]
  123. John, R.A.; Milozzi, A.; Tsarev, S.; Brönnimann, R.; Boehme, S.C.; Wu, E.; Shorubalko, I.; Kovalenko, M.V.; Ielmini, D. Ionic-Electronic Halide Perovskite Memdiodes Enabling Neuromorphic Computing with a Second-Order Complexity. Sci. Adv. 2022, 8, eade0072. [Google Scholar] [CrossRef]
  124. Kumar, S.; Williams, R.S.; Wang, Z. Third-Order Nanocircuit Elements for Neuromorphic Engineering. Nature 2020, 585, 518–523. [Google Scholar] [CrossRef]
Electronics 12 03298 g001 550
Figure 1. (a) Two-terminal memristor structure based Pt/TiO2/Pt. (b) I-V curve of threshold memristor [24].
Figure 1. (a) Two-terminal memristor structure based Pt/TiO2/Pt. (b) I-V curve of threshold memristor [24].
Electronics 12 03298 g001
Electronics 12 03298 g002 550
Figure 2. (a) Schematic diagram of a single memristor connected to presynaptic and postsynaptic neuron. (b) Synaptic cross array composed of single memristor.
Figure 2. (a) Schematic diagram of a single memristor connected to presynaptic and postsynaptic neuron. (b) Synaptic cross array composed of single memristor.
Electronics 12 03298 g002
Electronics 12 03298 g003 550
Figure 3. (a) Schematic diagram of two-memristor-two-resistor synaptic circuit. (b) Schematic diagram of four-memristor synaptic circuit.
Figure 3. (a) Schematic diagram of two-memristor-two-resistor synaptic circuit. (b) Schematic diagram of four-memristor synaptic circuit.
Electronics 12 03298 g003
Electronics 12 03298 g004 550
Figure 4. Presented spintronic memristor-based synaptic circuit.
Figure 4. Presented spintronic memristor-based synaptic circuit.
Electronics 12 03298 g004
Electronics 12 03298 g005 550
Figure 5. (a) IV Characteristics of Multi-resistance Analog memristor [27]; (b) Comparison of the electronic synapses of metal oxide memristor and biological synapses.
Figure 5. (a) IV Characteristics of Multi-resistance Analog memristor [27]; (b) Comparison of the electronic synapses of metal oxide memristor and biological synapses.
Electronics 12 03298 g005
Electronics 12 03298 g006 550
Figure 6. (a) The schematic presents the transition from STM to LTM through rehearsal. The current response to (b) 10 and (c) 30 presynaptic pulses, implementing STM and LTM behaviors, respectively. (d) Device conductance is stimulated by different pulse numbers [34].
Figure 6. (a) The schematic presents the transition from STM to LTM through rehearsal. The current response to (b) 10 and (c) 30 presynaptic pulses, implementing STM and LTM behaviors, respectively. (d) Device conductance is stimulated by different pulse numbers [34].
Electronics 12 03298 g006
Electronics 12 03298 g007 550
Figure 7. STDP implementation. (a) Pulse scheme for realizing STDP. (b) STDP rule for memristor [49].
Figure 7. STDP implementation. (a) Pulse scheme for realizing STDP. (b) STDP rule for memristor [49].
Electronics 12 03298 g007
Electronics 12 03298 g008 550
Figure 8. (a) Synaptic weight as a function of pulse number and interval [61]. (b) Synaptic weight response to a set of postsynaptic spike trains with the frequency sequence [62].
Figure 8. (a) Synaptic weight as a function of pulse number and interval [61]. (b) Synaptic weight response to a set of postsynaptic spike trains with the frequency sequence [62].
Electronics 12 03298 g008
Electronics 12 03298 g009 550
Figure 9. (a) PPF on hippocampal cells in guinea pig [63]. (b) PPF is observed on CeO2/Nb−SrTiO3 heterojunction memristors [62].
Figure 9. (a) PPF on hippocampal cells in guinea pig [63]. (b) PPF is observed on CeO2/Nb−SrTiO3 heterojunction memristors [62].
Electronics 12 03298 g009
Electronics 12 03298 g010 550
Figure 10. Learning experience behavior of the zinc oxide/poly (3-hexylthiophene) heterojunction-based device [65].
Figure 10. Learning experience behavior of the zinc oxide/poly (3-hexylthiophene) heterojunction-based device [65].
Electronics 12 03298 g010
Electronics 12 03298 g011 550
Figure 11. (a) Schematic diagram of SBT synaptic circuit. (b) Construction process of biological associative memory.
Figure 11. (a) Schematic diagram of SBT synaptic circuit. (b) Construction process of biological associative memory.
Electronics 12 03298 g011
Electronics 12 03298 g012 550
Figure 12. (a) Construction process of biological nonassociative memory. (b) Synaptic circuit of memristor for nonassociative memory.
Figure 12. (a) Construction process of biological nonassociative memory. (b) Synaptic circuit of memristor for nonassociative memory.
Electronics 12 03298 g012
Table
Table 1. The biological factors that significant memristors can act.
Table 1. The biological factors that significant memristors can act.
YearMaterialsSTM to LTMSTDPSRDPPPFLearning
Experience		Associative LearningNonassociative LearningRef.
2020ZnO//////Yes[93]
2022Zinc Oxide/Poly (3-hexylthiophene)Yes/YesYesYes//[65]
2022CarbonYesYes///Yes/[96]
2022AlOx/HfOxYesYes/YesYes//
2023CeO2/Nb−SrTiO3/YesYesYesYes//[62]
2023Pd/La:HfO2/La2/3Sr1/3MnO3YesYes/Yes/Yes/[64]
Table
Table 2. Ways to improve the stability and reliability of memristor.
Table 2. Ways to improve the stability and reliability of memristor.
YearLevelQuestionMethodRef.
2017
2022		DeviceRelaxation effectAdding thermal-enhanced layers[104,105]
2021ArrayExcessive oxygen vacancies generated by the abrupt SET processTriangular pulse for the programming[106]
2019AlgorithmDrifting conductanceConductance tracking method[107]
2020AlgorithmElectron hopping assisted by traps (vacancies)Optimizing the neural network weight noise tolerance[108]
2021SystemLimited precision of conductanceThe tradeoff of neural network accuracy, size, and current consumption[109]
Table
Table 3. The current development status of the 3D crossbar.
Table 3. The current development status of the 3D crossbar.
YearMaterialScaleLayer3D StructureCompatible with CMOSAnalog/DigitalRef.
2016Ta/TaOx/TiO2/Ti4 × 42Stacking/Analog (50 states)[111]
2016Pt/Al2O3/TiO2−x/TiN/Pt10 × 102 YesAnalog (16 states)[112]
2017p-Si/SiO2/n-Si (self-rectifying)8 × 85 (max)StackingYesDigital (104 ON/OFF)[113]
2020Pt/HfAlOx/TaN6 × 63Stacking/Analog[114]
2020HfO2/TaOx8 × 328Vertical/Digital[115]
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content.

Share and Cite

MDPI and ACS Style

Li, Y.; Su, K.; Chen, H.; Zou, X.; Wang, C.; Man, H.; Liu, K.; Xi, X.; Li, T. Research Progress of Neural Synapses Based on Memristors. Electronics 2023, 12, 3298. https://doi.org/10.3390/electronics12153298

AMA Style

Li Y, Su K, Chen H, Zou X, Wang C, Man H, Liu K, Xi X, Li T. Research Progress of Neural Synapses Based on Memristors. Electronics. 2023; 12(15):3298. https://doi.org/10.3390/electronics12153298

Chicago/Turabian Style

Li, Yamin, Kang Su, Haoran Chen, Xiaofeng Zou, Changhong Wang, Hongtao Man, Kai Liu, Xin Xi, and Tuo Li. 2023. "Research Progress of Neural Synapses Based on Memristors" Electronics 12, no. 15: 3298. https://doi.org/10.3390/electronics12153298

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop