# Characteristics of Offset Corbino Thin Film Transistor: A Physical Model

^{*}

## Abstract

**:**

## 1. Introduction

_{BD}) of TFT. One is to use materials of wide bandgap (E

_{g}> 3 eV) as the active layer, such as ZnO, IGZO and Ga

_{2}O

_{3}[5,6]. The other is to use specific structures such as drain offset [7,8,9] or field-plate (FP) structure [10,11]. The drain offset structure uses the ungated channel region to undertake much of the drain voltage, which reduces the voltage on the gated channel region [12,13]. While in the field-plate structure, a plate located above the gate edge near the drain offset region is used to suppress the current collapse phenomena by restraining the gate edge electric field concentration [14,15,16,17,18]. Sometimes, these two approaches are used together to increase the breakdown voltage of TFT [19,20].

_{2}O

_{3}as the gate dielectric layer to fabricate HVTFT, which demonstrated a gate breakdown voltage (V

_{BD_G}) of 45–50 V and a source-drain channel breakdown voltage (V

_{BD_SD}) exceeding 100 V [24]. Chow, et al., fabricated rectangular a-Si HVTFT to operate voltage above 300 V with an offset of 6 μm [25]. Li, et al., reported a-IGZO HVTFT with a high breakdown voltage of over 1.1 kV [26] and over 1.9 kV [27]. The results in the literature show that breakdown voltage can be improved if the drain offset structure is used. Although the drain offset structure can improve the breakdown voltage, it may reduce the operating current and occupy a larger area. The saturation currents of rectangular TFTs with offset at the drain side are approximately the same, and at the source side decrease with offset length [12,21].

## 2. Device Structure of Model

_{cir}and R

_{cor}, and the inner and outer radiuses of the offset region are denoted as R

_{oir}and R

_{oor}. Due to the coupling of the gated channel region and offset region in offset Corbino TFT, R

_{cir}= R

_{oor}can be found in Figure 1a,c, and R

_{oir}= R

_{cor}can be found in Figure 1b,d. In addition, we label the length of the gated channel region and offset region as L

_{channel}(R

_{cor}–R

_{cir}) and L

_{offset}(R

_{oor}–R

_{oir}). Although SGOD TFTs and DOGS TFTs (also for DGOS TFTs and SOGD TFTs) have the same L

_{channel}and L

_{offset}, their gated channel and offset region differ due to the rotation symmetry of Corbino TFTs, as shown in the top views. In addition, the direction of the drain current is also different for SGOD TFTs and DOGS TFTs. The charge carriers are injected from the outer electrode to the inner electrode in SGOD TFTs but from the inner electrode to the outer electrode in DOGS TFTs.

## 3. Results and Discussion

#### 3.1. Formula

_{D}is the drain current, W and L refer to the width and length of the gated semiconductor, μ

_{1}is the carrier mobility in the gated semiconductors, ${C}_{i}={\epsilon}_{ox}/{t}_{ox}$ with ${\epsilon}_{ox}$ as permittivity and ${t}_{ox}$ as the thickness of the insulating layer below or above the gated semiconductor, and V

_{G}and V

_{th}refer to the gate voltage and threshold voltage. The threshold voltage is the gate voltage axis intercept of the linear extrapolation of the transfer characteristics at its maximum first derivative (slope) point [38]. V

_{D}is the drain voltage, V

_{1}is the potential at the end of gated semiconductors, and V

_{S}is the source potential as transistors with organic or low-dimensional semiconductors usually have injection barriers, unlike MOSFETs. Therefore, the values of V

_{1}and V

_{S}depend on the specific structure of FETs with non-trivial gates. In addition, we derived the following Equation to describe the current of the offset region, calculated as the area of non-gated semiconductor times the current density [37]: ${I}_{D}={Q}_{0}S{\mu}_{2}{\left({V}_{D}-{V}_{0}-{V}_{1}\right)}^{\alpha}/{d}^{\beta}$. Here, ${Q}_{0}$ is the charge density factor, and μ

_{2}is the carrier mobility in the non-gated semiconductors. S and d are the current area and length of the non-gated semiconductor. V

_{0}is the onset voltage for the non-gated channel (due to injection barriers or trap states). The injection barriers or trap states are related to the material of the active layer and metal electrode. Therefore, V

_{0}is mainly related to material properties and film quality rather than transistor bias. Here, V

_{0}is omitted for simplicity and could be included by replacing V

_{D}with V

_{D}–V

_{0}whenever needed. $\alpha $ is referred to as the charge transport factor and $\beta \approx 2\alpha -1$. The current density of the offset region is the product of ${Q}_{0}$ and ${\mu}_{2}{\left({V}_{D}-{V}_{0}-{V}_{1}\right)}^{\alpha}/{d}^{\beta}$. Reference [35] shows our detailed analysis of ${Q}_{0}$, $\alpha $ and $\beta $ according to different conduction mechanisms, including Ohmic, SCLC, and other cases. According to the continuity principle, the current of the gated channel is equal to that of the offset region, so we have

_{0}as the intrinsic carrier concentration and q as the elementary charge. From this perspective, we can derive the physical model of Drain-Offset Corbino TFT and Source-Offset Corbino TFT by analyzing Vs and V

_{1}in the corresponding situation.

_{offset}as the non-gated offset region resistance, and the source serves as the reference point of the potential and is grounded instead of biased. We assume the contact in thin film-based transistors between the electrode and active layer is ohmic contact, and thus V

_{S}is set as zero. Thus, we approximate ${V}_{1}+{V}_{S}$ and ${V}_{1}-{V}_{S}$ to V

_{1}and obtain ${V}_{1}={V}_{D}-{I}_{D}{R}_{offset}$. By considering a radial electric field in Corbino TFT, the width-to-length ratio of Corbino TFT without offset can be written as $2\pi /\mathrm{ln}\left({R}_{2}/{R}_{1}\right)$ according to previous work [39], where R

_{2}and R

_{1}refer to the radius of the outer electrode and inner electrode. For Corbino offset resistance, we have:

_{offset}and t are the width and thickness of the offset semiconductor. It is worth noting that there are no geometric concepts of length and width in Corbino TFT with offset structure. Equation (3) considers that the geometrical factor of rectangular resistance is ${L}_{offset}/{W}_{offset}$, while Corbino-type offset resistance is $\mathrm{ln}\left({R}_{\mathrm{oor}}/{R}_{oir}\right)/2\pi $. We know the gate voltage, V

_{G}, could affect the carrier of the gated channel and the offset region. However, the Debye length in various semiconductors with low resistance at room temperature is in tens of nanometers. As a result, it is reasonable to ignore the effect of gate voltage when considering the resistance of the offset region of the micron scale.

_{n}refers to the transconductance coefficient of the device as $\pi {\mu}_{1}{C}_{i}/\mathrm{ln}\left({R}_{cor}/{R}_{cir}\right)$. Equation (4) is rewritten into:

_{Dsat}) and saturation drain voltage (V

_{Dsat}) when $\partial {I}_{D}/\partial {V}_{D}=0$.

_{D}[37], similar to the classic doped MOSFETs [40]. For simplicity, we use a simple one-dimensional depletion model in doped MOSFET, i.e., $\mathsf{\Delta}L\cong \sqrt{2\epsilon \left({V}_{D}-{V}_{Dsat}\right)/q{N}^{*}}$. Here ε is the permittivity of the active layer, and N* is the effective dopant concentration. Unlike rectangular TFT, the position of the depletion region is significant for Corbino TFT, which is with drain near the inner or outer electrode. Therefore, we have the drain current in the saturation region in Corbino TFT with the drain at the inner electrode or outer electrode, respectively:

_{1}is V

_{D,}and V

_{S}is I

_{D}R

_{offset}in Equation (2). Therefore, we have the current-voltage (I-V) Equation of Source-Offset Corbino TFT in the linear region as:

_{Dsat}, V

_{Dsat}, and the drain current of Source-Offset Corbino TFT in the saturation region could be obtained likewise.

_{Dsat}) and the saturation drain current (I

_{Dsat}). The position and length of the offset region are the key parameters influencing the electrical characteristics. Therefore, the derived equations listed in Table 1 are helpful when designing offset Corbino TFT for specific applications.

_{offset}, and the results are shown in Figure 3. The corresponding structure parameters and other parameters used are given in Table 2. For Drain-Offset Corbino TFTs, the V

_{Dsat}increases with L

_{offset}. The I

_{Dsat}of DOGS TFT remains unchanged independent of L

_{offset}. The I

_{Dsat}of SGOD TFT is larger for longer L

_{offset}because of larger K

_{n}for longer L

_{offset}in SGOD TFT with the same L

_{channel}. For Source-Offset Corbino TFT, including DGOS TFT and SOGD TFT, I

_{Dsat}decreases with longer L

_{offset}while V

_{Dsat}remains unchanged. As shown in Figure 3, the primary influence of offset in Drain-Offset Corbino TFT is to increase the saturation voltage, and in Source-Offset Corbino TFT is to reduce the saturation current. The offset in Drain-Offset Corbino TFT undertakes a great part of drain voltage, and thus Drain-Offset Corbino TFT can operate at higher drain voltage. The SGOD TFT can endure higher potential due to a larger R

_{offset}compared with DOGS TFT with the same L

_{offset}and L

_{channel}. Our derived model can also demonstrate the influence of the inherent conductivity of semiconductors (such as n

_{0}, μ

_{1}and μ

_{2}) on I

_{D}

_{.}When the semiconductor is more conductive, the I

_{D}of offset Corbino TFT is higher. The influence of offset on drain current shown in transfer characteristics is the same as in output characteristics, so we only show the relevant output curves in the manuscript for a concise presentation.

_{offset}and L

_{channel}, the I

_{Dsat}of Source-Offset Corbino TFT is smaller than that of Drain-Offset Corbino TFT because the offset in Source-Offset Corbino TFT reduces the saturation current. The DGOS TFT has the lowest I

_{Dsat}, and the SOGD TFT has the second lowest I

_{Dsat}. In the formula of I

_{Dsat}of Source-Offset Corbino TFT, the value of R

_{offset}exists as a denominator. The V

_{Dsat}and I

_{Dsat}of SGOD TFT are greater than those of DOGS TFT on account of larger K

_{n}and R

_{offset}, which can be explained directly using the formula of V

_{Dsat}and I

_{Dsat}of Drain-Offset Corbino TFT shown in Table 1.

_{D}in the saturation region shown in Table 1 gives direct quantitative theoretical proof. Channel length modulation in the device leads to variations in the I

_{D}of offset Corbino TFT in the saturation region. As shown in Table 1, the I

_{D}of offset Corbino TFT in the saturation region relates to the R

_{cor}and R

_{cir}. In our one-dimensional depletion model, the same drain voltage increment in the saturation region results in the same $\mathsf{\Delta}L$. In the case of R

_{cor}to R

_{cir}ratio greater than one and with the same $\mathsf{\Delta}L$, our Equations show that I

_{D}of Corbino TFT with the drain at the outer electrode in the saturation region increases more slowly than that of Corbino TFT with the drain at the inner electrode. The output conductance is expressed as $\partial {I}_{D}/\partial {V}_{D}$, so the Corbino TFT with the drain at the outer electrode has higher output resistance than Corbino TFT with the drain at the inner electrode.

#### 3.2. Simulation

_{TD}and N

_{TA}), conduction and valence band tail state slopes (W

_{TD}and W

_{TA}), donor-like and acceptor-like states (N

_{GD}and N

_{GA}) with Gaussian distributions, and their respective full width at half maximums (W

_{GD}and W

_{GA}) are listed in Table 3. The corresponding structure parameters for simulation are the same as the theoretical characteristics plotting, as shown in Table 2.

_{th}= 0 V, C

_{i}= 8.7 × 10

^{−9}F/cm

^{2}, n

_{0}= 5.0 × 10

^{16}cm

^{−3}for the curves of L

_{offset}= 2 μm in Figure 5c,d and n

_{0}= 3.8 × 10

^{15}cm

^{−3}for other fitting curves in Figure 5s and 6, μ

_{2}= 11 cm

^{2}V

^{−1}s

^{−1}for Figure 6 and μ

_{2}= 8 cm

^{2}V

^{−1}s

^{−1}for other fitting curves in Figure 5. Comparing Figure 5 with Figure 3, we found that the simulation results show that the characteristics of the TFT exhibit similar trends when offset length (L

_{offset}) increases. Offset in Drain-Offset Corbino TFT makes no difference to I

_{Dsat}with the same K

_{n}, as shown in Figure 5b. I

_{Dsat}decreases with offset length more rapidly in Source-Offset Corbino TFT, as shown in Figure 5c,d. Longer L

_{offset}significantly increases V

_{Dsat}in Drain-Offset Corbino TFT, as shown in Figure 5a,b. In the same way, we study the effect of the position of the offset region with the same L

_{offset}and L

_{channel}by TCAD simulation, as shown in Figure 6. The feature and trend of V

_{Dsat}and I

_{Dsat}with offset in Figure 6 are consistent with Figure 4, although their exact values are different. We can conclude that the TCAD simulation results prove the correctness of the formula of offset Corbino TFT we derived.

#### 3.3. Experimental Verification

_{2}was deposited by plasma-enhanced chemical vapor deposition (PECVD). A 50-nm-thick IGZO film was sputtered and etched to form the active layer on top of the gate insulator. Both the source and drain electrodes were formed by sputtering and lift-off processes. A SiO

_{2}passivation layer was deposited by PECVD and etched by reactive ion etching (RIE) to form contact holes. We fill the contact holes with indium tin oxide (ITO) by magnetron sputtering and patterning it via a lift-off process. There are two annealing steps in device fabrication. IGZO film was annealed by thermal oxidation at 350 °C for 1 hour in N

_{2}atmosphere, and ITO was annealed by thermal oxidation at 470 °C for 2 hours in air atmosphere.

_{offset}, i.e., 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 75, 100 μm. The optical images of two fabricated devices are shown in Figure 7. The electrical characteristics of the a-IGZO Corbino TFT were measured using a semiconductor analyzer (Agilent B1500A). The typical experimental and theoretical fitting output characteristics of fabricated offset Corbino TFTs are shown in Figure 8. The theoretical fitting parameters different from Table 2 are V

_{th}= −1 V, n

_{0}= 3.8 × 10

^{15}cm

^{−3}, μ

_{2}= 2.7 cm

^{2}V

^{−1}s

^{−1}, C

_{i}= 6.4 × 10

^{−9}F/cm

^{2}, μ

_{1}= 2.7 cm

^{2}V

^{−1}s

^{−1}for Figure 8a and μ

_{1}= 4 cm

^{2}V

^{−1}s

^{−1}for Figure 8b–d and Figure 9. Different positions of offset region in offset Corbino TFT with the same L

_{offset}and L

_{channel}are also studied in the experiment. The experimental and theoretical fitting output characteristics of different types of offset Corbino TFT with the same L

_{offset}and L

_{channel}are shown in Figure 9.

_{Dsat}increases with the L

_{offset}. SGOD TFT with longer L

_{offset}has larger I

_{Dsat}, and different DOGS TFT almost have the same I

_{Dsat}despite different L

_{offset}. Despite the slight variance in I

_{Dsat}, the experimental results verify the theoretical derivation and TCAD simulation, where different DOGS TFT have identical I

_{Dsat}for different values of L

_{offset}. For Source-Offset Corbino TFT, experimental TFTs with longer L

_{offset}have smaller I

_{Dsat}. In addition, the V

_{Dsat}of experimental Source-Offset Corbino TFTs is almost the same despite different L

_{offset}, as demonstrated in the formula. In Figure 9, the regulation of V

_{Dsat}and I

_{Dsat}with offset is the same as expected from the theoretical formula and simulation. Overall, the experiment results indicate that our physical model of offset Corbino TFT is reasonable.

## 4. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Song, Y.H.; Kim, K.B.; Hwang, C.S.; Park, D.J.; Lee, J.H.; Kang, K.Y.; Hur, J.H.; Jang, J. Active-matrix field-emission display based on a CNT emitter and a-Si TFTs. J. Soc. Inf. Disp.
**2005**, 13, 241–244. [Google Scholar] [CrossRef] - Marette, A.; Poulin, A.; Besse, N.; Rosset, S.; Briand, D.; Shea, H. Flexible zinc–tin oxide thin film transistors operating at 1 kV for integrated switching of dielectric elastomer actuators arrays. Adv. Mater.
**2017**, 29, 1700880. [Google Scholar] [CrossRef] [PubMed] - Karpelson, M.; Wei, G.-Y.; Wood, R.J. Driving high voltage piezoelectric actuators in microrobotic applications. Sens. Actuators A
**2012**, 176, 78–89. [Google Scholar] [CrossRef] - Zhang, Y.; Mei, Z.; Wang, T.; Huo, W.; Cui, S.; Liang, H.; Du, X. Flexible transparent high-voltage diodes for energy management in wearable electronics. Nano Energy
**2017**, 40, 289–299. [Google Scholar] [CrossRef] - Galazka, Z.; Uecker, R.; Irmscher, K.; Albrecht, M.; Klimm, D.; Pietsch, M.; Brützam, M.; Bertram, R.; Ganschow, S.; Fornari, R. Czochralski growth and characterization of β-Ga
_{2}O_{3}single crystals. Cryst. Res. Technol.**2010**, 45, 1229–1236. [Google Scholar] [CrossRef] - Hasegawa, H.; Kawabe, U.; Aita, T.; Ishiba, T. Single crystal growth of layered perovskite metal oxides. Jpn. J. Appl. Phys.
**1987**, 26, L673. [Google Scholar] [CrossRef] - Seki, S.; Kogure, O.; Tsujiyama, B. Leakage current characteristics of offset-gate-structure polycrystalline-silicon MOSFET’s. IEEE Electron Device Lett.
**1987**, 8, 434–436. [Google Scholar] [CrossRef] - Unagami, T. High-voltage poly-Si TFTs with multichannel structure. IEEE Trans. Electron Devices
**1988**, 35, 2363–2367. [Google Scholar] [CrossRef] - Huang, T.-Y.; Lewis, A.; Wu, I.-W.; Chiang, A.; Bruce, R. New intra-gate-offset high-voltage thin-film transistor with misalignment immunity. Electron. Lett.
**1989**, 25, 544–545. [Google Scholar] [CrossRef] - Huang, T.-Y.; Wu, I.-W.; Lewis, A.G.; Chiang, A.; Bruce, R.H. A simpler 100-V polysilicon TFT with improved turn-on characteristics. IEEE Electron Device Lett.
**1990**, 11, 244–246. [Google Scholar] [CrossRef] - Huang, T.-Y.; Wu, I.-W.; Lewis, A.; Chiang, A.; Bruce, R. Device sensitivity of field-plated polysilicon high-voltage TFTs and their application to low-voltage operation. IEEE Electron Device Lett.
**1990**, 11, 541–543. [Google Scholar] [CrossRef] - Park, C.; Billah, M.M.; Siddik, A.B.; Lee, S.; Han, B.; Jang, J. High Voltage Amorphous InGaZnO TFT with F Doped Drain Offset Structure. IEEE Electron Device Lett.
**2021**, 42, 1476–1479. [Google Scholar] [CrossRef] - Wu, M.-H.; Lin, H.-C.; Li, P.-W. Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation. Jpn. J. Appl. Phys.
**2019**, 58, 066502. [Google Scholar] [CrossRef] - Saito, W.; Kakiuchi, Y.; Nitta, T.; Saito, Y.; Noda, T.; Fujimoto, H.; Yoshioka, A.; Ohno, T.; Yamaguchi, M. Field-plate structure dependence of current collapse phenomena in high-voltage GaN-HEMTs. IEEE Electron Device Lett.
**2010**, 31, 659–661. [Google Scholar] [CrossRef] - Saito, W.; Nitta, T.; Kakiuchi, Y.; Saito, Y.; Tsuda, K.; Omura, I.; Yamaguchi, M. On-resistance modulation of high voltage GaN HEMT on sapphire substrate under high applied voltage. IEEE Electron Device Lett.
**2007**, 28, 676–678. [Google Scholar] [CrossRef] - Zhang, P.; Zhao, S.-L.; Hou, B.; Wang, C.; Zheng, X.-F.; Ma, X.-H.; Zhang, J.-C.; Hao, Y. Improvement of the off-state breakdown voltage with field plate and low-density drain in AlGaN/GaN high-electron mobility transistors. Chin. Phys. B
**2015**, 24, 037304. [Google Scholar] [CrossRef] - Saito, W.; Nitta, T.; Kakiuchi, Y.; Saito, Y.; Tsuda, K.; Omura, I.; Yamaguchi, M. Suppression of dynamic on-resistance increase and gate charge measurements in high-voltage GaN-HEMTs with optimized field-plate structure. IEEE Trans. Electron Devices
**2007**, 54, 1825–1830. [Google Scholar] [CrossRef] - Dora, Y.; Chakraborty, A.; Mccarthy, L.; Keller, S.; DenBaars, S.; Mishra, U. High breakdown voltage achieved on AlGaN/GaN HEMTs with integrated slant field plates. IEEE Electron Device Lett.
**2006**, 27, 713–715. [Google Scholar] [CrossRef] - Huo, W.; Liang, H.; Lu, Y.; Han, Z.; Zhu, R.; Sui, Y.; Wang, T.; Mei, Z. Dual-active-layer InGaZnO high-voltage thin-film transistors. Semicond. Sci. Technol.
**2021**, 36, 065021. [Google Scholar] [CrossRef] - Yang, G.; Li, M.; Yu, Z.; Xu, Y.; Sun, H.; Liu, S.; Sun, W.; Wu, W. High-Voltage a-IGZO TFTs With the Stair Gate-Dielectric Structure. IEEE Trans. Electron Devices
**2021**, 68, 4462–4466. [Google Scholar] [CrossRef] - Karim, K.S.; Servati, P.; Nathan, A. High voltage amorphous silicon TFT for use in large area applications. Microelectron. J.
**2004**, 35, 311–315. [Google Scholar] [CrossRef] - Martin, R.A.; Da Costa, V.M.; Hack, M.; Shaw, J.G. High-voltage amorphous silicon thin-film transistors. IEEE Trans. Electron Devices
**1993**, 40, 634–644. [Google Scholar] [CrossRef] - Unagami, T.; Kogure, O. High-voltage TFT fabricated in recrystallized polycrystalline silicon. IEEE Trans. Electron Devices
**1988**, 35, 314–319. [Google Scholar] [CrossRef] - Yu, M.-J.; Lin, R.-P.; Chang, Y.-H.; Hou, T.-H. High-Voltage Amorphous InGaZnO TFT With Al
_{2}O_{3}High-k Dielectric for Low-Temperature Monolithic 3-D Integration. IEEE Trans. Electron Devices**2016**, 63, 3944–3949. [Google Scholar] [CrossRef] - Chow, E.M.; Lu, J.P.; Ho, J.; Shih, C.; De Bruyker, D.; Rosa, M.; Peeters, E. High voltage thin film transistors integrated with MEMS. Sens. Actuators A
**2006**, 130, 297–301. [Google Scholar] [CrossRef] - Li, X.; Liu, C.; Liu, C.; Ou, H.; She, J.; Deng, S.; Chen, J. Kilo-voltage thin-film transistors for driving nanowire field emitters. IEEE Electron Device Lett.
**2020**, 41, 405–408. [Google Scholar] [CrossRef] - Li, X.; Liu, C.; Kong, J.; Ou, H.; She, J.; Deng, S.; Chen, J. Widely Adjusting the Breakdown Voltages of Kilo-voltage Thin Film Transistors. IEEE Electron Device Lett.
**2022**, 43, 240–243. [Google Scholar] [CrossRef] - Hong, W.-C.; Ku, C.-J.; Li, R.; Abbaslou, S.; Reyes, P.; Wang, S.-Y.; Li, G.; Lu, M.; Sheng, K.; Lu, Y. MgZnO high voltage thin film transistors on glass for inverters in building integrated photovoltaics. Sci. Rep.
**2016**, 6, 34169. [Google Scholar] [CrossRef] - Hong, W.-C.; Zhang, Y.; Wang, S.-Y.; Li, Y.; Alim, N.; Du, X.; Mei, Z.; Lu, Y. ZnO flexible high voltage thin film transistors for power management in wearable electronics. J. Vac. Sci. Technol. B Nanotechnol. Microelectron. Mater. Process. Meas. Phenom.
**2018**, 36, 050601. [Google Scholar] [CrossRef] - Mativenga, M.; Jun, H.; Choe, Y.; Um, J.G.; Jang, J. Circular structure for high mechanical bending stability of a-IGZO TFTs. IEEE J. Electron Devices Soc.
**2017**, 5, 453–457. [Google Scholar] [CrossRef] - Huo, W.; Mei, Z.; Sui, Y.; Han, Z.; Wang, T.; Liang, H.; Du, X. Flexible transparent InGaZnO thin-film transistors on muscovite mica. IEEE Trans. Electron Devices
**2019**, 66, 2198–2201. [Google Scholar] [CrossRef] - Mativenga, M.; Ha, S.H.; Geng, D.; Kang, D.H.; Mruthyunjaya, R.K.; Heiler, G.N.; Tredwell, T.J.; Jang, J. Infinite output resistance of Corbino thin-film transistors with an amorphous-InGaZnO active layer for large-area AMOLED displays. IEEE Trans. Electron Devices
**2014**, 61, 3199–3205. [Google Scholar] [CrossRef] - Joo, H.-J.; Shin, M.-G.; Kwon, S.-H.; Jeong, H.-Y.; Jeong, H.-S.; Kim, D.-H.; Jin, X.; Song, S.-H.; Kwon, H.-I. High-gain complementary inverter based on Corbino p-type tin monoxide and n-type indium-gallium-zinc oxide thin-film transistors. IEEE Electron Device Lett.
**2019**, 40, 1642–1645. [Google Scholar] [CrossRef] - Geng, R.; Gong, Y. High performance active image sensor pixel design with circular structure oxide TFT. J. Semicond.
**2019**, 40, 022402. [Google Scholar] [CrossRef] - Deegan, R.D.; Bakajin, O.; Dupont, T.F.; Huber, G.; Nagel, S.R.; Witten, T.A. Capillary flow as the cause of ring stains from dried liquid drops. Nature
**1997**, 389, 827–829. [Google Scholar] [CrossRef] - Zhang, L.; Liu, H.; Zhao, Y.; Sun, X.; Wen, Y.; Guo, Y.; Gao, X.; Di, C.a.; Yu, G.; Liu, Y. Inkjet printing high-resolution, large-area graphene patterns by coffee-ring lithography. Adv. Mater.
**2012**, 24, 436–440. [Google Scholar] [CrossRef] - Liu, C.; Li, X.; Luo, Y.; Wang, Y.; Hu, S.; Liu, C.; Liang, X.; Zhou, H.; Chen, J.; She, J. How Materials and Device Factors Determine the Performance: A Unified Solution for Transistors with Nontrivial Gates and Transistor–Diode Hybrid Integration. Adv. Sci.
**2021**, 9, 2104896. [Google Scholar] [CrossRef] - Qiang, L.; Yao, R. A new definition of the threshold voltage for amorphous InGaZnO thin-film transistors. IEEE Trans. Electron Devices
**2014**, 61, 2394–2397. [Google Scholar] [CrossRef] - Byun, Y.H.; Den Boer, W.; Yang, M.; Gu, T. An amorphous silicon TFT with annular-shaped channel and reduced gate-source capacitance. IEEE Trans. Electron Devices
**1996**, 43, 839–841. [Google Scholar] [CrossRef] - Neamen, D.A. Semiconductor Physics and Devices: Basic Principles, 4th ed.; McGraw-Hill: New York, NY, USA, 2003; pp. 446–447. [Google Scholar]

**Figure 1.**The three-dimensional cross-sectional structures and top views of offset Corbino TFTs. (

**a**) SGOD TFT. (

**b**) DOGS TFT. (

**c**) DGOS TFT. (

**d**) SOGD TFT. Insets of (

**a**–

**d**) are the corresponding schematic of offset Corbino TFTs.

**Figure 2.**The cross-section image of (

**a**) Drain-Offset Corbino TFT, and (

**b**) Source-Offset Corbino TFT. The schematic diagram of the equivalent circuit of (

**c**) Drain-Offset Corbino TFT, and (

**d**) Source-Offset Corbino TFT.

**Figure 3.**The theoretical output characteristics of offset Corbino TFT when V

_{G}is 15 V: (

**a**) SGOD TFT. (

**b**) DOGS TFT. (

**c**) DGOS TFT. (

**d**) SOGD TFT. Insets of (

**a**–

**d**) are the corresponding schematic of offset Corbino TFT.

**Figure 4.**The theoretical output characteristics of different offset Corbino TFTs with the same L

_{offset}of 10 μm and the same L

_{channel}of 175 μm when V

_{G}is 15 V.

**Figure 5.**The simulation output characteristics of offset Corbino TFT when V

_{G}is 15 V: (

**a**) SGOD TFT. (

**b**) DOGS TFT. (

**c**) DGOS TFT. (

**d**) SOGD TFT. Insets of (

**a**–

**d**) are the corresponding schematic of offset Corbino TFT. The TCAD simulated data are drawn in dots, and relevant results using the derived Equations are drawn in curves.

**Figure 6.**The simulation output characteristics of different offset Corbino TFTs with the same L

_{offset}of 10 μm and the same L

_{channel}of 175 μm when V

_{G}is 15 V. The TCAD simulated data are drawn in dots, and fitting results by using the derived Equations are drawn in curves.

**Figure 7.**Optical images of fabricated a-IGZO Corbino TFTs: (

**a**) without offset; and (

**b**) with an offset of 10 μm.

**Figure 8.**The experimental output characteristics of offset Corbino TFT when V

_{G}is 4 V: (

**a**) SGOD TFT. (

**b**) DOGS TFT. (

**c**) DGOS TFT. (

**d**) SOGD TFT. Insets of (

**a**–

**d**) are the corresponding schematic of offset Corbino TFT. The dots are experimental data, and the curves are the fitting results using the derived Equations.

**Figure 9.**The experimental output characteristics of different offset Corbino TFTs with the same L

_{offset}of 10 μm and the same L

_{channel}of 175 μm when V

_{G}is 4 V. The dots are experimental data, and the curves are the fitting results by using the derived Equations.

**Table 1.**The current-voltage equations of four types of offset Corbino TFT and other important parameters.

Drain-Offset Corbino TFT | ||

SGOD TFT | DOGS TFT | |

V_{1} | ${V}_{D}-{I}_{D}{R}_{offset}$ | |

V_{S} | 0 | |

I_{D} in the linear region | $\frac{{V}_{D}-{V}_{GT}}{{R}_{offset}}+\frac{\sqrt{{\left(2{K}_{n}{R}_{offset}{V}_{GT}+1\right)}^{2}-4{K}_{n}{R}_{offset}{V}_{D}}-1}{2{K}_{n}{R}_{offset}^{2}}$ | |

I_{D} in the saturation region | ${I}_{Dsat}\frac{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}}\right)}{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}+\mathsf{\Delta}L}\right)}$ | ${I}_{Dsat}\frac{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}}\right)}{\mathrm{ln}\left(\frac{{R}_{cor}-\mathsf{\Delta}L}{{R}_{cir}}\right)}$ |

V_{Dsat} | ${K}_{n}{R}_{offset}{V}_{GT}^{2}+{V}_{GT}$ | |

I_{Dsat} | ${K}_{n}{V}_{GT}^{2}$ | |

Source-Offset Corbino TFT | ||

DGOS TFT | SOGD TFT | |

V_{1} | V_{D} | |

V_{S} | ${I}_{D}{R}_{offset}$ | |

I_{D} in the linear region | $\frac{{V}_{GT}}{{R}_{offset}}-\frac{\sqrt{4{K}_{n}^{2}{R}_{offset}^{2}{\left({V}_{GT}-{V}_{D}\right)}^{2}+4{K}_{n}{R}_{offset}{V}_{GT}+1}-1}{2{K}_{n}{R}_{offset}^{2}}$ | |

I_{D} in the saturation region | ${I}_{Dsat}\frac{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}}\right)}{\mathrm{ln}\left(\frac{{R}_{cor}-\mathsf{\Delta}L}{{R}_{cir}}\right)}$ | ${I}_{Dsat}\frac{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}}\right)}{\mathrm{ln}\left(\frac{{R}_{cor}}{{R}_{cir}+\mathsf{\Delta}L}\right)}$ |

V_{Dsat} | ${V}_{GT}$ | |

I_{Dsat} | $\frac{{V}_{GT}}{{R}_{offset}}-\frac{\sqrt{4{K}_{n}{R}_{offset}{V}_{GT}+1}-1}{2{K}_{n}{R}_{offset}^{2}}$ |

**Table 2.**The structure parameters and other parameters of offset Corbino TFT used for theoretical characteristics plotting.

Parameter | Value | Parameter | Value |
---|---|---|---|

${V}_{th}\left(\mathrm{V}\right)$ | 1.0 | ${n}_{0}\left({\mathrm{cm}}^{-3}\right)$ | 1.5 × 10^{17} |

${\mu}_{1}\left({\mathrm{cm}}^{2}{\mathrm{V}}^{-1}{\mathrm{s}}^{-1}\right)$ | 5.0 | ${\mu}_{2}\left({\mathrm{cm}}^{2}{\mathrm{V}}^{-1}{\mathrm{s}}^{-1}\right)$ | 5.0 |

${C}_{i}\left(\mathrm{F}/{\mathrm{cm}}^{2}\right)$ | 5.0 × 10^{−8} | $\mathrm{t}\left(\mathrm{cm}\right)$ | 0.05 × 10^{−4} |

$\epsilon \left(\mathrm{F}/\mathrm{cm}\right)$ | 8.5 × 10^{−13} | ${N}^{*}\left({\mathrm{cm}}^{-3}\right)$ | 1.0 × 10^{17} |

${L}_{offset}\left(\mathsf{\mu}\mathrm{m}\right)$ | 0, 5, 10, 15, 20 | ${L}_{channel}$($\mathsf{\mu}\mathrm{m}$) | 175 |

Inner electrode radius ($\mathsf{\mu}\mathrm{m}$) | 75 |

Parameter | Value | Parameter | Value |
---|---|---|---|

${\mathrm{N}}_{\mathrm{TA}}\left({\mathrm{cm}}^{-3}{\mathrm{eV}}^{-1}\right)$ | 5.5 ×${10}^{18}$ | ${\mathrm{N}}_{\mathrm{GA}}\left({\mathrm{cm}}^{-3}{\mathrm{eV}}^{-1}\right)$ | 1.85 ×${10}^{16}$ |

${\mathrm{W}}_{\mathrm{TA}}\left({\mathrm{eV}}^{-1}\right)$ | 0.015 | ${\mathrm{W}}_{\mathrm{GA}}\left({\mathrm{eV}}^{-1}\right)$ | 0.3 |

${\mathrm{N}}_{\mathrm{TD}}\left({\mathrm{cm}}^{-3}{\mathrm{eV}}^{-1}\right)$ | 5.5 ×${10}^{18}$ | ${\mathrm{N}}_{\mathrm{GD}}\left({\mathrm{cm}}^{-3}{\mathrm{eV}}^{-1}\right)$ | 1.225 ×${10}^{17}$ |

${\mathrm{W}}_{\mathrm{TD}}\left({\mathrm{eV}}^{-1}\right)$ | 0.22 | ${\mathrm{W}}_{\mathrm{GD}}\left({\mathrm{eV}}^{-1}\right)$ | 0.13 |

Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |

© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Kong, J.; Liu, C.; Li, X.; Ou, H.; She, J.; Deng, S.; Chen, J.
Characteristics of Offset Corbino Thin Film Transistor: A Physical Model. *Electronics* **2023**, *12*, 2195.
https://doi.org/10.3390/electronics12102195

**AMA Style**

Kong J, Liu C, Li X, Ou H, She J, Deng S, Chen J.
Characteristics of Offset Corbino Thin Film Transistor: A Physical Model. *Electronics*. 2023; 12(10):2195.
https://doi.org/10.3390/electronics12102195

**Chicago/Turabian Style**

Kong, Jiaquan, Chuan Liu, Xiaojie Li, Hai Ou, Juncong She, Shaozhi Deng, and Jun Chen.
2023. "Characteristics of Offset Corbino Thin Film Transistor: A Physical Model" *Electronics* 12, no. 10: 2195.
https://doi.org/10.3390/electronics12102195