Design of the Buck Converter without Inductor Current Sensor

Abstract

This paper proposes a novel control scheme for the buck converter without an inductor current sensor. The architecture of the proposed buck converter is simple and suitable for integration and mass production. It employs an output-voltage-measurement method to determine the switch ON time; therefore, the current sensor is not required. The design specification targets the application with a standard battery power source to generate the low voltages for low-power MCU or ASIC. The load current range aims for several hundred milliamps. The proposed control scheme is analyzed and simulated by SIMPLIS. The control scheme, theoretical analysis, circuit realization, contributions, advantages, and simulation results are presented in this paper. Furthermore, the circuit can be fabricated by a 0.35 μm CMOS process.

1. Introduction

With the rapid development of portable devices, DC-DC converters with fast transient responses and low-power consumption have attracted much attention. Moreover, the power management integrated circuit (PMIC) [1] can provide specific voltages for the system. Therefore, the high-efficiency DC-DC converters play an essential role in electronic systems [2,3,4]. Buck converters now have different control schemes for different applications, such as current mode control (CMC) [5] and voltage mode control (VMC) [6]. In Figure 1, VMC is the simplest control method, which uses the error amplifier to regulate the output. On the contrary, CMC uses fast/slow paths to regulate the output. Therefore, the CMC transient response is better than the VMC one [7].

Many schemes have been proposed based on CMC, including constant on time (COT) and adaptive on time (AOT). In AOT and COT, AOT has a better transient response than COT [8]. For both COT and AOT, the switching frequency is not fixed, which varies according to the load conditions and output/input voltages. In addition, both COT and AOT have high efficiency in light load. Therefore, the switching frequency is lower in light load, and the switching loss is reduced to improve efficiency. However, this feature will make the electromagnetic interference (EMI) filter hard to design. Generally, the switching converter needs an EMI filter to prevent the coupled impact on the surrounding electrical circuits. Therefore, the constant switching frequency provides a good solution for the EMI issue [9,10].

From the perspective of the transient response, CMC is better than VMC. However, the inductor current sensor is required in CMC, as shown in Figure 1. In the next section, we will investigate various current sensors.

The organizational structure of the paper is as follows: Section 2 is an investigation on various current sensors. Section 3 presents the proposed control scheme and implementation. Section 4 introduces the theoretical analysis. Section 5 shows the SIMPLIS simulation results. Finally, conclusions are given in Section 6.

2. Current Sensor Investigation

Many kinds of current sensors are proposed in [11,12,13,14,15]. If the system requires isolation, the Hall sensor is a candidate. Nevertheless, the Hall-effect current sensors are susceptible to EMI [11]. Therefore, Aiello et al. [12] proposed an EMI-immune contactless current sensor using a split-drain MOS transistor (MagFET). Moreover, a Hall-effect-based current sensor immune to EMI was proposed in [13]. Low-cost isolation current sensors are proposed in [14,15], namely a giant magnetoresistance-effect-based sensor. These contactless current sensors are often used for electrical isolation requirements. Therefore, they may not be suitable for PMIC.

In contrast to the current contactless sensor, sensor-less solutions are more popular and are proposed in [16,17,18,19,20,21,22,23,24,25,26,27]. In Figure 2, the sensing method is straightforward [16,17]. The inductor current information can be obtained through the series resistor, R_dc. The drawback is the additional power consumption in R_dc.

In Figure 3, the sensing method uses a low-pass filter set with a parallel inductor, L, [18]. The drawback of this method is that the low-pass filter cannot be integrated into silicon.

In Figure 4, the active current-sensing (ACS) circuit is proposed to detect the inductor current [19]. However, the drawback is that the sensing points suffer from significant voltage variation, increasing circuit design complexity.

Similarly, in Figure 5, the proposed scheme can improve the transient response [20]. However, the sensing points are still the same as [19].

In Figure 6, the other ACS circuit is employed to sense the voltage, V_x [21]. However, the V_x has a large voltage swing, which increases the input range requirement of the ACS circuit.

In Figure 7, the virtual inductor current circuit [21] is proposed to improve the drawback of [19,20,21]. However, this scheme has two drawbacks: (a) the switching frequency is not constant, and (b) the virtual inductor sensor needs the input/output voltages to determine the switch S₁ ON time (T_ON). That means that two sets of voltage-to-current converters are required. Perhaps, the hardware may be further saved. Similarly, [23] proposed the dual loops mechanism buck converter, which uses the input/output voltages to generate T_ON, instead of the current sensor.

In Figure 8, the COT buck converter uses an average current-sensing scheme to detect the load current [24]. The drawback is that the circuit that duplicates entire inductor current components increases current consumption as current replication parts increase.

In Figure 9, an AOT-based buck converter with transient-acceleration loops and V-cubic techniques is proposed in [25]. It utilized the techniques of adaptive on-time and V-cubic to stabilize the switching frequency and promote conversion efficiency. Moreover, it is necessary to add a slope-compensation circuit to accelerate the transient response and decrease the transient voltage.

In Figure 10, a low-noise fast-transient-response continuous-time delta-sigma-modulator (CT-DSM) buck converter is proposed in [26]. The transient-accelerated circuits use a DCR current-sensing circuit and hysteresis-voltage-controlled (HVC) circuit to speed up the transient response. Therefore, the sensing method is similar to [18].

A high-efficiency fast transient constant on-time (COT) control DC–DC buck converter with current reused current sensor is proposed in [27]. The current reused current sensor enhances the loop stability and improves the power conversion efficiency at light load.

In this paper, a novel scheme is proposed to simplify circuits further. The contribution and expected outcomes of the designed converter can be listed as (a) simple architecture: it is accessible to implementation, (b) suitable for mass production, (c) high design flexibility: the converter provides more flexible design parameters for various application, (d) the constant switching frequency feature dramatically reduces the difficulty in solving the EMI issue, and (e) good transient response.

3. Proposed Control Scheme, Implementation, and Advantages

3.1. Proposed Control Scheme

Figure 11 shows the proposed control scheme. The function blocks are described as follows:

(A)

Proposed adaptive T_ON controller

Through the V_o, the proposed adaptive T_ON controller module generates a ramp signal and decides T_ON. The differences from the previous works are listed as follows:

(a)

In [22], the T_ON is decided by the virtual inductor current circuit, which senses the V_in and V_o. Compared with [22], this work eliminates the function of the current sensor. In addition, this work has the feature of the constant switching frequency.

(b)

In [23], the T_ON is decided by the voltage (V_in-V_o). Unlike [23], the T_ON is decided only by V_o. Moreover, the constant switching frequency mechanism is not the function of V_o. From the methodology perspective, the proposed scheme is different from [22]. This paper proposes another solution for the T_ON decision. It can further reduce the hardware effort.

(c)

In [20], it uses the optimum-damping controller to sense the voltages of the inductor (Figure 5). Compared with [20], this paper dramatically reduces the hardware effort.

(B)

Constant frequency mechanism [28]

The work of this module mainly makes the switching frequency constant. The module is composed of a frequency detector.

(C)

DRIVER:

It mainly provides sufficient driving capacity to drive the MOS switches, S₁ and S₂.

3.2. Implementation and Operating Principle

The implementation of the proposed converter is shown in Figure 12. First, the proposed adaptive T_ON controller architecture is straightforward and suitable for integration. Second, the circuits do not require a special process to fabricate. Third, the converter uses the constant frequency mechanism module to keep the switching frequency constant instead of PLL. The operation steps of the converter are described as follows (Figure 12):

• Inductor-charging phase (the switch S₁ is ON, and the switch S₂ is OFF):
  The switch S₁ ON time is labeled as T_ON. In Figure 12, the T_ON is decided by V_CMP and V_ramp. Once V_ramp reaches V_CMP, the T_ON is decided. T_ON is the function of V_ramp. The relationships between T_ON, V_ramp, V_FB, and V_o are as follows:

  (a)

  T_ON is the function of V_ramp.

  (b)

  V_ramp is the function of V_FB.

  (c)

  The relationship between V_o and V_FB is a resistor division.

  From (a)~(c), we can conclude that T_ON is the function of V_o. The larger V_o is, the shorter T_ON is.
• Inductor-discharging phase (the switch S₁ is OFF, and the switch S₂ is ON):
  The switch S₁ OFF time (T_OFF) is decided by V_EA1 and V_ramp2. Once V_ramp2 reaches V_EA1, the T_OFF is decided. The relationship between V_EA1 and T_OFF is the larger V_EA1 and the longer T_OFF. In addition, the V_EA1 is controlled by the constant frequency mechanism module.
• When the system is stable, the V_FB and the V_freq are almost equal to the V_REF and the V_REF2, respectively. The V_CMP and the V_EA1 will eventually converge to their stable voltages. The fundamental waveforms of the converter are drawn in Figure 13.

The purpose of different colors in Figure 12 is to clearly show the main function of the proposed adaptive T_ON controller.

3.3. Proposed Converter Advantages and Disadvantages

3.3.1. Advantages

The proposed converter has four advantages, which are listed below:

(A)

The whole circuit does not require a particular process to fabricate.

Because the whole circuit does not need special semiconductor devices to implement, there is no need for a specific process in fabrication.

(B)

There is no special layout/matching issue in the circuit.

Layout is an important step in fabrication. Fortunately, there is no special matching issue in the proposed circuits.

(C)

The whole circuit is robust.

Each crucial parameter has considered its design margin and the process variation.

(D)

The feature of constant switching frequency dramatically reduces the difficulty of solving the EMI issue.

The variable switching frequency makes the electromagnetic interference (EMI) filter hard to design.

3.3.2. Disadvantages

The proposed converter has four disadvantages, which are listed below:

(A)

The proposed converter has a slight switching frequency drift. The switching frequency is approximately 1.01–1.05 MHz. The variation is about 3.5%. However, this slight variation is acceptable for solving the EMI issue.

(B)

The regulation capability is poor at the input voltage of 3.6 V and the output voltage of 1.0 V. The maximum ripple voltage of the output is about 11.2 mV. The performance of the boundary conditions is barely acceptable.

4. Theoretical Analysis

4.1. Mathematical Model

In this section, the mathematical model of the buck converter will be illustrated. It can assist in confirming stability. Many studies [29,30,31,32] about modeling ways are proposed. Chou et al. [22,28] presents the design procedure in detail. The mathematical model is built through Reference [32] in this paper. In Figure 14, the open-loop transfer function of the converter can be expressed as Equation (1). Equation (2) represents the G_P(s) of the buck converter. A(s) represents the error amplifier composed of the transconductance, g_m, and the compensation network.

In Figure 14, the K_i, R_O, R₃, and C₁ are the key parameters, and the relations are shown in Equations (1)–(3). The purpose of different colors in Figure 14 is to clearly find the function blocks in Figure 12. According to [29,30], in Equation (4), we locate the zero, w_z, at the output pole of the buck converter. The pole, w_p, is a free design parameter. Therefore, we choose a suitable w_p to make the system stable. The design procedure is described in [22,28] and is verified by MathCAD and SIMPLIS.

$$\mathrm{T}\left(\mathrm{s}\right)=\frac{{\mathrm{V}}_{\mathrm{o}}\left(\mathrm{s}\right)}{{\mathrm{V}}_{\mathrm{i}}\left(\mathrm{s}\right)}={\mathrm{G}}_{\mathrm{P}}\left(\mathrm{s}\right)·\mathrm{A}\left(\mathrm{s}\right)$$

(1)

$${\mathrm{G}}_{\mathrm{P}}\left(\mathrm{s}\right)=\frac{{\mathrm{V}}_{\mathrm{FB}}\left(\mathrm{s}\right)}{{\mathrm{V}}_{\mathrm{i}}\left(\mathrm{s}\right)}=\frac{1}{{\mathrm{K}}_{\mathrm{i}}}·\frac{1}{1+\frac{\mathrm{s}}{\mathrm{Q}·\mathsf{\omega }}+\frac{{\mathrm{s}}^2}{{\mathsf{\omega }}^2}}·\frac{{\mathrm{R}}_{\mathrm{LOAD}}\left({\mathrm{R}}_{\mathrm{ESR}}{\mathrm{C}}_{\mathrm{o}}\mathrm{s}+1\right)}{\left({\mathrm{R}}_{\mathrm{LOAD}}+{\mathrm{R}}_{\mathrm{ESR}}\right){\mathrm{C}}_{\mathrm{o}}\mathrm{s}+1}$$

(2)

$$\mathrm{A}\left(\mathrm{s}\right)=\frac{{\mathrm{V}}_{\mathrm{o}}\left(\mathrm{s}\right)}{{\mathrm{V}}_{\mathrm{FB}}\left(\mathrm{s}\right)}={\mathrm{g}}_{\mathrm{m}}·{\mathrm{R}}_{\mathrm{o}}·\frac{\left(1+\frac{\mathrm{s}}{{\mathrm{w}}_{\mathrm{z}}}\right)}{\left(1+\frac{\mathrm{s}}{{\mathrm{w}}_{\mathrm{p}}}\right)}$$

(3)

$${\mathrm{w}}_{\mathrm{z}}=\frac{1}{\left({\mathrm{R}}_{\mathrm{LOAD}}+{\mathrm{R}}_{\mathrm{ESR}}\right){\mathrm{C}}_{\mathrm{o}}}\approx \frac{1}{{\mathrm{R}}_{\mathrm{LOAD}}·{\mathrm{C}}_{\mathrm{o}}},{ \mathrm{f}}_{\mathrm{z}}=\frac{{\mathrm{w}}_{\mathrm{z}}}{2\mathsf{\pi }}$$

(4)

where ${\mathrm{K}}_{\mathrm{i}}$ is the gain of the T_ON ramp generator, $\mathsf{\omega }=\raisebox{1ex}{$\mathsf{\pi }$}\!\left/ \!\raisebox{-1ex}{${\mathrm{T}}_{\mathrm{on}}$}\right., \mathrm{Q}=\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$\mathsf{\pi }$}\right.$, ${\mathrm{w}}_{\mathrm{z}}=\frac{1}{{\mathrm{R}}_3·{\mathrm{C}}_1}$, ${\mathrm{w}}_{\mathrm{p}}=\frac{1}{{\mathrm{R}}_{\mathrm{o}}·{\mathrm{C}}_1}$.

4.2. Design Parameters and Components Selection

By references [22,28], we can use MathCAD to calculate the design parameters of the converter. Compared with previous works, the external components and load conditions have not changed. The design parameters of this work are listed in

Table 1. Design parameters and component value.

Symbol	Value	Unit
RLOAD	3.6	Ω
Co	10	μF
L	4.7	μH
RESR	5	mΩ
Ro	1	MΩ
R3	251	kΩ
C1	220	p F

.

5. Simulation Results

5.1. SIMPLIS Schematic

The SIMPLIS schematic of the proposed converter is built and shown in Figure 15.

5.2. Transient Performance

The transient response at the load transition is shown in Figure 16 under the test conditions of 0.1–0.5 A load current and 3.3 V/1.8 V input/output voltage. The recovery time means that the output voltage recovers to 1% of 1.8 V at the load change.

In Figure 16, the step-up and step-down recovery times are 1.8 μs and 1.5 μs, respectively. From the results, the recovery time is less than 2 μs. In addition, Figure 16 shows that the overshoot/undershoot voltages are 21 mV/30 mV.

The converter specifies that V_in is 3.0–3.6 V and V_o is 1.0–2.5 V. Figure 17 illustrates that the maximum ripple voltage is 11.2 mV at the input voltage of 3.6 V and the output voltage of 1.0 V.

5.3. Load Regulation

The load regulation follows Equation (5). This specification indicates the output regulation capability when the load changes. The load regulation should be as small as possible for a good design. In this paper, the simulation conditions are the input/output voltages are 3.3 V/1.8 V, and the load current varies from 0.5 A to 0.1 A. As shown in Figure 18, the load regulation is nearly 0% by Equation (5).

$$\mathrm{Load} \mathrm{Regulation} =\frac{{\mathrm{V}}_{\mathrm{o}@0.1\mathrm{A} \mathrm{load} \mathrm{current}}-{\mathrm{V}}_{\mathrm{o}@0.5\mathrm{A} \mathrm{load} \mathrm{current}}}{{\mathrm{V}}_{\mathrm{o}@0.5\mathrm{A} \mathrm{load} \mathrm{current}}}·100\%$$

(5)

where ${\mathrm{V}}_{\mathrm{o}@0.5\mathrm{A} \mathrm{load} \mathrm{current}}$ is the voltage at the 0.5 A load current, and ${\mathrm{V}}_{\mathrm{o}@0.1\mathrm{A} \mathrm{load} \mathrm{current}}$ is the voltage at the 0.1 A load current.

5.4. Line Regulation

The line regulation follows Equation (6). This specification indicates the output regulation capability when the supply voltage changes. The line regulation should be as small as possible for a good design. In this paper, the supply voltage varies from 3.0 V to 3.6 V. Therefore, by Equation (6), the simulation value is close to 0.

$$\mathrm{Line} \mathrm{Regulation}=\frac{{\mathsf{\Delta }\mathrm{V}}_{\mathrm{o}}}{\Delta {\mathrm{V}}_{\mathrm{in}}}·100\%$$

(6)

where ΔV_in is the variation of the input voltage, and ΔV_o is the variation of the output voltage.

5.5. Switching Frequency Regulation

Figure 19 illustrates the switching frequency of the different output voltages. The results show that: (a) At the output voltage of 1.0–2.5 V, the switching frequency is approximately 1.011–1.046 MHz. (b) The switching frequency is about 1.02 MHz at an output voltage of 1.8 V. (c) The frequency variation is roughly 3.5%. It has a slight frequency drift that results from the EA1 of the constant frequency mechanism module in Figure 12. The EA1 cannot regulate well the V_freq to the V_REF2 at the lower output voltage. The lower V_o leads to the lower V_freq, slightly weakening the regulation ability.

5.6. Performance List

The performance of the novel buck converter is summarized in

Table 2. Performance Summary.

Parameter	Conditions	Min.	Typ.	Max.	Unit
Input voltage		3.0		3.6	V
Output voltage		1.0		2.5	V
Output ripple	Vin = 3.6 V, Vo = 2.5 V			11	mV
Load current		100		500	mA
Inductor	DCR *: 30 mΩ		4.7		μH
Output capacitor	ESR: 5 mΩ		10		μF
Switching frequency	Vin = 3.0~3.6 V, Vo = 1.0~2.5 V		1		MHz
Recovery time (step-up)	Vo = 1.8 V Load current: 100 mA to 500 mA		1.8		μs
Recovery time (step-down)	Vo = 1.8 V Load current: 500 mA to 100 mA		1.5		μs
Overshoot voltage	Vin = 3.3 V, Vo = 1.8 V		21		mV
Undershoot voltage	Vin = 3.3 V, Vo = 1.8 V		30		mV

* DCR: the DC resistance of inductor.

. From 100 mA to 500 mA load current, the recovery time is less than 2 μs. The converter has a good performance under the supply voltage of 3.0–3.6 V and the output voltage of 1.8 V. Finally, the performance comparisons with reported converters are listed in

Table 3. Performance Comparisons with Reported Converters.

References	2020 [33]	2022 [23]	2021 [22]	2021 [28]	This Work
Results	simulation	simulation	simulation	simulation	simulation
Control scheme	AOT	dual loops	AOT	AOT	AOT
Process (μm)	0.18	0.35 **	0.35 *	0.18 *	0.35 *
Input voltage (V)	3.3–5.0	3.0–3.6	3.0–3.6	3.0–3.6	3.0–3.6
Output voltage (V)	1.8	1.0–2.5	1.0–2.5	1.0–2.5	1.0–2.5
Inductor (μH)	1.5	4.7	4.7	4.7	4.7
Output capacitor (μF)	20	10	10	10	10
Switching frequency (MHz)	1	1	1	1	1
Switching frequency variation (%)	N/A	1	N/A	1	3.5
Max. load current (mA)	2000	500	500	500	500
Load current step (mA)	800	400	400	400	400
Undershoot/Overshoot (mV)	13/14	16/12	23/26	20/24	21/30
Recovery time (μs) (rise/fall)	6/2	1.5/0.9	1.98/1.6	1.69/1.62	1.8/1.5
References	2022 [26]	2021 [19]	2022 [25]	2021 [27]	2021 [24]
Results	measurement	measurement	measurement	measurement	measurement
Control scheme	2nd CT-DSM **	Hysteretic PLL	AOT	COT	COT
Process (μm)	0.18	0.35	0.18	0.13	0.18
Input voltage (V)	3.0–3.6	3.3–3.6	1.6–2.2	7–15	4.25–15
Output voltage (V)	1–2.5	0.9–2.5	0.4–1.2	5–7	1.1
Inductor (μH)	2.2	4.7	0.33	2.2	0.47
Output capacitor (μF)	10	10	10	10	47 × 3
Switching frequency (MHz)	10	1	3	2	0.5–1.25
Switching frequency variation (%)	N/A	1	N/A	N/A	42
Max. load current (mA)	N/A	600	500	2000	5000
Load current step (mA)	400	400	450	2000	5000
Undershoot/Overshoot (mV)	25/22	30/60	20/20	85/72	30/15.7
Recovery time (μs) (rise/fall)	3/3	2.6/2.2	3.4/3.6	3/2.7	80/45
References	2019 [34]	2018 [35]	2018 [36]	2021 [37]	2019 [20]
Results	measurement	measurement	measurement	measurement	measurement
Control scheme	Current-Mode Hysteretic	Current-Mode Hysteretic	Quasi-V2 hysteretic	DBC ***	DBC ***
Process (μm)	0.065	0.35	0.35	0.35	0.35
Input voltage (V)	3.3	2.7–4.2	3.3	2.8–4	2.5–3.6
Output voltage (V)	0.6–2.0	1.2–1.8	1.5–1.8	1.4–2.5	0.8–2.5
Inductor (μH)	2.2	2.2	2.2	2.2	3.3
Output capacitor (μF)	10	4.7	4.7	10	10
Switching frequency (MHz)	1	0.9	2.0	1	1
Switching frequency variation (%)	N/A	N/A	N/A	N/A	N/A
Max. load current (mA)	1500	600	700	700	600
Load current step (mA)	900	500	510	550	450
Undershoot/Overshoot (mV)	106/87	47/44	38/20	45/40	50/65
Recovery time (μs) (rise/fall)	3.4/3.6	4.7/5.2	2.5/2.6	1.8/1.8	2/2

* This work is system level simulation with SIMPLIS. ** Continuous-time delta-sigma-modulator (CT-DSM). *** dead-beat-controlled (DBC).

. Table 3 shows that the performance is still different even in the same control scheme. The reason comes from the different switching methods and circuit schemes. Generally, the transient response is greatly affected by external components, such as the load capacitor, inductor, and load. Therefore, we need to use the same load conditions for fair comparisons.

In Table 3, we compare this work to the others, make some discussions, and list as follows:

(A)

Compared with [33], the proposed scheme can provide better recovery time.

(B)

In [24,33], the output voltage is a fixed value. However, this work can provide greater flexibility for the output.

(C)

Compared with [23], although the performance on recovery time and switching frequency variation are slightly worse, the control scheme is simple and easy to implement, and these performance differences are not particularly obvious in application.

(D)

Compared with [22], this work can provide an approximately constant switching frequency.

(E)

Compared with [28], the most significant improvement is that the current sensor is not required. In addition, the proposed converter is straightforward.

(F)

Compared with [26], the switching frequency of this work is lower, and the switching loss is reduced. The [26] uses the DCR current-sensing and hysteresis-voltage-controlled (HVC) circuits to speed up the transient response. However, the circuits are more complicated than this work.

(G)

From Table 3, this work has a better transient response than [19,24,25,26,27], probably because this work is the simulation result.

(H)

Compared with [19], this work provides a simple scheme to keep the switching frequency constant. The [19] uses the PLL function block to achieve the switching frequency constant.

(I)

Compared with [25], the proposed scheme provides the output of 1.0–2.5 V. Additionally, [25] can provide a low output voltage of 0.4 V, suitable for low supply power systems. Moreover, [25] can adopt a lower inductor than this work.

(J)

In [24,27], the converters all use the COT control scheme. There is no feature of constant switching frequency in [24]. The [27] uses a current reused current sensor to enhance the loop stability. The [24] experiences a large overshoot/undershoot.

(K)

In [35], a current-mode hysteretic buck converter is presented in which the inductor current is sensed by a resistor-capacitor (RC) network. The sensing method is similar to [18]. (Figure 3) From Table 3, the undershoot/overshoot of the converter [34] is larger than 50 mV. In [35], the transient response of the converter is relatively poor.

(L)

Compared with [20,34,35,36,37], the proposed converter can provide a good transient response.

6. Conclusions

This paper proposes a novel buck converter with no current sensor. The performance of this converter is not inferior to that of CMC. The converter uses sensing of the V_o to generate the T_ON instead of the current sensor. There are four advantages to this converter. First, the whole circuit does not require a special process to fabricate. Second, there is no special layout-matching issue in the circuit. Third, the whole circuit is robust. Each crucial parameter has considered its design margin and process variation. Forth, the feature of constant switching frequency dramatically reduces the difficulty of solving the EMI issue. The design spec of the buck converter prototype is an output voltage of 1.0–2.5 V at the in-put voltage of 3.0–3.6 V. The driving capacity of the load current ranges from 100 mA to 500 mA. The scheme is verified by SIMPLIS. The simulation results show that the switching frequency variation is less than 3.5% at the output voltage of 1.0–2.5 V. The recovery time is less than 2 μs during the load change. The proposed converter can be implemented further with a 0.35 μm CMOS process.