Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Abstract

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

1. Introduction

According to reports from the International Technology Roadmap for Semiconductors (ITRS), the testing technology is lagging far behind the design and manufacturing technologies [1,2]. If the tester technology stagnates, the quality and yield will worsen [3,4]. The testing capabilities of the tester and the development speed of the manufacturing technology are different. To ensure the reliability of critical electronic products, strict quality control is required to eliminate all defective parts in the total number of parts; however, owing to the slow development of testing technology, it is becoming increasingly difficult to use existing technology to select highly reliable electronic products. Therefore, suppliers must propose good methods to solve this problem. Currently, in the semiconductor testing industry, retesting is being applied in the production process to improve test results [5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. In the actual test in the test factory, the retest strategy greatly improves the test yield. This paper proposes a new test method (multiplex tests) to improve testing efficiency. The new method involves moving the test guardband (TGB) and extending the test time, retesting the chips that pass the test several times, and repeatedly searching for truly reliable products to increase the test yield. Conversely, we used multiplex testing methods to improve the quality of products. We all know that zero-defect high-quality products (Zero Defect Manufacturing, ZDM) [20,21] are the ultimate goal of all industries. The quality requirements in the biomedical or automotive electronics industries are stringent, with higher safety requirements. Therefore, we used the multiplex testing method to reduce the errors that occur during testing, the mobile test guardband to reduce the generation of killing errors and missing errors, and obtain products with near-zero defects [22,23,24,25,26,27,28]. Multiplex testing can improve the test yield and test quality; however, if the test time and the number of tests are increased, the test cost will gradually increase. Furthermore, when the increased test cost is higher than the increased profit (the profit obtained by expanding the test yield), it will cause a loss of profit. Therefore, we applied a retest strategy to IC testing [29,30,31,32,33] and found an enhanced test procedure (enhanced IC test system (ETS)) that calculates the required test times by improving test yield and test cost. The enhanced solution we propose can avoid directionless retesting. It can save wasted manpower and time and minimizes the cost of testing. We achieved the best balance between increasing profit and increasing test cost using the enhanced test mechanism and the premise of increasing the test yield rate.

2. Integrated Circuit Development Process

IC development procedures were used in this study. The IC development starts from a concept, and this concept is transformed into circuit design, wafer manufacturing, and finally testing (Figure 1).

The designed chip is sent to a wafer factory for manufacturing, and the manufactured chip is then sent to a testing firm for testing and selection. After the IC manufacturing is completed, according to the design specification (DS), the product can be divided into good (G) and bad (B). Manufacturing yield (true yield) Y_m is the percentage of good products in the total (N), that is, Y_m = G/N; After the test, according to the test specifications (TS), the product can be divided into sellable (pass) and unsellable (fail). The test yield Y_t is the percentage of the total (N) that can be sold, that is, Y_t = P/N. Apparently, there are unavoidable errors in the measurement as the test process is not perfect. Moreover, problems in TS, TGB, or the accuracy of the VLSI tester can be encountered. If a test error occurs [34], then the test classification result might differentiate “good” into “fail” (type I error and killing error (α)), similar to the classification of “bad” into “pass” (type II error and missing error (β)). As a result, customers might buy defective (missing error) products.

2.1. Manufacturing Yield (Y_m) Estimation on the Basis of Normal Distribution

During semiconductor manufacturing, owing to uncertain factors in the semiconductor manufacturing environment (Figure 2), the performance of each wafer produced is different. In this paper, it is assumed that the delay time of each chip produced follows a normal distribution; that is, chip(x) = N (x; μ_M, σ_M), with μ_M denoting mean, and σ_M denoting standard deviation.

The manufacturing yield (Y_m) is the probability of the area under the normal curve, between the coordinates x = −∞ and x = DS; that is, P[−∞ < X < DS]. We express this as

$$\begin{array}{l}{\mathrm{Y}}_{\mathrm{m}}(\%)=\mathrm{Manufacturing} \mathrm{Yield}\\ ={{\displaystyle \int }}_{-\infty }^{\mathrm{DS}}\mathrm{Chip}(\mathrm{x})\mathrm{dx}\\ ={{\displaystyle \int }}_{-\infty }^{\mathrm{DS}}\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{x}-{\mathsf{\mu }}_{\mathrm{M}})}^2}{2{\mathsf{\sigma }}_{\mathrm{M}}{}^2}}\mathrm{dx}\\ ={{\displaystyle \int }}_{-\infty }^{\frac{\mathrm{DS}-{\mathsf{\mu }}_{\mathrm{M}}}{{\mathsf{\sigma }}_{\mathrm{M}}}}\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}\mathrm{dx}\\ ={{\displaystyle \int }}_{-\infty }^{\mathrm{Cm}}\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}\mathrm{dx}\end{array}$$

(1)

2.2. Small Process Variations in Semiconductors Have a Major Impact on Manufacturing Yields

Next, we define Cm = (DS − μ_M)/σ_M as the manufacturability index [30]. The higher the Cm value, the better the manufacturing capability is than the design capability and the better the manufacturing yield (Y_m). For example, as shown in Figure 3 and

Table 1. The relationship between process changes and manufacturing yield.

μM (ps)	σM (ps)	DS (ps)	Cm	Ym (%)
1000	60	1165	2.75	99.7
1000	80	1165	2.06	98
1000	100	1165	1.65	95
1000	120	1165	1.38	91.5
1000	140	1165	1.18	88
1000	160	1165	1.03	84.9
1000	180	1165	0.92	82
1000	200	1165	0.83	79.5
1000	220	1165	0.75	77.3
1000	240	1165	0.69	75.4

, DS = 1165 ps, and DUT X ~ N (x; μ_M = 1000 ps, σ_M = 100 ps), then Cm = 1.65; here, we can get the manufacturing yield Y_m = 95%. When σ_M = 200 ps, and DS = 1165 ps, DUT X ~ N (x; μ_M = 1000 ps, σ_M = 200 ps), then Cm = 0.83, and the manufacturing yield Y_m = 79.5%. When σ_M becomes increasingly larger, it means that the greater the manufacturing difference, the worse the manufacturing yield (Y_m). When σ_M = 60 ps, the manufacturing variation is relatively small, DS = 1100 ps, DUT X ~ N (x; μ_M = 1000 ps, σ_M = 60 ps), then Cm = 2.75, we can get the manufacturing yield Y_m = 99.7%. From the above results, we know that when σ_M becomes increasingly smaller (that is, the manufacturing capacity is better than the design capacity), the smaller the difference in manufacturing convenience, the better the manufacturing yield (Y_m) will be. In semiconductor manufacturing, in the same situation of increasingly smaller σ_M, the size of chip components and conductor widths will gradually decrease. The complexity of the chip will double in 18–24 months because the area of the chip component is reduced by half. When the area of the chip is halved, the problem of small changes in the chip electrical parameters will become more serious. Therefore, from the above simulation results, it is understood that process changes have a significant impact on manufacturing yield.

2.3. Test Yield Estimation (Y_t)

In this paper, automated test equipment (ATE) judges whether the DUT is “pass” or “fail” based on the comparison result of two signal timings (Figure 4). If the chip (chip delay time) arrives slower than the signal sent by the tester (X1 > X2), the ATE sends a fail signal and treats the chip as a failure. On the contrary, if the chip (chip delay time) arrives faster than the signal sent by the tester (X1 < X2), a pass signal is sent, and the chip is deemed qualified.

During manufacturing in a wafer factory, besides environmental factors, the tester accuracy during testing also influences the yield and quality. To judge the quality of a chip, the best test circuit is itself; however, a circuit or chip of a complex circuit contains numerous parameters, and the relationship between the parameters of various levels is complicated. Therefore, the proper use of the test circuit parameters is beneficial to the chip circuit analysis. As shown in Figure 5, during the test process, the tester failures and operating errors may cause test errors. Here we assume that the test capability is a probability distribution rather than a fixed value.

This work assumes the capability of a tester is normally distributed, with a mean, μ_T, and standard deviation, σ_T. The test yield Y_t is calculated as Y_t = P[pass] = P[X < Y] and expressed as follows:

$$\begin{array}{ll}{\mathrm{Y}}_{\mathrm{t}}(\%)& =\mathrm{Test} \mathrm{Yield}=\mathrm{P}\left[\mathrm{pass}\right]=\mathrm{P}\left[\mathrm{X}<\mathrm{Y}\right]\\ & ={{\displaystyle \int }}_{-\infty }^{\infty }\mathrm{Chip}(\mathrm{x}){{\displaystyle \int }}_{\mathrm{x}}^{\infty }\mathrm{Tester}(\mathrm{y})\mathrm{dy} \mathrm{dx}\\ & ={{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{x}-{\mathsf{\mu }}_{\mathrm{M}})}^2}{2{\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{T}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{y}-{\mathsf{\mu }}_{\mathrm{T}})}^2}{2{\mathsf{\sigma }}_{\mathrm{T}}{}^2}}\mathrm{dydx}\\ & ={{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}{{\displaystyle \int }}_{\frac{{\mathsf{\mu }}_{\mathrm{M}}+{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^2}\mathrm{dydx}\end{array}$$

(2)

Let ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ represent the traditional testing method using the appropriate TS to test the DUT (only test the DUT once).

2.4. Defect Level (DL) Estimation after Wafer Test

As is generally known, testing does not add any functionality; however, it provides added value to the product in the form of quality. Defect level (DL) is usually used to measure product quality. The quality defect level denotes the ratio of the number of defective parts (missing errors) to the number of shipped chips, and it can be calculated as DL = P[Bad|Pass] = P[(X > DS)∩(X < ST)]/P[X < ST]; thus, the DL can be expressed as

$$\begin{array}{ll}\mathrm{DL}& =\mathrm{Defect} \mathrm{Level} (\mathrm{ppm})\\ & =\frac{\mathrm{P}\left[\mathrm{Bad}|\mathrm{Pass}\right]}{{\mathrm{Y}}_{\mathrm{t}}}\\ & =\frac{\mathrm{Missing} \mathrm{Errors}}{{\mathrm{Y}}_{\mathrm{t}}}\\ & =\frac{{{\displaystyle \int }}_{\mathrm{DS}}^{\infty }\mathrm{Chip}(\mathrm{x}){{\displaystyle \int }}_{\mathrm{x}}^{\infty }\mathrm{Tester}(\mathrm{y})\mathrm{dy} \mathrm{dx}}{{{\displaystyle \int }}_{-\infty }^{\infty }\mathrm{Chip}(\mathrm{x}){{\displaystyle \int }}_{\mathrm{x}}^{\infty }\mathrm{Tester}(\mathrm{y})\mathrm{dy} \mathrm{dx}}\\ & =\frac{{{\displaystyle \int }}_{\mathrm{DS}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{x}-{\mathsf{\mu }}_{\mathrm{M}})}^2}{2{\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{T}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{y}-{\mathsf{\mu }}_{\mathrm{T}})}^2}{2{\mathsf{\sigma }}_{\mathrm{T}}{}^2}}\mathrm{dydx}}{{{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{x}-{\mathsf{\mu }}_{\mathrm{M}})}^2}{2{\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{T}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{y}-{\mathsf{\mu }}_{\mathrm{T}})}^2}{2{\mathsf{\sigma }}_{\mathrm{T}}{}^2}}\mathrm{dydx}}\\ & =\frac{{{\displaystyle \int }}_{\frac{\mathrm{DS}-{\mathsf{\mu }}_{\mathrm{M}}}{{\mathsf{\sigma }}_{\mathrm{M}}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}{{\displaystyle \int }}_{\frac{{\mathsf{\mu }}_{\mathrm{M}}+{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^2}\mathrm{dydx}}{{{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}{{\displaystyle \int }}_{\frac{{\mathsf{\mu }}_{\mathrm{M}}+{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{\mathrm{y}}^2}\mathrm{dydx}}\end{array}$$

(3)

2.5. Test Overall Timing Accuracy and TGB Impact on the Test Result

We considered the interaction between the overall timing accuracy (OTA) and Y_t. We used data from

Table 2. The impact of test parameters OTA and test specifications on test results.

σT (ps)	OTA (ps)	Yt (%)	DL (ppm)	Ts (ps)
30	90	76.4	13	μT = DS − 3σT	1075
30	90	84.3	262	μT = DS – 2σT	1105
30	90	90.2	2280	μT = DS – 1σT’	1135
30	90	94.3	9615	μT = DS	1165
40	120	66.2	20	μT = DS – 3σT	1045
40	120	78.5	356	μT = DS – 2σT	1085
40	120	87.7	2918	μT = DS – 1σT	1125
40	120	93.72	11,756	μT = DS	1165
60	180	44.9	41	μT = DS – 3σT	985
60	180	65.02	583	μT = DS – 2σT	1045
60	180	81.6	4133	μT = DS – 1σT	1105
60	180	92.14	15,104	μT = DS	1165

together with our proposed digital IC testing model (DITM: a test model and iterative yield estimation formula suitable for time-variant manufacturing processes) [30,31]. For the chip, DS = 1165 ps, circuit characteristic parameter X ~ N (x; μ_M = 1000 ps, σ_M = 100 ps), we obtain the manufacturing yield (or true yield) as being Y_m = P[Good] = P[X < DS] = 95%. Using the traditional test methodology for DUT testing, we applied three different OTA values (90, 120, and 180 ps) (Figure 6 and Table 2). When a high-precision tester is selected (the tester characteristic parameter OTA was 90 ps), the test gave high yield and high quality; however, when a tester with low accuracy was selected (the tester characteristic parameter OTA was 180 ps), the obtained yield and quality tested increasingly worsened. We know that as the accuracy of the characteristic parameter OTA of the tester decreases [35,36], the quality and yield rate also decrease, and the situation of killing error and missing error becomes increasingly serious. Of course, a high-precision (OTA) tester is expensive, while a low-precision (OTA) tester will have a lower price. Besides the consideration of the test cost and test yield quality, it is vital to appropriately select the tester according to the circuit characteristics of the test object.

Given the tester inaccuracy, it is necessary to consider the TGB. As shown in Figure 7 and Table 2, the TGB is defined as the distance between the test specification and the design specification TGB = DS − TS [37,38]. The TGB operation will affect the test yield and quality. For example, with the characteristic parameter OTA (120 ps, 3 σ_T = 3 × 40 = 120 ps) of the tester set at a fixed value, if the test specification is set to 1045 ps (TS = DS − 3σ_T), high quality, low yield (Y_t = 66.2%), and DL = 20 ppm will be obtained as the test result. Under the same conditions, select the same tester (OTA = 120 ps) to test the device under test (DUT). If the test specification is set to 1165 ps (TS = DS), low quality, high yield (Y_t = 93.72%), and DL = 11756 ppm will be obtained as the test result. Based on the above, the product test yield and test quality affect each other. Therefore, the more the TS moves to the left, that is, the larger the TGB (the smaller the TS value), the better the shipment quality can be guaranteed, but the test yield will decrease. Likewise, moving the TS to the right (relaxation of the test specifications) will increase the test yield but at the same time reduce the test quality. Therefore, the yield can be sacrificed for high-quality products. To obtain a high yield, the quality will be relatively lower, and the product will be tested. Rate and test quality are interchangeable, but both cannot be had. Defects in the manufacturing process may cause quality problems. Appropriate TGB selection and effective testing methods are important conditions for improving product quality and yield.

Therefore, using traditional test methods ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ and changing the TGB, the test quality and test yield could be traded off for each other, but the optimal values of both could not be achieved concurrently. Moving the TS to the left will cause an increase in killing errors and a decrease in missing errors. This way, the quality will increase, but the test yield will decrease. Assuming that the TS moves to the right, it will cause an increase in missing errors and a decrease in killing errors. This way, although the test yield rate will increase, the quality will decline, causing customers to return a large number of products. In reality, during the testing process, an appropriate TGB can be used to determine the quality and quantity of products delivered to consumers.

3. A New Method for Test Yield Improvement: Multiplex Testing

In the semiconductor IC testing industry, retesting methods have been applied during production to improve post-test yields [5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. For example, we refer to the paper of Kirmse et al. [17]. They propose three wafer retest recommendation models. These models have made possible rapid analysis of wafer runs and provided die- or bin-specific retests. They have also vastly improved the speed and efficiency of the detection process of detection of test errors. In regard to the retest of the chip, we also can refer to the paper by Horng et al. [7]. They propose an Ordinal Optimization theory-based two-level method to achieve fewer overkills by using retesting within reasonable computational time. Their method can also minimize overkills errors with a tolerable number of retests. In addition to that, Teslence Technology Co., Ltd. (TT), assisted by ASE Technology Holding Co., Ltd., developed a new test method [5] and applied its methodology to the test production line of chip products. The retest method proved to be capable of enhancing the test yield effectively. Furthermore, the full speed test [9] is to make the chip work at a clock frequency (on-chip clock controller (OCC)) higher than that of the ATE to detect the delayed failure of the DUT. We agree that this method is very effective. However, the problem with the test method of full speed test is that the embedded test circuit is in the chip and may need more design prework. As the technology of the tester is far behind the process technology, the ability to distinguish between good and bad chips is deteriorating. In order to meet consumers’ requirements for product quality and test yield, we changed the test method and adjusted the test guardband, and proposed a retest scheme (multiplex tests). After the IC is tested by the testing house, the semiconductor product can be divided into two parts: pass (P) or fail (F). We extend the test time and change the test method. Moreover, we discard the parts that failed the test and select the good (P) parts for retesting. Finally, we keep the PP part that passed the test. Let ${\mathrm{M}}_{2\mathrm{t}}^{2+}$ denote the multiplex testing method with the same test specifications. Figure 8 shows the corresponding decision diagram, and the multiplex testing (${\mathrm{M}}_{2\mathrm{t}}^{2+}$) formula is defined in (4).

$$\begin{array}{ll}{\mathrm{Y}}_{\mathrm{t}}(\mathrm{Test} \mathrm{Yield})& ={\mathrm{M}}_{2\mathrm{t}}^{2+}(\%)\\ & ={{\displaystyle \int }}_{-\infty }^{\infty }\mathrm{Chip}(\mathrm{x}){{\displaystyle \int }}_{\mathrm{x}}^{\infty }\mathrm{Tester}(\mathrm{y}, {\mathsf{\mu }}_{\mathrm{T}})\mathrm{dy}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\mathrm{Tester}(\mathrm{z}, {\mathsf{\mu }}_{\mathrm{T}})\mathrm{dz} \mathrm{dx}\\ & ={{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{x}-{\mathsf{\mu }}_{\mathrm{M}})}^2}{2{\mathsf{\sigma }}_{\mathrm{M}}{}^2}}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{T}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{y}-{\mathsf{\mu }}_{\mathrm{T}})}^2}{2{\mathsf{\sigma }}_{\mathrm{T}}{}^2}}\mathrm{dy}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}_{\mathrm{T}}{}^2}}{\mathrm{e}}^{\frac{-{(\mathrm{z}-{\mathsf{\mu }}_{\mathrm{T}})}^2}{2{\mathsf{\sigma }}_{\mathrm{T}}{}^2}}\mathrm{dzdx}.\end{array}$$

(4)

$$\begin{array}{ll}\mathrm{Defect} \mathrm{Level}& =\mathrm{DL}(\mathrm{ppm})\\ & =\frac{\mathrm{Missing} \mathrm{Errors}}{{\mathrm{Y}}_{\mathrm{t}}}\\ & =\frac{{{\displaystyle \int }}_{\mathrm{DS}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}{\mathsf{\sigma }}_{\mathrm{M}}}{\mathrm{e}}^{-\frac{1}{2}{(\frac{\mathrm{X}-{\mathsf{\mu }}_{\mathrm{M}}}{{\mathsf{\sigma }}_{\mathrm{M}}})}^2}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}{\mathsf{\sigma }}_{\mathrm{T}}}{\mathrm{e}}^{-\frac{1}{2}{(\frac{\mathrm{y}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}}})}^2}\mathrm{dy}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}{\mathsf{\sigma }}_{\mathrm{T}}}{\mathrm{e}}^{-\frac{1}{2}{(\frac{\mathrm{z}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}}})}^2}\mathrm{dz} \mathrm{dx}}{{{\displaystyle \int }}_{\frac{\mathrm{DS}-\mathrm{M}}{\mathrm{MSD}}}^{\infty }((\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{x}}^2}{2}}({{\displaystyle \int }}_{\frac{{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}+{\mathsf{\mu }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{\mathrm{TS}\mathrm{D}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{y}}^2}{2}}\mathrm{dy}))({{\displaystyle \int }}_{\frac{{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}+{\mathsf{\mu }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{\mathrm{TSD}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{z}}^2}{2}}\mathrm{dz}))\mathrm{dx}}\\ & =\frac{{{\displaystyle \int }}_{\frac{\mathrm{DS}-\mathrm{M}}{\mathrm{MSD}}}^{\infty }((\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{x}}^2}{2}}({{\displaystyle \int }}_{\frac{{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}+{\mathsf{\mu }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{\mathrm{TS}\mathrm{D}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{y}}^2}{2}}\mathrm{dy}))({{\displaystyle \int }}_{\frac{{\mathsf{\sigma }}_{\mathrm{M}}\mathrm{x}+{\mathsf{\mu }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{\mathrm{TSD}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{{\mathrm{z}}^2}{2}}\mathrm{dz}))\mathrm{dx}}{{{\displaystyle \int }}_{-\infty }^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{x})}^2}{{\displaystyle \int }}_{\frac{{\mathsf{\mu }}_{\mathrm{M}}+{\mathrm{x}\mathsf{\sigma }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}1}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{y})}^2}\mathrm{dy}{{\displaystyle \int }}_{\frac{{\mathsf{\mu }}_{\mathrm{M}}+{\mathrm{x}\mathsf{\sigma }}_{\mathrm{M}}-{\mathsf{\mu }}_{\mathrm{T}}}{{\mathsf{\sigma }}_{\mathrm{T}2}}}^{\infty }\frac{1}{\sqrt{2\mathsf{\pi }}}{\mathrm{e}}^{-\frac{1}{2}{(\mathrm{z})}^2}\mathrm{dzdx}}\end{array}$$

(5)

Figure 9 shows the corresponding decision diagram, where the passing chips were tested n times, where “n” denotes the number of extra times the passed DUT was tested.

3.1. The Impact of Multiplex Testing for n Times on the Test Yield

We considered the manufacturing progress together with product variation. We used data from

Table 3. Company profit surplus based on the number of tests.

σT (ps)	Ym (%)	Yt (%)	Test Specification (ps)	DL (ppm)	Test Method
40	95%	77.76	1082	300	${\mathrm{R}}_{1\mathrm{t}}^{1+}$
40	95%	83.47	1125	300	${\mathrm{M}}_{2\mathrm{t}}^{2+}$
40	95%	85.60	1145	300	${\mathrm{M}}_{3\mathrm{t}}^{3+}$
40	95%	86.76	1157	300	${\mathrm{M}}_{4\mathrm{t}}^{4+}$
40	95%	87.51	1166	300	${\mathrm{M}}_{5\mathrm{t}}^{5+}$
40	95%	87.99	1172	300	${\mathrm{M}}_{6\mathrm{t}}^{6+}$
40	95%	63.10	1036	10	${\mathrm{R}}_{1\mathrm{t}}^{1+}$
40	95%	74.22	1091	10	${\mathrm{M}}_{2\mathrm{t}}^{2+}$
40	95%	78.16	1115	10	${\mathrm{M}}_{3\mathrm{t}}^{3+}$
40	95%	80.39	1130	10	${\mathrm{M}}_{4\mathrm{t}}^{4+}$
40	95%	81.94	1141	10	${\mathrm{M}}_{5\mathrm{t}}^{5+}$
40	95%	82.95	1149	10	${\mathrm{M}}_{6\mathrm{t}}^{6+}$

together with our DITM (model and formula). When we used OTA = 120 ps, DS = 1165 ps (traditional test methodology ${\mathrm{R}}_{1\mathrm{t}}^{1+}$), and TS = 1000 ps, we obtained Y_t = 77.76% (set the test quality DL at 300 ppm,). As shown in Figure 10 and Table 3, applying multiplex testing ${\mathrm{M}}_{2\mathrm{t}}^{2+}$ (triple testing scheme) to the DUT under the same test conditions (DL = 300 ppm) could increase the yield from Y_t = 77.76% (${\mathrm{R}}_{1\mathrm{t}}^{1+}$) to Y_t = 83.47% (${\mathrm{M}}_{2\mathrm{t}}^{2+}$). Following the above procedure to estimate the Y_t for ${\mathrm{M}}_{3\mathrm{t}}^{3+}$, we applied multiplex testing ${\mathrm{M}}_{3\mathrm{t}}^{3+}$ using the same values for TS (Ts = 1145 ps), which raised the yield from Y_t = 77.76% (${\mathrm{R}}_{1\mathrm{t}}^{1+}$) to Y_t = 85.6% (${\mathrm{M}}_{3\mathrm{t}}^{3+}$). Over time, the use of traditional testing methods to test yield has shown ever-worsening results. However, we moved the TGB, changed the test conditions, and used multiplex testing ${\mathrm{M}}_{\mathrm{nt}}^{\mathrm{n}+}$ to effectively improve the test yield. However, semiconductor manufacturers must contend with the slow advancement of testing technology. It will be extremely difficult to identify zero-defect products using IC tester that lag behind manufacturing technology [22,23,24,25,26,27,28]. For example, using traditional test methodology, ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ to test DUT, TS = 1036 ps, limiting the DL to 10 ppm could obtain Y_t = 63.10% (Figure 10 and Table 3). Next, we applied multiplex testing ${\mathrm{M}}_6^{6+}$ to the DUT under the same test conditions (DL = 10 ppm), which could increase the yield from Y_t = 63.10% (${\mathrm{R}}_{1\mathrm{t}}^{1+}$) to Y_t = 82.95% (${\mathrm{M}}_6^{6+}$).

We know from the above simulation results that the more the number of tests, the fewer chips with missing errors. Using the repeated testing method can effectively improve the quality of the test while sacrificing a little test yield and screening out products with close to zero defects quality (Zero Defect Manufacturing ZDM) [20,21]. The above-simulated result indicates that moving the test specification parameters could effectively raise Y_t without sacrificing the defect level, and more frequent testing will result in fewer chips being subjected to killing errors. Thus, Y_t will more closely approach Y_m. As the number of tests continues to increase, the testing cost also increases. We also found that as the number of testing times increases, the movement of the rising curve of the test yield becomes increasingly slower; therefore, when the profit brought by the increased test output is lower than the test cost, retesting the DUT does not have any economic value. A good decision-making method [39,40] should be used to skip the retest step to avoid wasting manpower and test costs.

3.2. Enhanced IC Test System (ETS)

Currently, in the semiconductor testing industry [41], retesting is being applied in the production process to improve test results [5,6,7,8,9,10,11,12,13,14,15,16,17,18,19]. In the actual test in the test factory, the retest strategy greatly improves the test yield. Teslence Technology Co., Ltd. (TT), assisted by the test factory ASE Technology Holding Co., Ltd., developed a new test method [5] and applied its method to the test production line of chip products. This technology provides an auto-calculated reprobing path to minimize rescreen test time, maximize recovery yields, and allow production flexibility without downtime. After the test and operation on the production line, the retest method proved to effectively improve the test yield. To meet consumer requirements for product quality, a new enhanced IC test scheme is proposed to maximize the yield and desired quality. We apply the retest strategy [5] to IC testing and find a set of enhanced test procedures to obtain ideal test results under fast calculations.

Figure 11 is a flow chart of enhanced decision making. The steps of the smart multiplex testing method are as follows:

Step 1. First, use traditional test methods ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ to test the device under test (DUT) and then calculate the test yield and test quality. The purpose of this step is to establish a comparative reference value that will be compared with the results of the multiple tests as a reference basis for further retesting.

Step 2. Under a standard tester with the same testing abilities, we use the multiplex testing functions [22,30,31] and move the guardband (i.e., different test specification parameters) to test the DUT. This step aims to move the test guardband and minimize the killing error, improving the test yield.

Step 3. The manufacturing yield and test yield calculations are complicated because the DITM contains many complicated parameters. A slight change in the value of a parameter will cause a huge change in the calculation results. Therefore, we refer to the test specifications of traditional tests and move the TGB, using the approximate search methods to find the most appropriate test specifications and to obtain the best test yield (Y_t). Consequently, we used the above method to determine the TS value for the test (multiplex testing method), and the goal is to get the maximum test yield.

Step 4. Use the multiplex testing method to test the object under test (DUT). Based on the obtained test yield and test cost, the required number of retests is performed under the evaluation and feedback of comparative computation. When the profit from the increase in the test yield is greater than the test cost, the number of retests will be increased. However, when the overall profit, that is, the profit after the test cost has been removed, began to slowly decline, the number of retests will cease to be increased. We will determine the timing for the cessation of increment of the retest is determined through our analysis of the sequence of the enhanced test flow chart. By so doing, we can avoid the profit decline of the manufacturer and find out the optimal number of retests. Reducing the number of tests can avoid blind retesting, saving workforce, time, and testing costs.

Step 5. Finally, after multiplex testing, when the test cost is greater than the profit brought by the increase in yield, we stop the testing process and enter the next manufacturing stage. With repeated testing methods and cost calculations, the test system can maximize the test yield and increase the company’s profit.

Performing traditional tests ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ can obtain reference values for test specifications and test yields. The purpose of this step is to establish a comparative reference value and to compare it with the results of multiple tests as a reference for further retesting. After the comparison is conducted, we will then calculate the required number of retests according to the test yield obtained by the multiplex test method, under the feedback after comparing and calculating the test cost. Therefore, the traditional test must be performed at the beginning. If the multiplex test method is used alone, the reference value of the test specification and test yield cannot be obtained, and the required number of tests and the increased profit cannot be calculated.

3.3. Test Cost and Product Profit Calculation

In the highly competitive IC manufacturing industry, effective cost control is often the key to the success of the semiconductor industry. While it is helpful to focus on the test cost itself, the overall contribution to a manufacturer’s profitability from lower test costs will be very small, since the test is a small part of the overall device cost. For instance, according to the ITRS 2015 [2], the test cost accounts for about 5% of the total cost. If the manufacturing cost of the chip is 10.00 US dollars, the test cost is USD 0.5. If the test cost is reduced by 10%, the cost of each wafer will be reduced by USD 0.5 × 10% = USD 0.05. If other methods are used to increase the yield rate by 1%, the total cost of each chip will be reduced by USD 10 × 1% = USD 0.1. From the above example, we can know that the profit gained by improving the test yield is far greater than the profit saved by reducing the test cost. As the development speed of the tester is slower than the speed of the semiconductor development process, for the testing house, an IC test method based on multiplex testing with idle test equipment can be adopted for effective testing. However, although multiplex testing will increase the test yield because it will increase personnel cost and the tester rental time, the test costs must also be considered. Generally, the rental of the IC tester (ATE) is on a per-hour basis, and the test cost is about 5% of the total manufacturing cost (ITRS, 2015), However, when the multiplex testing method is used to test the DUT, the personnel only need to place the DUT (IC) on the load board of the tester and connect it directly to the test signal. We know that the electrical signal is very fast, and the retesting time is only a few seconds; therefore, a lot of time can be saved. From the perspective of cost calculation, the retesting cost should be much lower than 5% of the manufacturing cost.

3.4. Decision-Making Methods to Increase Company Profits

The internationally accepted chip pricing strategy is the 8:20 pricing method [42]; that is, when the chip cost is 8, the price is 20. For example, assuming that 10 million chips are produced every year if the manufacturing cost of an IC is USD 10 (United States dollars), the selling price of an IC can be estimated as USD 25. According to the ITRS, the test cost is about 5% of the manufacturing cost [2,42]; thus, the cost of testing the above product is about USD 5 million (10,000,000 × 10 × 5% = USD 5,000,000). Assuming that “C” company produces 10 million 0.858 GHz (1165 ps) chips, each unit price is USD 25. As shown in

Table 4. The number of tests determines the surplus of profit.

Test Method		Unit	TS (ps)	Yield Rate (%) and Profit (USD Million) Improvement
${\mathrm{R}}_{1\mathrm{t}}^{1+}$	TS (μT)	ps	1082	Yt (%)	Profit (USD M)↑	Yt (%)	Profit (USD M)↑
	Yt	%	77.76
${\mathrm{M}}_{2\mathrm{t}}^{2+}$	TS (μT)	ps	1125	${\mathrm{M}}_{2\mathrm{t}}^{2+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}$ = 5.71	4.275	${\mathrm{M}}_{2\mathrm{t}}^{2+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}$ = 5.71	4.275
	Yt	%	83.47
${\mathrm{M}}_{3\mathrm{t}}^{3+}$	TS (μT)	ps	1145	${\mathrm{M}}_{3\mathrm{t}}^{3+}-{\mathrm{M}}_{2\mathrm{t}}^{2+}$ = 2.18	0.45	${\mathrm{M}}_{3\mathrm{t}}^{3+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}$ = 7.89	4.725
	Yt	%	85.65
${\mathrm{M}}_{4\mathrm{t}}^{4+}$	TS (μT)	ps	1157	${\mathrm{M}}_{4\mathrm{t}}^{4+}-{\mathrm{M}}_{3\mathrm{t}}^{3+}$ = 1.11	−2.225	${\mathrm{M}}_{4\mathrm{t}}^{4+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}=9$	2.5
	Yt	%	86.76
${\mathrm{M}}_{5\mathrm{t}}^{5+}$	TS (μT)	ps	1166 87.57	${\mathrm{M}}_{5\mathrm{t}}^{5+}-{\mathrm{M}}_{4\mathrm{t}}^{4+}$ = 0.81	−2.975	${\mathrm{M}}_{5\mathrm{t}}^{5+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}$ = 9.81	−0.475
${\mathrm{M}}_{6\mathrm{t}}^{6+}$	TS (μT)	ps	1173 88.18	${\mathrm{M}}_{6\mathrm{t}}^{6+}-{\mathrm{M}}_{5\mathrm{t}}^{5+}$ = 0.61	−3.475	${\mathrm{M}}_{6\mathrm{t}}^{6+}-{\mathrm{R}}_{1\mathrm{t}}^{1+}$ = 10.42	−3.95

below, DS = 1165 ps (0.858 GHz), circuit characteristic parameter X ~ N (x; μ_M = 1000 ps, σ_M = 100 ps). We substituted the chip values using the above-mentioned equation to obtain a 95% manufacturing yield. When a tester is selected (OTA = 120 ps), the DL requirement is set to 300 ppm. If the traditional test method ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ and the multiplex testing method ${\mathrm{M}}_{3\mathrm{t}}^{3+}$ are used to test the DUT, after estimation, the test yield (Y_t) can be increased from 77.76% to 85.65% (Figure 12 and Table 4). Therefore, when the new test method is used, the test yield rate increases by 7.89% (85.65% − 77.76% = 7.89%). Since company “C” can sell 789,000 more chips each year, the additional annual revenue is USD 19.725 million. (10,000,000 × 25 × 7.89% = 19.725 million). However, because the rental time is more than twice, after deducting the cost of two repeated tests, the additional income is only USD 4.725 million (19.725 − 5 − 5 − 5 = USD 4.725 million). From the above analysis, it is clear that for semiconductor manufacturers, the use of multiplex testing methods can improve the test yield and increase company profits.

When the test technology stagnates, the test yield will worsen. The proposed multiplex testing method can improve the test yield; however, the more the number of tests, the higher the cost. It is important to get the best number of test repetitions, to avoid the test cost exceeding the additional profit brought by multiplex testing. In addition, the above example proves that multiplex testing can increase the test yield. However, with the increase in the number of tests, the labor cost and tester rental time also increase; therefore, when changing the test method, test executors must also consider the test cost. However, test executors must avoid retesting blindly, which will affect product profits. As when the improved test yield results in a situation where the company profit is less than the test cost, the company’s overall profit will also decline.

Furthermore, the DUT retesting for four times ${\mathrm{M}}_{4\mathrm{t}}^{4+}$ was simulated (Figure 13 and Table 4). With the removal of the extra test yield produced by the previous traditional ${\mathrm{R}}_{1\mathrm{t}}^{1+}$, the test yield (Y_t) can be increased from 77.76% to 86.76 %. Moreover, we found that the test yield of the four-retest strategy was 1.11% higher than that of the three-retest strategy: ${\mathrm{M}}_{4\mathrm{t}}^{4+}$ − ${\mathrm{M}}_{3\mathrm{t}}^{3+}$ = 86.76 − 85.65 = 1.11%. However, the overall profit, that is, the profit after the test cost has been removed, began to slowly decline. This means that the cost of repeating the test four times ${\mathrm{M}}_{4\mathrm{t}}^{4+}$ is greater than the profit brought by the corresponding increase in yield (10,000,000 × 25 × 1.11% = USD 2.775 million, 2.775 − 5 = USD −2.225 million). Regarding the above electrical parameters and test parameters, the DUT multiplex testing limited to three times can yield the most ideal profit, and the test cost [43] can be optimized. According to the sequence of the enhanced test flow chart, to avoid the company profit decline, the test should be stopped, and the next stage of work should be conducted.

Retest has been widely used in the IC testing industry and can effectively improve the test yield. However, aimlessly repetitive retesting can cause the cost of testing to surpass the profit from retesting. Therefore, in order to meet the requirements of manufacturers for high profit and high yield, we propose an enhanced test system (ETS). Based on the obtained test yield and test cost, under the feedback of enhanced calculation, the required number of retests is calculated. Reducing the number of tests can avoid unnecessary retesting, save manpower and time, and reduce testing costs. Judging from the feedback of enhanced computing (Enhanced IC test system), when the test cost is greater than the profit brought by the yield improvement, the test process is stopped and the next product manufacturing stage is entered. Through the above-enhanced testing methods, we can obtain the best test yield and the best profit.

4. Application of Multiplex Testing to the IRDS 2017 Data

For example, assume that “C” Company produces 10 million chips each year, and the cost of testing accounts for 5% of the manufacturing cost of each chip. The pricing strategy uses an 8:20 pricing method. The cost of producing a chip is USD 10 and the price is USD 25. We applied the traditional test method to the test table of the International Roadmap for Devices and Systems (IRDS) 2017 [44]. Referring to Figure 14 and

Table 5. Company profit surplus based on the number of tests.

Year		Unit	2018	2019	2020	2021	2022	2023	2024	2025	2026	2027	2028	2029	2030	2031	2032
Device period		ps	400	354	330	300	273	248	226	205	187	170	154	140	127	116	105
Chip frequency		GHz	2.5	2.75	3.03	3.33	3.66	4.03	4.43	4.87	5.36	5.89	6.48	7.13	7.85	8.63	9.49
σM		ps	83	73	68	62	57	51	47	42	39	35	32	29	26	24	22
μM		ps	264	233	218	198	180	163	149	135	123	112	101	92	84	76	69
DL		ppm	300	300	300	300	300	300	300	300	300	300	300	300	300	300	300
OTA		ps	100	95	90.25	85.7	81.5	77.4	73.5	70	66.3	63	59.9	56.9	54	51.3	48.8
${\mathrm{R}}_{1\mathrm{t}}^{1+}$	TS (μT)	ps	330.7	366	266.3	239	214	192	172	153.3	137.2	122.3	108.1	96	84.4	75.4	65.5
	Yt	%	77.2	75.3	74.2	72.6	70.5	69.4	66.8	64.8	62.4	60	57.5	54.6	50.5	49.2	45
${\mathrm{M}}_{2\mathrm{t}}^{2+}$	TS (μT)	ps	357	321	299	270	244	220	199	180	162	146	131	118	105	95	85
	Yt	%	82.9	81.7	81.2	80	78.6	77.9	76	75.5	73.2	71.5	70	68	64	63.5	60.5
${\mathrm{M}}_{3\mathrm{t}}^{3+}$	TS (μT)	ps	383	337	314	284	257	233	211	191	173	157	141	127	115	104	93
	Yt	%	85.3	84.3	83.8	82.7	81.3	81.2	79.3	78.9	76.9	76.2	74.4	72.2	70.6	69	65.8
${\mathrm{M}}_{4\mathrm{t}}^{4+}$	TS (μT)	ps	293	347	323	293	266	241	219	198	180	163	148	134	121	110	99
	Yt	%	86.4	85.7	85	84.3	83.2	82.8	81.4	80.7	79.1	78.1	77.6	76	74	72.7	70.4
${\mathrm{M}}_{5\mathrm{t}}^{5+}$	TS (μT)	ps	400	354	330	299	272	247	225	204	185	168	152	138	125	114	103
	Yt	%	87.1	86.6	86	85.1	84.3	84.1	82.8	82.5	80.6	80	78.8	77.5	75.9	75	71.8
${\mathrm{M}}_{6\mathrm{t}}^{6+}$	TS (μT)	ps	406	359	335	304	277	252	229	208	189	172	156	141	128	117	105
	Yt	%	87.8	87.13	86.7	85.9	85.2	85.0	83.7	83.4	81.8	81.3	80.5	78.7	77.2	76.8	73.58
Increased maximum profit		million US	5.25	7.5	9	10.25	12.00	14.5	16.5	19.75	20.5	25.00	28.25	32.25	38.5	39	41.45

, for chips whose DS was 300 ps and DUT characteristic parameter was X ~ N (x; μ_M = 198 ps, σ_M = 62 ps) in 2021, we substituted them into the above-mentioned equation and obtained 95% of manufacturing yield (Y_m). Next, the tester (ATE) characteristic parameter whose OTA was 85.7 ps was used for testing, limiting the DL to 300 ppm, TS = 239 ps (traditional test methodology ${\mathrm{R}}_{1\mathrm{t}}^{1+}$), and we obtained Y_t = 72.6%. When DS = 205 ps (4.87 GHz) for 2025, the OTA value of the tester (ATE) was 70 ps, and the test yield was 64.8%. This indicates that the future tester did not show bigger technological breakthroughs even though the manufacturing technology was continuously improving, leading to the continuous reduction of the test yield and quality.

In the semiconductor IC testing industry, retesting methods have been applied during production to improve post-test yields. As a result, we propose a new test solution that extends the test time and moves the TGB to meet consumer demands for product yield and quality, address the shortage of semiconductor chips, and improve the ability of IC testers and test yield. The proposed scheme has been shown to maximize the yield by minimizing the test cost. Hence, we changed the test method under the same IC tester equipment (OTA = 85.7 ps), using the multiplex test method to test the DUT. By using the above estimation methods, the test yield obtained from the multiplex test ${\mathrm{M}}_{2\mathrm{t}}^{2+}$ method (80%) is higher than that obtained from the traditional test method ${\mathrm{R}}_{1\mathrm{t}}^{1+}$ in 2021 when testing chips (DUT) (72.6%). The multiplex test method improves the yield of the test, which is approximately 7.4% higher than that of the traditional test yield ${\mathrm{R}}_{1\mathrm{t}}^{1+}$. Next, chips produced in 2025 will be tested using a multiplex test ${\mathrm{M}}_{2\mathrm{t}}^{2+}$ methods. After the simulation and estimation by the above formula, the yield rate will increase to Y_t = 75.5%. Hence, the multiplex test method improves the test yield by approximately 12.2% (75.5% − 64.8% = 10.7%) as compared to the traditional test method ${\mathrm{R}}_{1\mathrm{t}}^{1+}$. Multiplex testing could promote Y_t and tester performance without influencing VLSI tester inaccuracy. Thus, the Y_t of the tester could be improved dramatically. More time spent on testing allows for the recovery of chips with killing errors and the achievement of high yield delivery, both of which can significantly increase a company’s total profit.

Test Yield Improvement Affects Company Profits

Based on the preceding example, we will estimate the additional profit added to the company by using the retest method (recycling test) from a cost–benefit perspective. For example, assume that “C” Company produces 10 million chips each year, and the cost of testing accounts for 5% of the manufacturing cost of each chip. The pricing strategy uses an 8:20 pricing method. The cost of producing a chip is USD 10 and the price is USD 25. In the above example, moving the TGB and using multiplex testing ${\mathrm{M}}_{4\mathrm{t}}^{4+}$ for testing can increase the test yield for 2025 from 64.8% to 80.7% (Figure 14 and Table 5). It will increase the overall company profit, that is, the profit after the subtraction of the test cost, by 19.75 million USD (10,000,000 × 25 × 15.9% = USD 39.75 million, 39.75 − 5 − 5 − 5 − 5 = USD 19.75 million). Next, repeating the test five times ${\mathrm{M}}_{5\mathrm{t}}^{5+}$ increased the test yield by 1.8% (${\mathrm{M}}_{5\mathrm{t}}^{5+}-{\mathrm{M}}_{4\mathrm{t}}^{4+}=$ 82.5 − 80.7 = 1.8%). After statistics and cost estimation, we found that although the fifth retest increased the test yield by 1.8%, the increased profit was less than the cost required to test the chip (10,000,000 × 25 × 1.8% = USD 4.5 million, 4.5 − 5 = USD −0.5 million). In other words, without evaluation and simulation, blindly conducting the fifth retest will not only waste manpower and time but also reduce the company’s profits. Therefore, with the current electrical parameters and test parameter conditions, the to-be-tested device only needs to be tested four times to increase the test yield and maximize the company’s profit. We know from the above results that the enhanced test mechanism is applied to IC testing. Through the multiplex test, the test yield can be improved. The number of required tests will be calculated via the improved yield and test efficiency cost during assessment and feedback by enhanced, fast calculation (Enhanced IC test system). Thus, we can avoid blind retesting, which saves manpower and time and reduces the cost of testing. The proposed scheme has been proved to maximize test yields and company profits while minimizing test costs. As long as test manufacturers are willing to develop more effective test methods and spend reasonable test time and cost, they can not only reduce chip defects and errors but also increase test yield and wafer shipments. Therefore, the company can improve the test yields, and more chip deliveries can increase a company’s overall profit margin.

5. Conclusions

We model integrated circuit (IC) testing (DITM), which is a recursive evaluation process used to estimate the test yield and quality of integrated circuits. Using normal probability distributions of product properties, we digitally analyzed IC yield and quality, introduced testing thresholds and guardbands, and assessed various parameters’ influence on outcomes. The overall development speed of testing technology is different from that of manufacturing technology. With the slow progress of the very-large-scale integration test equipment, it may become increasingly difficult to distinguish between good and bad products in the future. Therefore, semiconductor manufacturers and test plants are trying to improve test results in better ways and reduce test costs to increase company profits. In order to meet the product quality for the consumer’s requirement, a valid multiplex testing method was proposed simultaneously with a moving guardband test to see if the test yield and test quality could be improved to achieve the high quality, near-zero-defect objectives required by the biomedical electronic and aviation electronic industries. Finally, we applied the multiplex testing method to the IRDS table in 2017. From the results, we can see that compared with traditional testing methods, repeated testing can increase the test results by 28% or more. However, retest has been widely used in the IC testing industry, and it can effectively improve the test yield. However, endless directionless retesting may cause the test cost to exceed the profit brought by the retesting. Therefore, to meet consumer requirements for the required product output, we propose an enhanced test system (ETS). According to the obtained test yield and test cost, the required number of retests is calculated under the feedback of enhanced calculation. With repeated tests methods and cost calculations, the test system can maximize the test yield and increase the company’s profit. Finally, we introduce the IRDS roadmap data to predict the trend of future test yield and prove that this enhanced test system (ETS) can effectively improve the test yield rate and maximize the test profit.