A Novel Single-Stage Common-Ground Transformerless Buck–Boost Inverter

Abstract

In this article, a novel single-stage transformerless buck–boost inverter is introduced. The proposed inverter can share a common ground between the DC input side and the grid; this leads to having a zero-leakage current. The proposed inverter also provides the buck and boost voltage capabilities. Additionally, the power switches are operated at high frequency in the half-cycle of the sinusoidal wave, so the efficiency of the proposed inverter can be improved. Operating analysis, design consideration, comparison, and simulation study are presented. Finally, a 500 W laboratory prototype is also built to confirm the correctness and feasibility of the proposed inverter.

1. Introduction

In recent years, the nearly exhausted fossil fuels and environmental deterioration have promoted the development of renewable energy sources such as wind power, photovoltaic (PV), fuel cells, and ocean waves [1,2,3,4]. Among these renewable energy sources, the PV market has several advantages, which include being inexhaustible, as well as its easy availability and pollution-free operation. Moreover, the main technological evolution for the PV system is the inverter. The inverter can be divided into two types with transformer topologies [5,6,7] or transformerless topologies [8,9,10]. Although transformer-based inverters can provide galvanic isolation and protection, they have undesirable properties such as high cost and weight, with additional losses [9,10]. On the other hand, transformerless inverters have reduced costs and sizes, and improved efficiency, but the isolation between the PV panel and the inverter system leads to the occurrence of leakage current. This leakage current causes a rise in harmonic distortion, in both output voltage and current, which also results in electromagnetic interference between the PV system and grid. To eliminate leakage current, the DC current injection from the inverter should also be reduced, as presented in the standards IEEE 1547 and IEC 61727 [11,12]. Moreover, the transformerless inverter topologies can be classified into two groups—namely, two-stage configurations and single-stage configurations. In two-stage configurations, the power processing is divided into two stages. A DC–DC boost converter is added between the inverter side and DC input power supply side, which boosts a low-voltage input to the high voltage required for the second stage [13,14,15]. The next stage is an inverter that converts DC voltage to AC voltage to connect with the grid. Two-stage transformerless inverter topologies can have some disadvantages, including low efficiency, increased cost, and complexity control in a two-stage configuration. In contrast, single-stage configurations have all the functions of boosting ability and maximum power extraction, as well as DC–AC conversion. Compared with two-stage configurations, single-stage configurations have more benefits, including compactness, lower device count, lower costs, and greater efficiency [16]. From this point of view, single-stage inverters are reported in the literature, and their comprehensive review is given in [17,18,19,20,21,22,23,24,25,26,27]. Common-ground transformerless inverter topologies were introduced in [21,22,23,24,25,28,29,30], which directly connect the ground of the grid to the negative of the DC input source. The common-mode voltage is equal to zero, and it also protects against any high-frequency content. Therefore, there is no common-mode leakage current in the presented topologies.

In order to improve the boosting capability and provide common ground with single-stage configuration, single-stage, common-ground transformerless inverters have been used in [23] without a continuous input current. However, the power switches are operated at high frequency. This leads to an increase in the switching loss of the inverter. Similarly, a buck–boost inverter in [24] with five switches is proposed to achieve the common-ground condition and wide buck–boost voltage operation. However, three switches are operated at a high switching frequency in the half-line period. The single-phase transformerless grid-connected PV inverter introduced in [25,26] also focuses on a doubly grounded inverter with single-stage conversion and uses fewer components. Nevertheless, the disadvantage of this inverter is also the high switching frequency of its power switches. To further improve the voltage gain, a novel step-up transformerless inverter is presented in [27]. This inverter can provide the common ground between the output and input sides with a single stage. However, it requires more switches, which increases the size and cost of the inverter package.

In this article, a novel single-stage common-ground transformerless buck–boost inverter (CGBBI) is proposed to eliminate leakage current elimination and achieve voltage boosting capability. Moreover, the PWM control method of the proposed inverter can reduce the high switching loss on semiconductor devices. The remainder of this article is organized as follows: First, the inverter configuration, PWM control method, and operating principle of the proposed inverter are presented in Section 2. Design guidelines of the devices are given in Section 3. A comparative study is provided in Section 4, drawing on other existing common-ground buck–boost inverter topologies. Simulation and experimental results are presented in Section 5 to evaluate the accurate performance of the proposed inverter. Finally, the conclusions of the study are drawn in Section 6.

2. Derivation of Proposed CGBBI

The proposed CGBBI topology is shown in Figure 1. The major characteristic of the proposed CGBBI topology is to have a common point between the output side and the negative terminal of the input DC power supply, which avoids the leakage current [9]. The proposed CGBBI topology includes five power switches S₁–S₅, three diodes D₁–D₃, two inductors L₁–L₂, two capacitors C₁–C₂, and one output filter inductor L_f. It can be seen that the proposed CGBBI topology is composed of one buck–boost module, one boost module, and one power switch operating at low frequency. The buck–boost module comprises three power switches S₁–S₃, two diodes D₁–D₂, and a pair of L₁ and C₁. Similarly, the boost module has one power switch S₄, one diode D₃, one inductor L₂, and one capacitor C₂.

2.1. PWM Control Method for the Proposed CGBBI Topology

Figure 2 presents the PWM control method for the proposed CGBBI topology. When output voltage v_o is higher than 0, switch S₃ is turned on, and S₄ and S₅ are turned off. However, switches S₁ and S₂ are turned on/off alternately at high frequency. When the output voltage v_o is negative, three switches S₁, S₂, and S₃ are turned off, while S₅ is turned on. In this case, only switch S₄ is operated at high frequency during this negative half-line cycle.

2.2. Operating of the Proposed CGBBI Topology

Interval 1 ([0, t₁] or [t₂, t₃]): This interval appears when the voltage V_in is higher than v_o. In this case, only the buck–boost module is operated. Switch S₃ is turned on, while S₂, S₄, and S₅ are turned off. It can be seen that only switch S₁ is turned on and off at high frequency. Voltage v_C1 is equal to v_o. In terms of the inductor current, i_L1 approximates the output current, while i_L2 is zero.

Mode 1 (Figure 3a): Switch S₁ is turned off, and diodes D₁–D₂ are forward biased. Inductor L₁ is connected to the capacitor C₁ and load, to which it charges energy. In this mode, capacitor C₁ provides energy to the load and maintains the constant output voltage across the load. We have

$$\{\begin{array}{c}{L}_1\frac{d{i}_{L1}}{dt}=-v_o\\ C_1\frac{d{v}_{C1}}{dt}=i_{L1}-i_o\end{array}$$

(1)

Mode 2 (Figure 3b): Switch S₁ is turned on, diode D₁ is reverse biased and D₂ is forward biased. Inductor L₁ is charged by an input voltage V_in, capacitor C₁, and the load. The inductor current i_L1 increases linearly. The equations in this mode can be derived as follows:

$$\{\begin{array}{c}{L}_1\frac{d{i}_{L1}}{dt}=V_{in}-v_o\\ C_1\frac{d{v}_{C1}}{dt}=i_{L1}-i_o\end{array}$$

(2)

By applying voltage-second balance condition to an inductor L₁, the relationship between v_o and V_in can be obtained as

$$v_o=d_1{V}_{in}$$

(3)

where d₁ is the duty ratio of S₁.

Interval 2 ([t₁, t₂]): This interval appears when the input voltage V_in is lower than v_o. In this case, only the buck–boost module operates. Switch S₁ is turned on, while S₄ and S₅ are kept off. Only switch S₂ is turned on and off at high frequency. Voltage v_C1 is equal to v_o, while inductor current i_L1 is larger than output current, and inductor current i_L2 is zero.

Mode 1 (Figure 4a): Switch S₂ in the buck–boost converter is turned on. Consequently, diodes D₁ and D₂ are reverse biasED. The voltage in inductor L₁ equals the input voltage V_in. Inductor current i_L1 increases linearly, and capacitor C₁ charges the load. The related equations are as follows:

$$\{\begin{array}{c}{L}_1\frac{d{i}_{L1}}{dt}=V_{in}\\ C_1\frac{d{v}_{C1}}{dt}=-i_o\end{array}$$

(4)

Mode 2 (Figure 4b): Switch S₂ is turned off, diode D₁ is reverse biased, and D₂ is forward biased. The power supply and inductor L₁ charge energy to filter the capacitor and the load, so capacitor C₁ is charged, and inductor current i_L1 decreases linearly. We have

$$\{\begin{array}{c}{L}_1\frac{d{i}_{L1}}{dt}=V_{in}-v_o\\ C_1\frac{d{v}_{C1}}{dt}=i_{L1}-i_o\end{array}$$

(5)

The relationship between v_o and V_in can be obtained from (4) and (5).

$$v_o=\frac{V_{in}}{1-d_2}$$

(6)

where d₂ is the duty ratio of S₂.

Interval 3 ([t₃, t₄]): The output voltage is negative, and it can be observed that only the boost module operates in this interval. Switch S₅ is turned on and switches S₁, S₂, and S₃ are turned off. In this case, only switch S₄ is controlled at high frequency. Voltage v_C1 is equal to output voltage v_o. Capacitor voltage v_C2 is the total voltage of input voltage and output voltage, while inductor current i_L1 is equal to 0, and inductor current i_L2 is higher than the output current.

Mode 1 (Figure 5a): Switch S₄ is turned on, and diode D₃ is reverse biased in this mode. Inductor L₂ is charged from the input voltage, and the inductor current i_L2 increases linearly. The capacitor C₂ transfers power to the load. The equations of this mode can be found as follows:

$$\{\begin{array}{c}{L}_2\frac{d{i}_{L2}}{dt}=V_{in}\\ C_2\frac{d{v}_{C2}}{dt}=i_{in}-i_{L2}\\ C_1\frac{d{v}_{C1}}{dt}=i_{in}-i_{L2}-i_o\end{array}$$

(7)

Mode 2 (Figure 5b): Switch S₄ is turned off, and diode D₃ is forward biased. Inductor L₂ transfers energy to capacitor C₂ through diode D₃. In this mode, the energy of inductor L₂ is also transferred to capacitor C₁ and the load through S₅ and D₃, so the inductor current i_L2 decreases linearly. We have

$$\{\begin{array}{c}{L}_2\frac{d{i}_{L2}}{dt}=V_{in}-v_{C2}\\ C_2\frac{d{v}_{C2}}{dt}=i_{in}\\ C_1\frac{d{v}_{C1}}{dt}=i_{in}-i_o-i_{L2}\end{array}$$

(8)

From (7) and (8), we have

$$v_o=\frac{d_4{V}_{in}}{d_4-1}$$

(9)

where d₄ is the duty ratio of S₄.

When v_o > 0, the voltage in capacitors C₁ and C₂ can be given as

$$\{\begin{array}{c}{v}_{C1}=V_{o}sin\omega t\\ v_{C2}=V_{in}\end{array}$$

(10)

When v_o < 0, the voltage in capacitors C₁ and C₂ can be rewritten as

$$\{\begin{array}{c}{v}_{C1}=V_{o}sin\omega t\\ v_{C2}=V_{in}-V_{o}sin\omega t\end{array}$$

(11)

where V_o is the peak value of output voltage, and ω is the angular frequency.

The relationship between the input voltage and the peak value of output voltage can be determined as follows:

$$M=\frac{V_o}{V_{in}}$$

(12)

where M is the modulation index.

The resulting duty cycles for the PWM modulation are visualized in Figure 2 and are calculated based on (12).

From (3), (6), (9), (12), the corresponding duty cycles for the PWM control method are defined in (13) and (14) as follows:

$$\{\begin{array}{c}{d}_1\left(t\right)=Msin\omega t\\ d_2\left(t\right)=1-\frac{1}{Msin\omega t}\\ d_4\left(t\right)=0\end{array}, when v_o>0$$

(13)

$$\{\begin{array}{c}{d}_1\left(t\right)=0\\ d_2\left(t\right)=0 \\ d_4\left(t\right)=\frac{Msin\omega t}{Msin\omega t-1}\end{array}, when v_o<0$$

(14)

According to (13) and (14), the maximum values of the corresponding duty cycles can be expressed as

$$\{\begin{array}{c}{D}_{1.max}=M\\ D_{2.max}=1-\frac{1}{M} with M>1\\ D_{2.max}=0 with M\le 1\\ D_{4.max}=\frac{M}{M+1}\end{array}$$

(15)

In order to determine the switching state in the PWM control method, shown in Figure 2, interval 2 is executed when the output voltage is higher than the input voltage. The values of t₁ and t₂ are calculated as follows:

$$\{\begin{array}{c}{t}_1=\frac{1}{\omega }si{n}^{-1}\left(\frac{1}{M}\right)\\ t_2=\pi -\frac{1}{\omega }si{n}^{-1}\left(\frac{1}{M}\right)\end{array}$$

(16)

3. Parameter Design

3.1. Selection of the Inductors

Using (1), (2), (4), (5), (7), and (8), applying the volt-second balance principle on L₁ and L₂, the inductors L₁ and L₂ currents can be calculated using (17) and (18).

$$i_{L1}=\{\begin{array}{c}\begin{array}{c}{I}_{o}sin\omega t, 0<t\le t_1 and t_2<t\le t_3\\ \frac{I_{o}sin\omega t}{1-d_2}, t_1<t\le t_2\end{array}\\ 0, t_3<t\le t_4\end{array}$$

(17)

$$i_{L2}=\{\begin{array}{c}0, 0<t\le t_3\\ \frac{I_{o}sin\omega t}{d_4-1}, t_3<t\le t_4\end{array}$$

(18)

where I_o is the peak value of output current.

According to (17), (18), and (12), the peak value of inductors L₁ and L₂ currents can be given by (19) and (20).

$$I_{L1}=\{\begin{array}{c}{I}_o, M\le 1\\ M{I}_o, M>1\end{array}$$

(19)

$$I_{L2}=\left(M+1\right)I_o$$

(20)

The inductors can be designed by using the equation of their current ripple, using (17), (18), and (15), while the peak-to-peak current ripple of inductors L₁ and L₂ can be defined by (21) and (22).

$$\mathsf{\Delta }{i}_{L1.max}=\{\begin{array}{c}\frac{V_{in}}{4f_s{L}_1}, M\le 1\\ \frac{\left(M-1\right)V_{in}}{M{f}_s{L}_1}, M>1\end{array}$$

(21)

$$\mathsf{\Delta }{i}_{L2.max}=\frac{M{V}_{in}}{\left(M+1\right)f_s{L}_2}$$

(22)

where f_s denotes the switching frequency.

According to (19)–(22), the inductance values of L₁ and L₂ can be calculated using (23) and (24) as follows:

$$L_1=\{\begin{array}{c}\frac{V_{in}}{4f_{s}x\%I_o}, M\le 1\\ \frac{\left(M-1\right)V_{in}}{M^2{f}_{s}x\%I_o}, M>1\end{array}$$

(23)

$$L_2=\frac{M{V}_{in}}{{\left(M+1\right)}^2{f}_{s}x\%I_o}$$

(24)

where x% is the inductors L₁ and L₂ ripple.

Based on the maximum value of the current through the inductors L₁, L₂ in (19) and (20). The stored energy of the inductor is given by

$$W_m=\frac{1}{2}L{I}_{L.max}^2$$

(25)

The required area product of the inductor, as cited in [31,32], is

$$A_p=\frac{2W_m}{K_u{B}_m{J}_m}$$

(26)

where K_u, B_m, and J_m are the core window of the fill factor, the amplitude of a magnetic flux density in the core, and the amplitude in current density of the winding conductor, respectively.

3.2. Selection of the Capacitors

Using the equations given in (15), the peak-to-peak voltage ripple of capacitors C₁ and C₂ can be defined as

$$\mathsf{\Delta }{v}_{C1.max}=\{\begin{array}{c}\frac{V_{in}}{32L_1{C}_1{f}_s^2}, M\le 1\\ \frac{\left(M-1\right)I_o}{M{f}_s{C}_1}, M>1\end{array}$$

(27)

$$\mathsf{\Delta }{v}_{C2.max}=\frac{M{I}_o}{\left(M+1\right)f_s(C_1+C_2)}$$

(28)

According to (27) and (28), the capacitance values of C₁ and C₂ are calculated as follows:

$$C_1=\{\begin{array}{c}\frac{V_{in}}{32y{L}_1{f}_s^2}, M\le 1\\ \frac{\left(M-1\right)I_o}{M{f}_{s}y\%V_o}, M>1\end{array}$$

(29)

$$C_2=\frac{M{I}_o}{\left(M+1\right)f_{s}y\%V_o}-C_1$$

(30)

where y% is the capacitors C₁ and C₂ ripple.

3.3. Selection of Switching Devices

The voltage stress across the switches and the diodes are given in (31)–(34).

$$\{\begin{array}{c}{V}_{DS1}=V_{D1}=V_{in}\\ V_{DS2}=V_{DS3}=V_{DS5}=V_{D2}=V_o \\ V_{DS4}=V_{D3}=V_{in}+V_o\end{array}$$

(31)

The current stresses of switches S₁–S₅ reach the maximum when the output current has its peak value (I_o), as given by (32)–(34).

$$\{\begin{array}{c}{I}_{S1}=I_{S3}=I_{D1}=I_{D2}=I_{L1}=I_o\\ I_{S2}=0\end{array}, M\le 1$$

(32)

$$\{\begin{array}{c}{I}_{S1}=I_{S2}=I_{S3}=I_{D2}=I_{L1}=M{I}_o\\ I_{D1}=I_{o}sin\omega t_1 \end{array}, M>1$$

(33)

$$I_{S5}\approx I_{S4}=I_{D3}=I_{L2}=\left(M+1\right)I_o$$

(34)

3.4. Power Loss Calculation

3.4.1. Power Loss of Power Switches

The total power loss of the switches is equal to the sum of the conduction losses and switching losses, given by

$$P_{S\_tot}=P_{S\_con}+P_{S\_sw}$$

(35)

$$P_{S\_con}={\displaystyle \sum }_{i=1}^5{R}_{dsi}{I}_{Si.rms}^2$$

(36)

$$P_{S\_sw}={\displaystyle \sum }_{i=1}^5{V}_{Si}{I}_{Si.avg}\left(t_{ri}+t_{fi}\right)f_s$$

(37)

where R_dsi, t_ri, and t_fi are the on-state drain-source resistance, the turn-on and turn-off delay times of each MOSFET, respectively.

The average and RMS current values through the switches are calculated as

$$\{\begin{array}{c}{I}_{S1.avg}=\frac{1}{2\pi }\left[2{{\displaystyle \int }}_0^{t_1}{i}_{L1}\left(t\right)d_1\left(t\right)d\left(\omega t\right)+{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}\left(t\right)d\left(\omega t\right)\right]\\ I_{S1.rms}=\sqrt{\frac{1}{2\pi }\left[2{{\displaystyle \int }}_0^{t_1}{i}_{L1}{}^2\left(t\right)d_1\left(t\right)d\left(\omega t\right)+{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}{}^2\left(t\right)d\left(\omega t\right)\right]}\end{array}$$

(38)

$$\{\begin{array}{c}{I}_{S2.avg}=\frac{1}{2\pi }\left[{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}\left(t\right)d_2\left(t\right)d\left(\omega t\right)\right]\\ I_{S2.rms}=\sqrt{\frac{1}{2\pi }\left[{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}{}^2\left(t\right)d_2\left(t\right)d\left(\omega t\right)\right]}\end{array}$$

(39)

$$\{\begin{array}{c}{I}_{S3.avg}=\frac{1}{2\pi }\left[{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}\left(t\right)\left[1-d_2\left(t\right)\right]d\left(\omega t\right)\right]\\ I_{S3.rms}=\sqrt{\frac{1}{2\pi }\left[{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}{}^2\left(t\right)\left[1-d_2\left(t\right)\right]d\left(\omega t\right)\right]}\end{array}$$

(40)

$$\{\begin{array}{c}{I}_{S4.avg}=\frac{1}{2\pi }\left[{{\displaystyle \int }}_{\pi }^{2\pi }{i}_{L2}\left(t\right)d_4\left(t\right)d\left(\omega t\right)\right]\\ I_{S4.rms}=\sqrt{\frac{1}{2\pi }\left[{{\displaystyle \int }}_{\pi }^{2\pi }{i}_{L2}{}^2\left(t\right)d_4\left(t\right)d\left(\omega t\right)\right]}\end{array}$$

(41)

$$\{\begin{array}{c}{I}_{S5.avg}=\frac{1}{2\pi }\left[{{\displaystyle \int }}_{\pi }^{2\pi }\left[i_{L2}\left(t\right)-I_{in}\right]\left[1-d_4\left(t\right)\right]d\left(\omega t\right)\right]\\ I_{S5.rms}=\sqrt{\frac{1}{2\pi }\left[{{\displaystyle \int }}_{\pi }^{2\pi }{\left[i_{L2}\left(t\right)-I_{in}\right]}^2\left[1-d_4\left(t\right)\right]d\left(\omega t\right)\right]}\end{array}$$

(42)

3.4.2. Power Loss of Diodes

The power loss in the diodes includes conduction loss and reverse recovery loss. The power loss of the diodes is calculated as

$$P_{D\_tot}=P_{D\_con}+P_{D\_sw}$$

(43)

$$P_{D\_con}={\displaystyle \sum }_{i=1}^3\left(V_{Fi}{I}_{Di.avg}+R_{Di}{I}_{Di.rms}^2\right)$$

(44)

$$P_{D\_sw}={\displaystyle \sum }_{i=1}^3{Q}_{rri}{V}_{Di}{f}_s$$

(45)

where V_Fi, R_Di, and Q_rri are the forward voltage, the ON-state resistance, and the reverse recovery charge of each diode, respectively.

The average and RMS current values through the switches are calculated as

$$\{\begin{array}{c}{I}_{D1.avg}=\frac{1}{\pi }{{\displaystyle \int }}_0^{t_1}{i}_{L1}\left(t\right)\left[1-d_1\left(t\right)\right]d\left(\omega t\right)\\ I_{D1.rms}=\sqrt{\frac{1}{\pi }{{\displaystyle \int }}_0^{t_1}{i}_{L1}{}^2\left(t\right)\left[1-d_1\left(t\right)\right]d\left(\omega t\right)}\end{array}$$

(46)

$$\{\begin{array}{c}{I}_{D2.avg}=\frac{1}{2\pi }{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}\left(t\right)\left[1-d_2\left(t\right)\right]d\left(\omega t\right)\\ I_{D2.rms}=\sqrt{\frac{1}{2\pi }{{\displaystyle \int }}_{t_1}^{t_2}{i}_{L1}{}^2\left(t\right)\left[1-d_2\left(t\right)\right]d\left(\omega t\right)}\end{array}$$

(47)

$$\{\begin{array}{c}{I}_{D3.avg}=\frac{1}{2\pi }{{\displaystyle \int }}_{\pi }^{2\pi }{i}_{L2}\left(t\right)\left[1-d_4\left(t\right)\right]d\left(\omega t\right)\\ I_{D3.rms}=\sqrt{\frac{1}{2\pi }{{\displaystyle \int }}_{\pi }^{2\pi }{i}_{L2}{}^2\left(t\right)\left[1-d_4\left(t\right)\right]d\left(\omega t\right)}\end{array}$$

(48)

3.4.3. Power Loss of Inductors

The power loss in the inductors includes the core loss and copper loss. The inductor loss is defined as

$$P_L=2·k·B^{\beta }·f_s^{\alpha }·A_e·l_e+r_L\left(I_{L1.rms}^2+I_{L2.rms}^2\right)$$

(49)

where B is the AC magnetic flux; f_s is the frequency; A_e is the core cross-sectional area; l_e is the core mean magnetic path length; I_L1.rms and I_L2.rms are RMS currents of the inductors; r_L is wire resistance. k, α, and β can be found in the manufacturer’s datasheet.

RMS values I_L1.rms and I_L2.rms can be calculated as

$$\{\begin{array}{c}{I}_{L1.rms}=\sqrt{\frac{1}{2\pi }\left(2{{\displaystyle \int }}_0^{t_1}{i}_o{}^2\left(t\right)d\left(\omega t\right)+{{\displaystyle \int }}_{t_1}^{t_2}{\left[\frac{i_o\left(t\right)}{1-d_2\left(t\right)}\right]}^{2}d\left(\omega t\right)\right)}\\ I_{L2.rms}=\sqrt{\frac{1}{2\pi }{{\displaystyle \int }}_{\pi }^{2\pi }{\left[\frac{i_o\left(t\right)}{1-d_4\left(t\right)}\right]}^{2}d\left(\omega t\right)}\end{array}$$

(50)

3.4.4. Power Loss of Capacitors

The power loss of capacitors is calculated as

$$P_C=r_{C1}{I}_{C1.rms}^2+r_{C2}{I}_{C2.rms}^2$$

(51)

where r_C1 and r_C2 are the equivalent series resistance (ESR) of the C₁ and C₂ capacitors, respectively; I_C1.rms and I_C2.rms are the RMS capacitor currents and are calculated as

$$\{\begin{array}{c}{I}_{C1.rms}=\sqrt{\frac{1}{2\pi }\left({{\displaystyle \int }}_{t_1}^{t_2}{i}_o{}^2\left(t\right)d_2\left(t\right)d\left(\omega t\right)+{{\displaystyle \int }}_{\pi }^{2\pi }{\left[I_{in}-i_{L2}\left(t\right)-i_o\left(t\right)\right]}^{2}d\left(\omega t\right)\right)}\\ I_{C2.rms}=\sqrt{\frac{1}{2\pi }\left({{\displaystyle \int }}_{\pi }^{2\pi }{\left[I_{in}-i_{L2}\left(t\right)\right]}^2{d}_4\left(t\right)d\left(\omega t\right)+{{\displaystyle \int }}_{\pi }^{2\pi }{I}_{in}{}^2\left[1-d_4\left(t\right)\right]d\left(\omega t\right)\right)}\end{array}$$

(52)

4. Comparison with Other Common-Ground Transformerless Inverters

Currently, the research literature is often focused on extending the buck–boost ability with higher efficiency, reducing the number of devices, and decreasing voltage stress across semiconductor devices. To show the potential capability of the proposed CGBBI topology, a comparative analysis between the proposed CGBBI topology and other common-ground transformerless inverters is presented in

Table 1. Comparison between the proposed CGBBI topology and other common-ground transformerless inverters.

	Inverter in [21]	Inverter in [22]	Inverter in [23]	Inverter in [24]	Inverter in [25]	Inverter in [28]	Inverter in [29]	Inverter in [30]	Proposed CGBBI
Switches	4	6	5	5	5	8	7	5	5
Diodes	2	5	0	4	3	0	1	3	3
Inductors	2	2	2	5	2	1	0	2	2
Capacitors	2	1	2	3	2	1	2	2	2
Total devices	10	14	9	17	12	10	10	12	12
Switches stress	S1 to S4: 2Vo	S1, S4: Vin S2, S3: Vo S5, S6: Vo	S1 to S5: Vin + Vo	S1 to S5: Vin + Vo	S1: Vin + Vo S2 to S5: Vo	S1: Vin S2: Vo S3: Vin S4, S7: Vin + Vo S5: Vo S6, S8: Vo	S1, S2: Vin S3: 3Vin S4, S5: 2Vin S6: 2Vin S7: 4Vin	S1, S2: Vin + Vo S3, S4: Vo S5: Vo	S1: Vin S2, S3, S5: Vo S4: Vin + Vo
HF-switches in each period	4P 4N	3P 3N	2P 2N	3P 1N	3P 1N	5P 3N	4P 5N	2P 1N	2P 1N
Diodes stress	-	D1, D4: Vin D2, D3, D5: Vo	-	D1 to D4: Vin + Vo	D1: Vin + Vo D2: Vin D3: Vo	-	D: Vin	D1: Vo D2: Vin + Vo D3: Vo − Vin	D1: Vin D2: Vo D3: Vin + Vo

P and N are the number of high-frequency switching in positive and negative half-line periods, respectively.

. It can be seen that the number of devices in the inverters proposed by [21,23] is lower than that of the inverters developed by [22,24,25], as well as the proposed CGBBI of this study. Moreover, the total number of devices in the proposed CGBBI is lower than that of the inverter in [22,24]. Having considered voltage stress across the power switches, the inverter developed by [22] and our proposed CGBBI have total switch voltage stress of 2V_in + 4V_o, which is lower than that of the inverter in [21,23,24,25]. As is clear from Table 1, the number of high-frequency switches in each period in the proposed CGBBI topology is the least when compared with other inverters. When comparing diode voltage stress values, it is revealed that the inverter used in [25] and the proposed CGBBI have lower voltage stress values than the inverters in [22,24]. Compared with the inverters in [28,29], the proposed CGBBI requires a smaller number of power switches than that in [28,29] and the number of high-frequency switches in each period in the inverters developed by [28,29] is higher than that of the proposed CGBBI. In addition, the number of devices in the inverter used in [30] is equal to that of the proposed CGBBI. However, the total voltage stress of semiconductor devices in the proposed CGBBI is smaller than that in the inverter [30]. Considering the comparison in terms of component count, the voltage stress on semiconductor devices, and the number of high-frequency switches, the proposed CGBBI topology is a better solution than other common-ground buck–boost inverters mentioned in the literature.

5. Simulation and Experiment Verifications

5.1. Simulation Results

The operating analysis of the proposed CGBBI topology was verified in the PSIM simulation version 9.1 [33]. The specifications for simulation are shown in

Table 2. Parameters of the proposed CGBBI topology.

Parameter	Symbol	Part No./Value
Input voltage range	Vin	60–240 V
Output Voltage	vo	110 Vrms
Output frequency	fo	50 Hz
Output Power	Po	500 W
Switching frequency	fsw	50 kHz
Capacitors	C1	5 µF/200 V
	C2	1 µF/450 V
Inductors	L1, L2	0.5 mH
Filter inductor	Lf	0.5 mH
MOSFETs	S1	IRFP4868PbF (300 V, 70 A, Rdson = 25.5 mΩ)
	S2, S3, S5	IRFP4668PbF (200 V, 130 A, Rdson = 8 mΩ)
	S4	IPW60R045CPA (600 V, 60 A, Rdson = 45 mΩ)
Diodes	D1	FF60UP30DN (300 V, 60 A, VF = 1.12 V)
	D2	STPS60SM200C (200 V, 30 A, VF = 0.7 V)
	D3	DSEI30-06A (600 V, 37 A, VF = 1.4 V)

. The drain-to-source on-resistance and body-diode threshold voltage of the MOSFETs S₁, S₄, and S₂, S₃, S₅ were set to 25.5 mΩ, 45 mΩ, and 8 mΩ, respectively. The forward voltage of diodes D₁ to D₃ was set to 1.12 V, 0.7 V, and 1.4 V, respectively. Figure 6 and Figure 7 present the simulation waveforms of the proposed CGBBI topology in both buck and boost operations. The RMS values of the output voltage and output frequency were set at 110 V and 50 Hz. The input voltage values were 60 V and 240 V. In the case of V_in = 60 V, the modulation index and maximum values of duty cycles were M = 2.58, D_1.max = 2.58, D_2.max = 0.61, D_4.max = 0.72. Additionally, with V_in = 240 V, the modulation index and maximum values of duty cycles were M = 0.64, D_1.max = 0.64, D_2.max = 0, D_4.max = 0.39. The high-switching frequency of semiconductor devices was 50 kHz. From the design guideline in Section 3, the parameters of passive devices were chosen as follows: L₁ = L₂ = 0.5 mH, C₁ = 5 µF, C₂ = 1 µF. The input voltage, capacitor C₂ voltage, output voltage, voltage stresses of semiconductor devices are shown in Figure 6 and Figure 7. Moreover, the THD values of the output voltage waveforms were measured at 1.2% and 0.5% for the input voltage of 60 V and 240 V, respectively. It can be observed that the simulation results well agreed with the theoretical analysis. The conduction and switching losses of the proposed CGBBI, together with the simulation results, are shown in

Table 3. The power loss of the proposed CGBBI with simulation.

Components	Vin = 60 V				Vin = 240 V
	Currents (A)		Losses (W)		Currents (A)		Losses (W)
	Average	RMS	Conduction	Switching	Average	RMS	Conduction	Switching
S1	4.1	7.08	1.28	0.75	1.04	2.4	0.15	1.25
S2	2.14	5.33	0.23	2.97	0	0	0	0
S3	2	4.67	0.17	2.77	2.05	3.26	0.09	2.84
S4	4.12	8.53	3.27	1.33	1.03	2.99	0.4	1.63
S5	2	4.54	0.16	2.77	2.05	3.65	0.11	2.84
D1	5.24 × 10−2	0.26	0.06	0.03	1.01	2.19	1.28	0.13
D2	2	4.67	1.9	0	2.05	3.26	1.68	0
D3	2	5.62	4.38	0.94	2.06	4.05	3.7	1.73
L1	4.15	7.09	2.01	-	2.05	3.25	0.42	-
L2	6.12	10.22	4.18	-	3.09	5.04	1.02	-
C1	1.9 × 10−3	4.77	0.11	-	3.86 × 10−3	1.77	0.02	-
C2	9.22 × 10−3	1.48	0	-	9.32 × 10−3	0.77	0	-
Ploss	-	-	29.31		-	-	19.29

. It can be seen that the simulation results are close to the power loss analysis.

5.2. Experimental Results

A 500 W prototype circuit was fabricated and tested to verify the performance of the proposed CGBBI topology. The specifications for testing are also shown in Table 2. Figure 8 presents the experimental waveforms of the proposed CGBBI topology when the inverter operated in boost mode. The maximum value of the output voltage was boosted to 155 V from an input voltage of 60 V, which corresponds to M = 2.58. Figure 8a shows the input voltage, capacitor C₂ voltage, and output voltage for the load value of 24 Ω and filter inductor of 0.5 mH. The capacitor voltage V_C2 was half-sinusoidal with DC offset V_in in the positive half of the output cycle. Therefore, the peak voltage across the capacitor C₂ was approximately 220 V. In the negative half of the output cycle, the voltage across the capacitor C₁ was equal to the input voltage. The RMS value and THD of the output voltage waveform were 109 V and 1.6%, respectively. Figure 8b shows the voltage stress on switches S₁, S₂, and the current of inductor L₁. Figure 8c shows the voltage stress on switches S₄, S₅, and the current of inductor L₂. The peak currents of inductors L₁ and L₂ were about 16 A and 23 A, respectively. The high-frequency ripple of inductors L₁ and L₂ current were about 2.5 A and 3 A, respectively. Figure 8d shows the voltage stress on diode D₁, the voltage stress on switch diodes S₃–D₂, and voltage stress on diode D₃. Similarly, the proposed CGBBI topology was tested with an input voltage of 240 V, as shown in Figure 9. It can be seen that the experimental results are verified with the simulation and the theoretical analyses.

Moreover, the efficiency of the proposed CGBBI topology was measured at V_in = 60 V and V_in = 240 V. In this case, the output power of the inverter changed from 25 W to 500 W. When V_in = 240 V, the proposed CGBBI topology achieved the highest efficiency of 96.1%. When the input voltage decreased to 60 V, the efficiency of the proposed CGBBI topology also achieved the highest efficiency of 95% at 350 W. From Figure 10, the EU efficiency of the proposed CGBBI topology can be obtained at 95.24%. The parameters for the power losses calculation are presented in

Table 4. Parameters for power loss analysis.

Parameters		Values
Inductors L1, L2	Core	CM777125 (142 nH/N2)
	Parastic Resistor	40 mΩ
Capacitors	ESR of C1	49 mΩ
	ESR of C2	14 mΩ
MOSFETs		IRFP4668PbF (200 V, 130 A, Rdson = 8 mΩ)
		IRFP4868PbF (300 V, 70 A, Rdson = 25.5 mΩ)
		IPW60R045CPA (600 V, 60 A, Rdson = 45 mΩ)
Diodes		STPS60SM200C (200 V, 30 A, VF = 0.7 V)
		FF60UP30DN (300 V, 60 A, VF = 1.12 V)
		DSEI30-06A (600 V, 37 A, VF = 1.4 V)

. Figure 11 depicts the power loss distribution of the proposed CGBBI when V_in = 60 V and 240 V, v_o = 110 Vrms, and P_o = 500 W.

6. Conclusions

In this article, a common-ground buck–boost inverter topology was introduced, and its theoretical analysis was discussed in detail. In the proposed inverter, there is no common-mode leakage current because the ground of the output side is directly connected to the negative of the DC input power source. The proposed common-ground buck–boost inverter topology also provides buck–boost capability by controlling the duty cycle of power switches. In addition, few power switches operated with high-switching frequency, so the efficiency of the proposed inverter can be improved. Furthermore, the simulation and experimental verification were presented with a 500 W prototype inverter. The results highlighted that the proposed inverter can steadily operate and have good performance.